1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_dp_types.h" 36 #include "dc_hw_types.h" 37 #include "dal_types.h" 38 #include "grph_object_defs.h" 39 40 #ifdef CONFIG_DRM_AMD_DC_HDCP 41 #include "dm_cp_psp.h" 42 #endif 43 44 /* forward declarations */ 45 struct dc_plane_state; 46 struct dc_stream_state; 47 struct dc_link; 48 struct dc_sink; 49 struct dal; 50 struct dc_dmub_srv; 51 52 /******************************** 53 * Environment definitions 54 ********************************/ 55 enum dce_environment { 56 DCE_ENV_PRODUCTION_DRV = 0, 57 /* Emulation on FPGA, in "Maximus" System. 58 * This environment enforces that *only* DC registers accessed. 59 * (access to non-DC registers will hang FPGA) */ 60 DCE_ENV_FPGA_MAXIMUS, 61 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 62 * requirements of Diagnostics team. */ 63 DCE_ENV_DIAG, 64 /* 65 * Guest VM system, DC HW may exist but is not virtualized and 66 * should not be used. SW support for VDI only. 67 */ 68 DCE_ENV_VIRTUAL_HW 69 }; 70 71 /* Note: use these macro definitions instead of direct comparison! */ 72 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ 73 (dce_environment == DCE_ENV_FPGA_MAXIMUS) 74 75 #define IS_DIAG_DC(dce_environment) \ 76 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG)) 77 78 struct dc_perf_trace { 79 unsigned long read_count; 80 unsigned long write_count; 81 unsigned long last_entry_read; 82 unsigned long last_entry_write; 83 }; 84 85 #define DC_MAX_EDID_BUFFER_SIZE 2048 86 #define DC_EDID_BLOCK_SIZE 128 87 #define MAX_SURFACE_NUM 4 88 #define NUM_PIXEL_FORMATS 10 89 #define MAX_REPEATER_CNT 8 90 91 #include "dc_ddc_types.h" 92 93 enum tiling_mode { 94 TILING_MODE_INVALID, 95 TILING_MODE_LINEAR, 96 TILING_MODE_TILED, 97 TILING_MODE_COUNT 98 }; 99 100 enum view_3d_format { 101 VIEW_3D_FORMAT_NONE = 0, 102 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 103 VIEW_3D_FORMAT_SIDE_BY_SIDE, 104 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 105 VIEW_3D_FORMAT_COUNT, 106 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 107 }; 108 109 enum plane_stereo_format { 110 PLANE_STEREO_FORMAT_NONE = 0, 111 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 112 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 113 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 114 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 115 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 116 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 117 }; 118 119 /* TODO: Find way to calculate number of bits 120 * Please increase if pixel_format enum increases 121 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 122 */ 123 124 enum dc_edid_connector_type { 125 DC_EDID_CONNECTOR_UNKNOWN = 0, 126 DC_EDID_CONNECTOR_ANALOG = 1, 127 DC_EDID_CONNECTOR_DIGITAL = 10, 128 DC_EDID_CONNECTOR_DVI = 11, 129 DC_EDID_CONNECTOR_HDMIA = 12, 130 DC_EDID_CONNECTOR_MDDI = 14, 131 DC_EDID_CONNECTOR_DISPLAYPORT = 15 132 }; 133 134 enum dc_edid_status { 135 EDID_OK, 136 EDID_BAD_INPUT, 137 EDID_NO_RESPONSE, 138 EDID_BAD_CHECKSUM, 139 EDID_THE_SAME, 140 EDID_FALL_BACK, 141 }; 142 143 enum act_return_status { 144 ACT_SUCCESS, 145 ACT_LINK_LOST, 146 ACT_FAILED 147 }; 148 149 /* audio capability from EDID*/ 150 struct dc_cea_audio_mode { 151 uint8_t format_code; /* ucData[0] [6:3]*/ 152 uint8_t channel_count; /* ucData[0] [2:0]*/ 153 uint8_t sample_rate; /* ucData[1]*/ 154 union { 155 uint8_t sample_size; /* for LPCM*/ 156 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 157 uint8_t max_bit_rate; 158 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 159 }; 160 }; 161 162 struct dc_edid { 163 uint32_t length; 164 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 165 }; 166 167 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 168 * is used. In this case we assume speaker location are: front left, front 169 * right and front center. */ 170 #define DEFAULT_SPEAKER_LOCATION 5 171 172 #define DC_MAX_AUDIO_DESC_COUNT 16 173 174 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 175 176 union display_content_support { 177 unsigned int raw; 178 struct { 179 unsigned int valid_content_type :1; 180 unsigned int game_content :1; 181 unsigned int cinema_content :1; 182 unsigned int photo_content :1; 183 unsigned int graphics_content :1; 184 unsigned int reserved :27; 185 } bits; 186 }; 187 188 struct dc_panel_patch { 189 unsigned int dppowerup_delay; 190 unsigned int extra_t12_ms; 191 unsigned int extra_delay_backlight_off; 192 unsigned int extra_t7_ms; 193 unsigned int skip_scdc_overwrite; 194 unsigned int delay_ignore_msa; 195 unsigned int disable_fec; 196 unsigned int extra_t3_ms; 197 unsigned int max_dsc_target_bpp_limit; 198 unsigned int skip_avmute; 199 }; 200 201 struct dc_edid_caps { 202 /* sink identification */ 203 uint16_t manufacturer_id; 204 uint16_t product_id; 205 uint32_t serial_number; 206 uint8_t manufacture_week; 207 uint8_t manufacture_year; 208 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 209 210 /* audio caps */ 211 uint8_t speaker_flags; 212 uint32_t audio_mode_count; 213 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 214 uint32_t audio_latency; 215 uint32_t video_latency; 216 217 union display_content_support content_support; 218 219 uint8_t qs_bit; 220 uint8_t qy_bit; 221 222 uint32_t max_tmds_clk_mhz; 223 224 /*HDMI 2.0 caps*/ 225 bool lte_340mcsc_scramble; 226 227 bool edid_hdmi; 228 bool hdr_supported; 229 230 struct dc_panel_patch panel_patch; 231 }; 232 233 struct dc_mode_flags { 234 /* note: part of refresh rate flag*/ 235 uint32_t INTERLACE :1; 236 /* native display timing*/ 237 uint32_t NATIVE :1; 238 /* preferred is the recommended mode, one per display */ 239 uint32_t PREFERRED :1; 240 /* true if this mode should use reduced blanking timings 241 *_not_ related to the Reduced Blanking adjustment*/ 242 uint32_t REDUCED_BLANKING :1; 243 /* note: part of refreshrate flag*/ 244 uint32_t VIDEO_OPTIMIZED_RATE :1; 245 /* should be reported to upper layers as mode_flags*/ 246 uint32_t PACKED_PIXEL_FORMAT :1; 247 /*< preferred view*/ 248 uint32_t PREFERRED_VIEW :1; 249 /* this timing should be used only in tiled mode*/ 250 uint32_t TILED_MODE :1; 251 uint32_t DSE_MODE :1; 252 /* Refresh rate divider when Miracast sink is using a 253 different rate than the output display device 254 Must be zero for wired displays and non-zero for 255 Miracast displays*/ 256 uint32_t MIRACAST_REFRESH_DIVIDER; 257 }; 258 259 260 enum dc_timing_source { 261 TIMING_SOURCE_UNDEFINED, 262 263 /* explicitly specifed by user, most important*/ 264 TIMING_SOURCE_USER_FORCED, 265 TIMING_SOURCE_USER_OVERRIDE, 266 TIMING_SOURCE_CUSTOM, 267 TIMING_SOURCE_EXPLICIT, 268 269 /* explicitly specified by the display device, more important*/ 270 TIMING_SOURCE_EDID_CEA_SVD_3D, 271 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 272 TIMING_SOURCE_EDID_CEA_SVD_420, 273 TIMING_SOURCE_EDID_DETAILED, 274 TIMING_SOURCE_EDID_ESTABLISHED, 275 TIMING_SOURCE_EDID_STANDARD, 276 TIMING_SOURCE_EDID_CEA_SVD, 277 TIMING_SOURCE_EDID_CVT_3BYTE, 278 TIMING_SOURCE_EDID_4BYTE, 279 TIMING_SOURCE_VBIOS, 280 TIMING_SOURCE_CV, 281 TIMING_SOURCE_TV, 282 TIMING_SOURCE_HDMI_VIC, 283 284 /* implicitly specified by display device, still safe but less important*/ 285 TIMING_SOURCE_DEFAULT, 286 287 /* only used for custom base modes */ 288 TIMING_SOURCE_CUSTOM_BASE, 289 290 /* these timing might not work, least important*/ 291 TIMING_SOURCE_RANGELIMIT, 292 TIMING_SOURCE_OS_FORCED, 293 TIMING_SOURCE_IMPLICIT, 294 295 /* only used by default mode list*/ 296 TIMING_SOURCE_BASICMODE, 297 298 TIMING_SOURCE_COUNT 299 }; 300 301 302 struct stereo_3d_features { 303 bool supported ; 304 bool allTimings ; 305 bool cloneMode ; 306 bool scaling ; 307 bool singleFrameSWPacked; 308 }; 309 310 enum dc_timing_support_method { 311 TIMING_SUPPORT_METHOD_UNDEFINED, 312 TIMING_SUPPORT_METHOD_EXPLICIT, 313 TIMING_SUPPORT_METHOD_IMPLICIT, 314 TIMING_SUPPORT_METHOD_NATIVE 315 }; 316 317 struct dc_mode_info { 318 uint32_t pixel_width; 319 uint32_t pixel_height; 320 uint32_t field_rate; 321 /* Vertical refresh rate for progressive modes. 322 * Field rate for interlaced modes.*/ 323 324 enum dc_timing_standard timing_standard; 325 enum dc_timing_source timing_source; 326 struct dc_mode_flags flags; 327 }; 328 329 enum dc_power_state { 330 DC_POWER_STATE_ON = 1, 331 DC_POWER_STATE_STANDBY, 332 DC_POWER_STATE_SUSPEND, 333 DC_POWER_STATE_OFF 334 }; 335 336 /* DC PowerStates */ 337 enum dc_video_power_state { 338 DC_VIDEO_POWER_UNSPECIFIED = 0, 339 DC_VIDEO_POWER_ON = 1, 340 DC_VIDEO_POWER_STANDBY, 341 DC_VIDEO_POWER_SUSPEND, 342 DC_VIDEO_POWER_OFF, 343 DC_VIDEO_POWER_HIBERNATE, 344 DC_VIDEO_POWER_SHUTDOWN, 345 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 346 DC_VIDEO_POWER_AFTER_RESET, 347 DC_VIDEO_POWER_MAXIMUM 348 }; 349 350 enum dc_acpi_cm_power_state { 351 DC_ACPI_CM_POWER_STATE_D0 = 1, 352 DC_ACPI_CM_POWER_STATE_D1 = 2, 353 DC_ACPI_CM_POWER_STATE_D2 = 4, 354 DC_ACPI_CM_POWER_STATE_D3 = 8 355 }; 356 357 enum dc_connection_type { 358 dc_connection_none, 359 dc_connection_single, 360 dc_connection_mst_branch, 361 dc_connection_sst_branch 362 }; 363 364 struct dc_csc_adjustments { 365 struct fixed31_32 contrast; 366 struct fixed31_32 saturation; 367 struct fixed31_32 brightness; 368 struct fixed31_32 hue; 369 }; 370 371 enum dpcd_downstream_port_max_bpc { 372 DOWN_STREAM_MAX_8BPC = 0, 373 DOWN_STREAM_MAX_10BPC, 374 DOWN_STREAM_MAX_12BPC, 375 DOWN_STREAM_MAX_16BPC 376 }; 377 378 379 enum link_training_offset { 380 DPRX = 0, 381 LTTPR_PHY_REPEATER1 = 1, 382 LTTPR_PHY_REPEATER2 = 2, 383 LTTPR_PHY_REPEATER3 = 3, 384 LTTPR_PHY_REPEATER4 = 4, 385 LTTPR_PHY_REPEATER5 = 5, 386 LTTPR_PHY_REPEATER6 = 6, 387 LTTPR_PHY_REPEATER7 = 7, 388 LTTPR_PHY_REPEATER8 = 8 389 }; 390 391 struct dc_lttpr_caps { 392 union dpcd_rev revision; 393 uint8_t mode; 394 uint8_t max_lane_count; 395 uint8_t max_link_rate; 396 uint8_t phy_repeater_cnt; 397 uint8_t max_ext_timeout; 398 #if defined(CONFIG_DRM_AMD_DC_DCN) 399 union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding; 400 union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates; 401 #endif 402 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; 403 }; 404 405 #if defined(CONFIG_DRM_AMD_DC_DCN) 406 struct dc_dongle_dfp_cap_ext { 407 bool supported; 408 uint16_t max_pixel_rate_in_mps; 409 uint16_t max_video_h_active_width; 410 uint16_t max_video_v_active_height; 411 struct dp_encoding_format_caps encoding_format_caps; 412 struct dp_color_depth_caps rgb_color_depth_caps; 413 struct dp_color_depth_caps ycbcr444_color_depth_caps; 414 struct dp_color_depth_caps ycbcr422_color_depth_caps; 415 struct dp_color_depth_caps ycbcr420_color_depth_caps; 416 }; 417 #endif 418 419 struct dc_dongle_caps { 420 /* dongle type (DP converter, CV smart dongle) */ 421 enum display_dongle_type dongle_type; 422 bool extendedCapValid; 423 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 424 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 425 bool is_dp_hdmi_s3d_converter; 426 bool is_dp_hdmi_ycbcr422_pass_through; 427 bool is_dp_hdmi_ycbcr420_pass_through; 428 bool is_dp_hdmi_ycbcr422_converter; 429 bool is_dp_hdmi_ycbcr420_converter; 430 uint32_t dp_hdmi_max_bpc; 431 uint32_t dp_hdmi_max_pixel_clk_in_khz; 432 #if defined(CONFIG_DRM_AMD_DC_DCN) 433 uint32_t dp_hdmi_frl_max_link_bw_in_kbps; 434 struct dc_dongle_dfp_cap_ext dfp_cap_ext; 435 #endif 436 }; 437 /* Scaling format */ 438 enum scaling_transformation { 439 SCALING_TRANSFORMATION_UNINITIALIZED, 440 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 441 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 442 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 443 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 444 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 445 SCALING_TRANSFORMATION_INVALID = 0x80000000, 446 447 /* Flag the first and last */ 448 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 449 SCALING_TRANSFORMATION_END = 450 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 451 }; 452 453 enum display_content_type { 454 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 455 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 456 DISPLAY_CONTENT_TYPE_PHOTO = 2, 457 DISPLAY_CONTENT_TYPE_CINEMA = 4, 458 DISPLAY_CONTENT_TYPE_GAME = 8 459 }; 460 461 enum cm_gamut_adjust_type { 462 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 463 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 464 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 465 }; 466 467 struct cm_grph_csc_adjustment { 468 struct fixed31_32 temperature_matrix[12]; 469 enum cm_gamut_adjust_type gamut_adjust_type; 470 enum cm_gamut_coef_format gamut_coef_format; 471 }; 472 473 /* writeback */ 474 struct dwb_stereo_params { 475 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 476 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 477 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 478 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 479 }; 480 481 struct dc_dwb_cnv_params { 482 unsigned int src_width; /* input active width */ 483 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 484 unsigned int crop_width; /* cropped window width at cnv output */ 485 bool crop_en; /* window cropping enable in cnv */ 486 unsigned int crop_height; /* cropped window height at cnv output */ 487 unsigned int crop_x; /* cropped window start x value at cnv output */ 488 unsigned int crop_y; /* cropped window start y value at cnv output */ 489 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 490 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 491 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 492 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 493 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 494 }; 495 496 struct dc_dwb_params { 497 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 498 unsigned int hdr_mult; /* must be in FP1.6.12 */ 499 struct cm_grph_csc_adjustment csc_params; 500 struct dwb_stereo_params stereo_params; 501 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 502 unsigned int dest_width; /* Destination width */ 503 unsigned int dest_height; /* Destination height */ 504 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 505 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 506 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 507 struct scaling_taps scaler_taps; /* Scaling taps */ 508 enum dwb_subsample_position subsample_position; 509 struct dc_transfer_func *out_transfer_func; 510 }; 511 512 /* audio*/ 513 514 union audio_sample_rates { 515 struct sample_rates { 516 uint8_t RATE_32:1; 517 uint8_t RATE_44_1:1; 518 uint8_t RATE_48:1; 519 uint8_t RATE_88_2:1; 520 uint8_t RATE_96:1; 521 uint8_t RATE_176_4:1; 522 uint8_t RATE_192:1; 523 } rate; 524 525 uint8_t all; 526 }; 527 528 struct audio_speaker_flags { 529 uint32_t FL_FR:1; 530 uint32_t LFE:1; 531 uint32_t FC:1; 532 uint32_t RL_RR:1; 533 uint32_t RC:1; 534 uint32_t FLC_FRC:1; 535 uint32_t RLC_RRC:1; 536 uint32_t SUPPORT_AI:1; 537 }; 538 539 struct audio_speaker_info { 540 uint32_t ALLSPEAKERS:7; 541 uint32_t SUPPORT_AI:1; 542 }; 543 544 545 struct audio_info_flags { 546 547 union { 548 549 struct audio_speaker_flags speaker_flags; 550 struct audio_speaker_info info; 551 552 uint8_t all; 553 }; 554 }; 555 556 enum audio_format_code { 557 AUDIO_FORMAT_CODE_FIRST = 1, 558 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 559 560 AUDIO_FORMAT_CODE_AC3, 561 /*Layers 1 & 2 */ 562 AUDIO_FORMAT_CODE_MPEG1, 563 /*MPEG1 Layer 3 */ 564 AUDIO_FORMAT_CODE_MP3, 565 /*multichannel */ 566 AUDIO_FORMAT_CODE_MPEG2, 567 AUDIO_FORMAT_CODE_AAC, 568 AUDIO_FORMAT_CODE_DTS, 569 AUDIO_FORMAT_CODE_ATRAC, 570 AUDIO_FORMAT_CODE_1BITAUDIO, 571 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 572 AUDIO_FORMAT_CODE_DTS_HD, 573 AUDIO_FORMAT_CODE_MAT_MLP, 574 AUDIO_FORMAT_CODE_DST, 575 AUDIO_FORMAT_CODE_WMAPRO, 576 AUDIO_FORMAT_CODE_LAST, 577 AUDIO_FORMAT_CODE_COUNT = 578 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 579 }; 580 581 struct audio_mode { 582 /* ucData[0] [6:3] */ 583 enum audio_format_code format_code; 584 /* ucData[0] [2:0] */ 585 uint8_t channel_count; 586 /* ucData[1] */ 587 union audio_sample_rates sample_rates; 588 union { 589 /* for LPCM */ 590 uint8_t sample_size; 591 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 592 uint8_t max_bit_rate; 593 /* for Audio Formats 9-15 */ 594 uint8_t vendor_specific; 595 }; 596 }; 597 598 struct audio_info { 599 struct audio_info_flags flags; 600 uint32_t video_latency; 601 uint32_t audio_latency; 602 uint32_t display_index; 603 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 604 uint32_t manufacture_id; 605 uint32_t product_id; 606 /* PortID used for ContainerID when defined */ 607 uint32_t port_id[2]; 608 uint32_t mode_count; 609 /* this field must be last in this struct */ 610 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 611 }; 612 struct audio_check { 613 unsigned int audio_packet_type; 614 unsigned int max_audiosample_rate; 615 unsigned int acat; 616 }; 617 enum dc_infoframe_type { 618 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 619 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 620 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 621 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 622 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 623 }; 624 625 struct dc_info_packet { 626 bool valid; 627 uint8_t hb0; 628 uint8_t hb1; 629 uint8_t hb2; 630 uint8_t hb3; 631 uint8_t sb[32]; 632 }; 633 634 struct dc_info_packet_128 { 635 bool valid; 636 uint8_t hb0; 637 uint8_t hb1; 638 uint8_t hb2; 639 uint8_t hb3; 640 uint8_t sb[128]; 641 }; 642 643 #define DC_PLANE_UPDATE_TIMES_MAX 10 644 645 struct dc_plane_flip_time { 646 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 647 unsigned int index; 648 unsigned int prev_update_time_in_us; 649 }; 650 651 enum dc_psr_state { 652 PSR_STATE0 = 0x0, 653 PSR_STATE1, 654 PSR_STATE1a, 655 PSR_STATE2, 656 PSR_STATE2a, 657 PSR_STATE2b, 658 PSR_STATE3, 659 PSR_STATE3Init, 660 PSR_STATE4, 661 PSR_STATE4a, 662 PSR_STATE4b, 663 PSR_STATE4c, 664 PSR_STATE4d, 665 PSR_STATE5, 666 PSR_STATE5a, 667 PSR_STATE5b, 668 PSR_STATE5c, 669 PSR_STATE_INVALID = 0xFF 670 }; 671 672 struct psr_config { 673 unsigned char psr_version; 674 unsigned int psr_rfb_setup_time; 675 bool psr_exit_link_training_required; 676 bool psr_frame_capture_indication_req; 677 unsigned int psr_sdp_transmit_line_num_deadline; 678 bool allow_smu_optimizations; 679 bool allow_multi_disp_optimizations; 680 }; 681 682 union dmcu_psr_level { 683 struct { 684 unsigned int SKIP_CRC:1; 685 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 686 unsigned int SKIP_PHY_POWER_DOWN:1; 687 unsigned int SKIP_AUX_ACK_CHECK:1; 688 unsigned int SKIP_CRTC_DISABLE:1; 689 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 690 unsigned int SKIP_SMU_NOTIFICATION:1; 691 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 692 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 693 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 694 unsigned int RESERVED:22; 695 } bits; 696 unsigned int u32all; 697 }; 698 699 enum physical_phy_id { 700 PHYLD_0, 701 PHYLD_1, 702 PHYLD_2, 703 PHYLD_3, 704 PHYLD_4, 705 PHYLD_5, 706 PHYLD_6, 707 PHYLD_7, 708 PHYLD_8, 709 PHYLD_9, 710 PHYLD_COUNT, 711 PHYLD_UNKNOWN = (-1L) 712 }; 713 714 enum phy_type { 715 PHY_TYPE_UNKNOWN = 1, 716 PHY_TYPE_PCIE_PHY = 2, 717 PHY_TYPE_UNIPHY = 3, 718 }; 719 720 struct psr_context { 721 /* ddc line */ 722 enum channel_id channel; 723 /* Transmitter id */ 724 enum transmitter transmitterId; 725 /* Engine Id is used for Dig Be source select */ 726 enum engine_id engineId; 727 /* Controller Id used for Dig Fe source select */ 728 enum controller_id controllerId; 729 /* Pcie or Uniphy */ 730 enum phy_type phyType; 731 /* Physical PHY Id used by SMU interpretation */ 732 enum physical_phy_id smuPhyId; 733 /* Vertical total pixels from crtc timing. 734 * This is used for static screen detection. 735 * ie. If we want to detect half a frame, 736 * we use this to determine the hyst lines. 737 */ 738 unsigned int crtcTimingVerticalTotal; 739 /* PSR supported from panel capabilities and 740 * current display configuration 741 */ 742 bool psrSupportedDisplayConfig; 743 /* Whether fast link training is supported by the panel */ 744 bool psrExitLinkTrainingRequired; 745 /* If RFB setup time is greater than the total VBLANK time, 746 * it is not possible for the sink to capture the video frame 747 * in the same frame the SDP is sent. In this case, 748 * the frame capture indication bit should be set and an extra 749 * static frame should be transmitted to the sink. 750 */ 751 bool psrFrameCaptureIndicationReq; 752 /* Set the last possible line SDP may be transmitted without violating 753 * the RFB setup time or entering the active video frame. 754 */ 755 unsigned int sdpTransmitLineNumDeadline; 756 /* The VSync rate in Hz used to calculate the 757 * step size for smooth brightness feature 758 */ 759 unsigned int vsync_rate_hz; 760 unsigned int skipPsrWaitForPllLock; 761 unsigned int numberOfControllers; 762 /* Unused, for future use. To indicate that first changed frame from 763 * state3 shouldn't result in psr_inactive, but rather to perform 764 * an automatic single frame rfb_update. 765 */ 766 bool rfb_update_auto_en; 767 /* Number of frame before entering static screen */ 768 unsigned int timehyst_frames; 769 /* Partial frames before entering static screen */ 770 unsigned int hyst_lines; 771 /* # of repeated AUX transaction attempts to make before 772 * indicating failure to the driver 773 */ 774 unsigned int aux_repeats; 775 /* Controls hw blocks to power down during PSR active state */ 776 union dmcu_psr_level psr_level; 777 /* Controls additional delay after remote frame capture before 778 * continuing powerd own 779 */ 780 unsigned int frame_delay; 781 bool allow_smu_optimizations; 782 bool allow_multi_disp_optimizations; 783 }; 784 785 struct colorspace_transform { 786 struct fixed31_32 matrix[12]; 787 bool enable_remap; 788 }; 789 790 enum i2c_mot_mode { 791 I2C_MOT_UNDEF, 792 I2C_MOT_TRUE, 793 I2C_MOT_FALSE 794 }; 795 796 struct AsicStateEx { 797 unsigned int memoryClock; 798 unsigned int displayClock; 799 unsigned int engineClock; 800 unsigned int maxSupportedDppClock; 801 unsigned int dppClock; 802 unsigned int socClock; 803 unsigned int dcfClockDeepSleep; 804 unsigned int fClock; 805 unsigned int phyClock; 806 }; 807 808 809 enum dc_clock_type { 810 DC_CLOCK_TYPE_DISPCLK = 0, 811 DC_CLOCK_TYPE_DPPCLK = 1, 812 }; 813 814 struct dc_clock_config { 815 uint32_t max_clock_khz; 816 uint32_t min_clock_khz; 817 uint32_t bw_requirequired_clock_khz; 818 uint32_t current_clock_khz;/*current clock in use*/ 819 }; 820 821 struct hw_asic_id { 822 uint32_t chip_id; 823 uint32_t chip_family; 824 uint32_t pci_revision_id; 825 uint32_t hw_internal_rev; 826 uint32_t vram_type; 827 uint32_t vram_width; 828 uint32_t feature_flags; 829 uint32_t fake_paths_num; 830 void *atombios_base_address; 831 }; 832 833 struct dc_context { 834 struct dc *dc; 835 836 void *driver_context; /* e.g. amdgpu_device */ 837 struct dc_perf_trace *perf_trace; 838 void *cgs_device; 839 840 enum dce_environment dce_environment; 841 struct hw_asic_id asic_id; 842 843 /* todo: below should probably move to dc. to facilitate removal 844 * of AS we will store these here 845 */ 846 enum dce_version dce_version; 847 struct dc_bios *dc_bios; 848 bool created_bios; 849 struct gpio_service *gpio_service; 850 uint32_t dc_sink_id_count; 851 uint32_t dc_stream_id_count; 852 uint32_t dc_edp_id_count; 853 uint64_t fbc_gpu_addr; 854 struct dc_dmub_srv *dmub_srv; 855 #ifdef CONFIG_DRM_AMD_DC_HDCP 856 struct cp_psp cp_psp; 857 #endif 858 859 }; 860 861 /* DSC DPCD capabilities */ 862 union dsc_slice_caps1 { 863 struct { 864 uint8_t NUM_SLICES_1 : 1; 865 uint8_t NUM_SLICES_2 : 1; 866 uint8_t RESERVED : 1; 867 uint8_t NUM_SLICES_4 : 1; 868 uint8_t NUM_SLICES_6 : 1; 869 uint8_t NUM_SLICES_8 : 1; 870 uint8_t NUM_SLICES_10 : 1; 871 uint8_t NUM_SLICES_12 : 1; 872 } bits; 873 uint8_t raw; 874 }; 875 876 union dsc_slice_caps2 { 877 struct { 878 uint8_t NUM_SLICES_16 : 1; 879 uint8_t NUM_SLICES_20 : 1; 880 uint8_t NUM_SLICES_24 : 1; 881 uint8_t RESERVED : 5; 882 } bits; 883 uint8_t raw; 884 }; 885 886 union dsc_color_formats { 887 struct { 888 uint8_t RGB : 1; 889 uint8_t YCBCR_444 : 1; 890 uint8_t YCBCR_SIMPLE_422 : 1; 891 uint8_t YCBCR_NATIVE_422 : 1; 892 uint8_t YCBCR_NATIVE_420 : 1; 893 uint8_t RESERVED : 3; 894 } bits; 895 uint8_t raw; 896 }; 897 898 union dsc_color_depth { 899 struct { 900 uint8_t RESERVED1 : 1; 901 uint8_t COLOR_DEPTH_8_BPC : 1; 902 uint8_t COLOR_DEPTH_10_BPC : 1; 903 uint8_t COLOR_DEPTH_12_BPC : 1; 904 uint8_t RESERVED2 : 3; 905 } bits; 906 uint8_t raw; 907 }; 908 909 struct dsc_dec_dpcd_caps { 910 bool is_dsc_supported; 911 uint8_t dsc_version; 912 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 913 union dsc_slice_caps1 slice_caps1; 914 union dsc_slice_caps2 slice_caps2; 915 int32_t lb_bit_depth; 916 bool is_block_pred_supported; 917 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 918 union dsc_color_formats color_formats; 919 union dsc_color_depth color_depth; 920 int32_t throughput_mode_0_mps; /* In MPs */ 921 int32_t throughput_mode_1_mps; /* In MPs */ 922 int32_t max_slice_width; 923 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 924 925 /* Extended DSC caps */ 926 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 927 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 928 uint32_t branch_max_line_width; 929 bool is_dp; 930 }; 931 932 struct dc_golden_table { 933 uint16_t dc_golden_table_ver; 934 uint32_t aux_dphy_rx_control0_val; 935 uint32_t aux_dphy_tx_control_val; 936 uint32_t aux_dphy_rx_control1_val; 937 uint32_t dc_gpio_aux_ctrl_0_val; 938 uint32_t dc_gpio_aux_ctrl_1_val; 939 uint32_t dc_gpio_aux_ctrl_2_val; 940 uint32_t dc_gpio_aux_ctrl_3_val; 941 uint32_t dc_gpio_aux_ctrl_4_val; 942 uint32_t dc_gpio_aux_ctrl_5_val; 943 }; 944 945 enum dc_gpu_mem_alloc_type { 946 DC_MEM_ALLOC_TYPE_GART, 947 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 948 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 949 DC_MEM_ALLOC_TYPE_AGP 950 }; 951 952 enum dc_psr_version { 953 DC_PSR_VERSION_1 = 0, 954 DC_PSR_VERSION_SU_1 = 1, 955 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 956 }; 957 958 /* Possible values of display_endpoint_id.endpoint */ 959 enum display_endpoint_type { 960 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 961 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 962 DISPLAY_ENDPOINT_UNKNOWN = -1 963 }; 964 965 /* Extends graphics_object_id with an additional member 'ep_type' for 966 * distinguishing between physical endpoints (with entries in BIOS connector table) and 967 * logical endpoints. 968 */ 969 struct display_endpoint_id { 970 struct graphics_object_id link_id; 971 enum display_endpoint_type ep_type; 972 }; 973 974 #endif /* DC_TYPES_H_ */ 975