1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_STREAM_H_ 27 #define DC_STREAM_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 32 /******************************************************************************* 33 * Stream Interfaces 34 ******************************************************************************/ 35 struct timing_sync_info { 36 int group_id; 37 int group_size; 38 bool master; 39 }; 40 41 struct dc_stream_status { 42 int primary_otg_inst; 43 int stream_enc_inst; 44 int plane_count; 45 int audio_inst; 46 struct timing_sync_info timing_sync_info; 47 struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; 48 }; 49 50 // TODO: References to this needs to be removed.. 51 struct freesync_context { 52 bool dummy; 53 }; 54 55 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 56 enum hubp_dmdata_mode { 57 DMDATA_SW_MODE, 58 DMDATA_HW_MODE 59 }; 60 61 struct dc_dmdata_attributes { 62 /* Specifies whether dynamic meta data will be updated by software 63 * or has to be fetched by hardware (DMA mode) 64 */ 65 enum hubp_dmdata_mode dmdata_mode; 66 /* Specifies if current dynamic meta data is to be used only for the current frame */ 67 bool dmdata_repeat; 68 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ 69 uint32_t dmdata_size; 70 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ 71 bool dmdata_updated; 72 /* If hardware mode is used, the base address where DMDATA surface is located */ 73 PHYSICAL_ADDRESS_LOC address; 74 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ 75 bool dmdata_qos_mode; 76 /* If qos_mode = 1, this is the QOS value to be used: */ 77 uint32_t dmdata_qos_level; 78 /* Specifies the value in unit of REFCLK cycles to be added to the 79 * current time to produce the Amortized deadline for Dynamic Metadata chunk request 80 */ 81 uint32_t dmdata_dl_delta; 82 /* An unbounded array of uint32s, represents software dmdata to be loaded */ 83 uint32_t *dmdata_sw_data; 84 }; 85 #endif 86 87 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 88 struct dc_writeback_info { 89 bool wb_enabled; 90 int dwb_pipe_inst; 91 struct dc_dwb_params dwb_params; 92 struct mcif_buf_params mcif_buf_params; 93 }; 94 95 struct dc_writeback_update { 96 unsigned int num_wb_info; 97 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 98 }; 99 #endif 100 101 enum vertical_interrupt_ref_point { 102 START_V_UPDATE = 0, 103 START_V_SYNC, 104 INVALID_POINT 105 106 //For now, only v_update interrupt is used. 107 //START_V_BLANK, 108 //START_V_ACTIVE 109 }; 110 111 struct periodic_interrupt_config { 112 enum vertical_interrupt_ref_point ref_point; 113 int lines_offset; 114 }; 115 116 union stream_update_flags { 117 struct { 118 uint32_t scaling:1; 119 uint32_t out_tf:1; 120 uint32_t out_csc:1; 121 uint32_t abm_level:1; 122 uint32_t dpms_off:1; 123 uint32_t gamut_remap:1; 124 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 125 uint32_t wb_update:1; 126 #endif 127 } bits; 128 129 uint32_t raw; 130 }; 131 132 struct dc_stream_state { 133 // sink is deprecated, new code should not reference 134 // this pointer 135 struct dc_sink *sink; 136 137 struct dc_link *link; 138 struct dc_panel_patch sink_patches; 139 union display_content_support content_support; 140 struct dc_crtc_timing timing; 141 struct dc_crtc_timing_adjust adjust; 142 struct dc_info_packet vrr_infopacket; 143 struct dc_info_packet vsc_infopacket; 144 struct dc_info_packet vsp_infopacket; 145 146 struct rect src; /* composition area */ 147 struct rect dst; /* stream addressable area */ 148 149 // TODO: References to this needs to be removed.. 150 struct freesync_context freesync_ctx; 151 152 struct audio_info audio_info; 153 154 struct dc_info_packet hdr_static_metadata; 155 PHYSICAL_ADDRESS_LOC dmdata_address; 156 bool use_dynamic_meta; 157 158 struct dc_transfer_func *out_transfer_func; 159 struct colorspace_transform gamut_remap_matrix; 160 struct dc_csc_transform csc_color_matrix; 161 162 enum dc_color_space output_color_space; 163 enum dc_dither_option dither_option; 164 165 enum view_3d_format view_format; 166 167 bool use_vsc_sdp_for_colorimetry; 168 bool ignore_msa_timing_param; 169 bool converter_disable_audio; 170 uint8_t qs_bit; 171 uint8_t qy_bit; 172 173 /* TODO: custom INFO packets */ 174 /* TODO: ABM info (DMCU) */ 175 /* PSR info */ 176 unsigned char psr_version; 177 /* TODO: CEA VIC */ 178 179 /* DMCU info */ 180 unsigned int abm_level; 181 182 struct periodic_interrupt_config periodic_interrupt0; 183 struct periodic_interrupt_config periodic_interrupt1; 184 185 /* from core_stream struct */ 186 struct dc_context *ctx; 187 188 /* used by DCP and FMT */ 189 struct bit_depth_reduction_params bit_depth_params; 190 struct clamping_and_pixel_encoding_params clamping; 191 192 int phy_pix_clk; 193 enum signal_type signal; 194 bool dpms_off; 195 196 void *dm_stream_context; 197 198 struct dc_cursor_attributes cursor_attributes; 199 struct dc_cursor_position cursor_position; 200 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 201 202 /* from stream struct */ 203 struct kref refcount; 204 205 struct crtc_trigger_info triggered_crtc_reset; 206 207 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 208 /* writeback */ 209 unsigned int num_wb_info; 210 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 211 #endif 212 /* Computed state bits */ 213 bool mode_changed : 1; 214 215 /* Output from DC when stream state is committed or altered 216 * DC may only access these values during: 217 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams 218 * values may not change outside of those calls 219 */ 220 struct { 221 // For interrupt management, some hardware instance 222 // offsets need to be exposed to DM 223 uint8_t otg_offset; 224 } out; 225 226 bool apply_edp_fast_boot_optimization; 227 bool apply_seamless_boot_optimization; 228 229 uint32_t stream_id; 230 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 231 bool is_dsc_enabled; 232 #endif 233 union stream_update_flags update_flags; 234 }; 235 236 #define ABM_LEVEL_IMMEDIATE_DISABLE 0xFFFFFFFF 237 238 struct dc_stream_update { 239 struct dc_stream_state *stream; 240 241 struct rect src; 242 struct rect dst; 243 struct dc_transfer_func *out_transfer_func; 244 struct dc_info_packet *hdr_static_metadata; 245 unsigned int *abm_level; 246 247 struct periodic_interrupt_config *periodic_interrupt0; 248 struct periodic_interrupt_config *periodic_interrupt1; 249 250 struct dc_info_packet *vrr_infopacket; 251 struct dc_info_packet *vsc_infopacket; 252 struct dc_info_packet *vsp_infopacket; 253 254 bool *dpms_off; 255 256 struct colorspace_transform *gamut_remap; 257 enum dc_color_space *output_color_space; 258 enum dc_dither_option *dither_option; 259 260 struct dc_csc_transform *output_csc_transform; 261 262 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 263 struct dc_writeback_update *wb_update; 264 #endif 265 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) 266 struct dc_dsc_config *dsc_config; 267 #endif 268 }; 269 270 bool dc_is_stream_unchanged( 271 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 272 bool dc_is_stream_scaling_unchanged( 273 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 274 275 /* 276 * Set up surface attributes and associate to a stream 277 * The surfaces parameter is an absolute set of all surface active for the stream. 278 * If no surfaces are provided, the stream will be blanked; no memory read. 279 * Any flip related attribute changes must be done through this interface. 280 * 281 * After this call: 282 * Surfaces attributes are programmed and configured to be composed into stream. 283 * This does not trigger a flip. No surface address is programmed. 284 */ 285 286 void dc_commit_updates_for_stream(struct dc *dc, 287 struct dc_surface_update *srf_updates, 288 int surface_count, 289 struct dc_stream_state *stream, 290 struct dc_stream_update *stream_update, 291 struct dc_state *state); 292 /* 293 * Log the current stream state. 294 */ 295 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream); 296 297 uint8_t dc_get_current_stream_count(struct dc *dc); 298 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); 299 300 /* 301 * Return the current frame counter. 302 */ 303 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); 304 305 /* 306 * Send dp sdp message. 307 */ 308 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 309 const uint8_t *custom_sdp_message, 310 unsigned int sdp_message_size); 311 312 /* TODO: Return parsed values rather than direct register read 313 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos) 314 * being refactored properly to be dce-specific 315 */ 316 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 317 uint32_t *v_blank_start, 318 uint32_t *v_blank_end, 319 uint32_t *h_position, 320 uint32_t *v_position); 321 322 enum dc_status dc_add_stream_to_ctx( 323 struct dc *dc, 324 struct dc_state *new_ctx, 325 struct dc_stream_state *stream); 326 327 enum dc_status dc_remove_stream_from_ctx( 328 struct dc *dc, 329 struct dc_state *new_ctx, 330 struct dc_stream_state *stream); 331 332 333 bool dc_add_plane_to_context( 334 const struct dc *dc, 335 struct dc_stream_state *stream, 336 struct dc_plane_state *plane_state, 337 struct dc_state *context); 338 339 bool dc_remove_plane_from_context( 340 const struct dc *dc, 341 struct dc_stream_state *stream, 342 struct dc_plane_state *plane_state, 343 struct dc_state *context); 344 345 bool dc_rem_all_planes_for_stream( 346 const struct dc *dc, 347 struct dc_stream_state *stream, 348 struct dc_state *context); 349 350 bool dc_add_all_planes_for_stream( 351 const struct dc *dc, 352 struct dc_stream_state *stream, 353 struct dc_plane_state * const *plane_states, 354 int plane_count, 355 struct dc_state *context); 356 357 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 358 bool dc_stream_add_writeback(struct dc *dc, 359 struct dc_stream_state *stream, 360 struct dc_writeback_info *wb_info); 361 bool dc_stream_remove_writeback(struct dc *dc, 362 struct dc_stream_state *stream, 363 uint32_t dwb_pipe_inst); 364 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); 365 bool dc_stream_set_dynamic_metadata(struct dc *dc, 366 struct dc_stream_state *stream, 367 struct dc_dmdata_attributes *dmdata_attr); 368 #endif 369 370 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); 371 372 /* 373 * Set up streams and links associated to drive sinks 374 * The streams parameter is an absolute set of all active streams. 375 * 376 * After this call: 377 * Phy, Encoder, Timing Generator are programmed and enabled. 378 * New streams are enabled with blank stream; no memory read. 379 */ 380 /* 381 * Enable stereo when commit_streams is not required, 382 * for example, frame alternate. 383 */ 384 bool dc_enable_stereo( 385 struct dc *dc, 386 struct dc_state *context, 387 struct dc_stream_state *streams[], 388 uint8_t stream_count); 389 390 391 enum surface_update_type dc_check_update_surfaces_for_stream( 392 struct dc *dc, 393 struct dc_surface_update *updates, 394 int surface_count, 395 struct dc_stream_update *stream_update, 396 const struct dc_stream_status *stream_status); 397 398 /** 399 * Create a new default stream for the requested sink 400 */ 401 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); 402 403 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream); 404 405 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink); 406 407 void dc_stream_retain(struct dc_stream_state *dc_stream); 408 void dc_stream_release(struct dc_stream_state *dc_stream); 409 410 struct dc_stream_status *dc_stream_get_status_from_state( 411 struct dc_state *state, 412 struct dc_stream_state *stream); 413 struct dc_stream_status *dc_stream_get_status( 414 struct dc_stream_state *dc_stream); 415 416 /******************************************************************************* 417 * Cursor interfaces - To manages the cursor within a stream 418 ******************************************************************************/ 419 /* TODO: Deprecated once we switch to dc_set_cursor_position */ 420 bool dc_stream_set_cursor_attributes( 421 struct dc_stream_state *stream, 422 const struct dc_cursor_attributes *attributes); 423 424 bool dc_stream_set_cursor_position( 425 struct dc_stream_state *stream, 426 const struct dc_cursor_position *position); 427 428 429 bool dc_stream_adjust_vmin_vmax(struct dc *dc, 430 struct dc_stream_state *stream, 431 struct dc_crtc_timing_adjust *adjust); 432 433 bool dc_stream_get_crtc_position(struct dc *dc, 434 struct dc_stream_state **stream, 435 int num_streams, 436 unsigned int *v_pos, 437 unsigned int *nom_v_pos); 438 439 bool dc_stream_configure_crc(struct dc *dc, 440 struct dc_stream_state *stream, 441 bool enable, 442 bool continuous); 443 444 bool dc_stream_get_crc(struct dc *dc, 445 struct dc_stream_state *stream, 446 uint32_t *r_cr, 447 uint32_t *g_y, 448 uint32_t *b_cb); 449 450 void dc_stream_set_static_screen_events(struct dc *dc, 451 struct dc_stream_state **stream, 452 int num_streams, 453 const struct dc_static_screen_events *events); 454 455 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, 456 enum dc_dynamic_expansion option); 457 458 void dc_stream_set_dither_option(struct dc_stream_state *stream, 459 enum dc_dither_option option); 460 461 bool dc_stream_set_gamut_remap(struct dc *dc, 462 const struct dc_stream_state *stream); 463 464 bool dc_stream_program_csc_matrix(struct dc *dc, 465 struct dc_stream_state *stream); 466 467 bool dc_stream_get_crtc_position(struct dc *dc, 468 struct dc_stream_state **stream, 469 int num_streams, 470 unsigned int *v_pos, 471 unsigned int *nom_v_pos); 472 473 #endif /* DC_STREAM_H_ */ 474