1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_STREAM_H_ 27 #define DC_STREAM_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 32 /******************************************************************************* 33 * Stream Interfaces 34 ******************************************************************************/ 35 struct timing_sync_info { 36 int group_id; 37 int group_size; 38 bool master; 39 }; 40 41 struct dc_stream_status { 42 int primary_otg_inst; 43 int stream_enc_inst; 44 int plane_count; 45 int audio_inst; 46 struct timing_sync_info timing_sync_info; 47 struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; 48 bool is_abm_supported; 49 }; 50 51 // TODO: References to this needs to be removed.. 52 struct freesync_context { 53 bool dummy; 54 }; 55 56 enum hubp_dmdata_mode { 57 DMDATA_SW_MODE, 58 DMDATA_HW_MODE 59 }; 60 61 struct dc_dmdata_attributes { 62 /* Specifies whether dynamic meta data will be updated by software 63 * or has to be fetched by hardware (DMA mode) 64 */ 65 enum hubp_dmdata_mode dmdata_mode; 66 /* Specifies if current dynamic meta data is to be used only for the current frame */ 67 bool dmdata_repeat; 68 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ 69 uint32_t dmdata_size; 70 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ 71 bool dmdata_updated; 72 /* If hardware mode is used, the base address where DMDATA surface is located */ 73 PHYSICAL_ADDRESS_LOC address; 74 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ 75 bool dmdata_qos_mode; 76 /* If qos_mode = 1, this is the QOS value to be used: */ 77 uint32_t dmdata_qos_level; 78 /* Specifies the value in unit of REFCLK cycles to be added to the 79 * current time to produce the Amortized deadline for Dynamic Metadata chunk request 80 */ 81 uint32_t dmdata_dl_delta; 82 /* An unbounded array of uint32s, represents software dmdata to be loaded */ 83 uint32_t *dmdata_sw_data; 84 }; 85 86 struct dc_writeback_info { 87 bool wb_enabled; 88 int dwb_pipe_inst; 89 struct dc_dwb_params dwb_params; 90 struct mcif_buf_params mcif_buf_params; 91 struct mcif_warmup_params mcif_warmup_params; 92 /* the plane that is the input to TOP_MUX for MPCC that is the DWB source */ 93 struct dc_plane_state *writeback_source_plane; 94 /* source MPCC instance. for use by internally by dc */ 95 int mpcc_inst; 96 }; 97 98 struct dc_writeback_update { 99 unsigned int num_wb_info; 100 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 101 }; 102 103 enum vertical_interrupt_ref_point { 104 START_V_UPDATE = 0, 105 START_V_SYNC, 106 INVALID_POINT 107 108 //For now, only v_update interrupt is used. 109 //START_V_BLANK, 110 //START_V_ACTIVE 111 }; 112 113 struct periodic_interrupt_config { 114 enum vertical_interrupt_ref_point ref_point; 115 int lines_offset; 116 }; 117 118 struct dc_mst_stream_bw_update { 119 bool is_increase; // is bandwidth reduced or increased 120 uint32_t mst_stream_bw; // new mst bandwidth in kbps 121 }; 122 123 union stream_update_flags { 124 struct { 125 uint32_t scaling:1; 126 uint32_t out_tf:1; 127 uint32_t out_csc:1; 128 uint32_t abm_level:1; 129 uint32_t dpms_off:1; 130 uint32_t gamut_remap:1; 131 uint32_t wb_update:1; 132 uint32_t dsc_changed : 1; 133 uint32_t mst_bw : 1; 134 uint32_t crtc_timing_adjust : 1; 135 } bits; 136 137 uint32_t raw; 138 }; 139 140 struct test_pattern { 141 enum dp_test_pattern type; 142 enum dp_test_pattern_color_space color_space; 143 struct link_training_settings const *p_link_settings; 144 unsigned char const *p_custom_pattern; 145 unsigned int cust_pattern_size; 146 }; 147 148 #ifdef CONFIG_DRM_AMD_DC_DCN 149 #define SUBVP_DRR_MARGIN_US 500 // 500us for DRR margin (SubVP + DRR) 150 151 enum mall_stream_type { 152 SUBVP_NONE, // subvp not in use 153 SUBVP_MAIN, // subvp in use, this stream is main stream 154 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream 155 }; 156 157 struct mall_stream_config { 158 /* MALL stream config to indicate if the stream is phantom or not. 159 * We will use a phantom stream to indicate that the pipe is phantom. 160 */ 161 enum mall_stream_type type; 162 struct dc_stream_state *paired_stream; // master / slave stream 163 }; 164 #endif 165 166 struct dc_stream_state { 167 // sink is deprecated, new code should not reference 168 // this pointer 169 struct dc_sink *sink; 170 171 struct dc_link *link; 172 /* For dynamic link encoder assignment, update the link encoder assigned to 173 * a stream via the volatile dc_state rather than the static dc_link. 174 */ 175 struct link_encoder *link_enc; 176 struct dc_panel_patch sink_patches; 177 union display_content_support content_support; 178 struct dc_crtc_timing timing; 179 struct dc_crtc_timing_adjust adjust; 180 struct dc_info_packet vrr_infopacket; 181 struct dc_info_packet vsc_infopacket; 182 struct dc_info_packet vsp_infopacket; 183 uint8_t dsc_packed_pps[128]; 184 struct rect src; /* composition area */ 185 struct rect dst; /* stream addressable area */ 186 187 // TODO: References to this needs to be removed.. 188 struct freesync_context freesync_ctx; 189 190 struct audio_info audio_info; 191 192 struct dc_info_packet hdr_static_metadata; 193 PHYSICAL_ADDRESS_LOC dmdata_address; 194 bool use_dynamic_meta; 195 196 struct dc_transfer_func *out_transfer_func; 197 struct colorspace_transform gamut_remap_matrix; 198 struct dc_csc_transform csc_color_matrix; 199 200 enum dc_color_space output_color_space; 201 enum dc_dither_option dither_option; 202 203 enum view_3d_format view_format; 204 205 bool use_vsc_sdp_for_colorimetry; 206 bool ignore_msa_timing_param; 207 208 bool freesync_on_desktop; 209 210 bool converter_disable_audio; 211 uint8_t qs_bit; 212 uint8_t qy_bit; 213 214 /* TODO: custom INFO packets */ 215 /* TODO: ABM info (DMCU) */ 216 /* TODO: CEA VIC */ 217 218 /* DMCU info */ 219 unsigned int abm_level; 220 221 struct periodic_interrupt_config periodic_interrupt0; 222 struct periodic_interrupt_config periodic_interrupt1; 223 224 /* from core_stream struct */ 225 struct dc_context *ctx; 226 227 /* used by DCP and FMT */ 228 struct bit_depth_reduction_params bit_depth_params; 229 struct clamping_and_pixel_encoding_params clamping; 230 231 int phy_pix_clk; 232 enum signal_type signal; 233 bool dpms_off; 234 235 void *dm_stream_context; 236 237 struct dc_cursor_attributes cursor_attributes; 238 struct dc_cursor_position cursor_position; 239 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 240 241 /* from stream struct */ 242 struct kref refcount; 243 244 struct crtc_trigger_info triggered_crtc_reset; 245 246 /* writeback */ 247 unsigned int num_wb_info; 248 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 249 const struct dc_transfer_func *func_shaper; 250 const struct dc_3dlut *lut3d_func; 251 /* Computed state bits */ 252 bool mode_changed : 1; 253 254 /* Output from DC when stream state is committed or altered 255 * DC may only access these values during: 256 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams 257 * values may not change outside of those calls 258 */ 259 struct { 260 // For interrupt management, some hardware instance 261 // offsets need to be exposed to DM 262 uint8_t otg_offset; 263 } out; 264 265 bool apply_edp_fast_boot_optimization; 266 bool apply_seamless_boot_optimization; 267 uint32_t apply_boot_odm_mode; 268 269 uint32_t stream_id; 270 271 struct test_pattern test_pattern; 272 union stream_update_flags update_flags; 273 274 bool has_non_synchronizable_pclk; 275 bool vblank_synchronized; 276 #ifdef CONFIG_DRM_AMD_DC_DCN 277 struct mall_stream_config mall_stream_config; 278 #endif 279 }; 280 281 #define ABM_LEVEL_IMMEDIATE_DISABLE 255 282 283 struct dc_stream_update { 284 struct dc_stream_state *stream; 285 286 struct rect src; 287 struct rect dst; 288 struct dc_transfer_func *out_transfer_func; 289 struct dc_info_packet *hdr_static_metadata; 290 unsigned int *abm_level; 291 292 struct periodic_interrupt_config *periodic_interrupt0; 293 struct periodic_interrupt_config *periodic_interrupt1; 294 295 struct dc_info_packet *vrr_infopacket; 296 struct dc_info_packet *vsc_infopacket; 297 struct dc_info_packet *vsp_infopacket; 298 299 bool *dpms_off; 300 bool integer_scaling_update; 301 302 struct colorspace_transform *gamut_remap; 303 enum dc_color_space *output_color_space; 304 enum dc_dither_option *dither_option; 305 306 struct dc_csc_transform *output_csc_transform; 307 308 struct dc_writeback_update *wb_update; 309 struct dc_dsc_config *dsc_config; 310 struct dc_mst_stream_bw_update *mst_bw_update; 311 struct dc_transfer_func *func_shaper; 312 struct dc_3dlut *lut3d_func; 313 314 struct test_pattern *pending_test_pattern; 315 struct dc_crtc_timing_adjust *crtc_timing_adjust; 316 }; 317 318 bool dc_is_stream_unchanged( 319 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 320 bool dc_is_stream_scaling_unchanged( 321 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 322 323 /* 324 * Set up surface attributes and associate to a stream 325 * The surfaces parameter is an absolute set of all surface active for the stream. 326 * If no surfaces are provided, the stream will be blanked; no memory read. 327 * Any flip related attribute changes must be done through this interface. 328 * 329 * After this call: 330 * Surfaces attributes are programmed and configured to be composed into stream. 331 * This does not trigger a flip. No surface address is programmed. 332 */ 333 334 void dc_commit_updates_for_stream(struct dc *dc, 335 struct dc_surface_update *srf_updates, 336 int surface_count, 337 struct dc_stream_state *stream, 338 struct dc_stream_update *stream_update, 339 struct dc_state *state); 340 /* 341 * Log the current stream state. 342 */ 343 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream); 344 345 uint8_t dc_get_current_stream_count(struct dc *dc); 346 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); 347 struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link); 348 349 /* 350 * Return the current frame counter. 351 */ 352 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); 353 354 /* 355 * Send dp sdp message. 356 */ 357 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 358 const uint8_t *custom_sdp_message, 359 unsigned int sdp_message_size); 360 361 /* TODO: Return parsed values rather than direct register read 362 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos) 363 * being refactored properly to be dce-specific 364 */ 365 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 366 uint32_t *v_blank_start, 367 uint32_t *v_blank_end, 368 uint32_t *h_position, 369 uint32_t *v_position); 370 371 enum dc_status dc_add_stream_to_ctx( 372 struct dc *dc, 373 struct dc_state *new_ctx, 374 struct dc_stream_state *stream); 375 376 enum dc_status dc_remove_stream_from_ctx( 377 struct dc *dc, 378 struct dc_state *new_ctx, 379 struct dc_stream_state *stream); 380 381 382 bool dc_add_plane_to_context( 383 const struct dc *dc, 384 struct dc_stream_state *stream, 385 struct dc_plane_state *plane_state, 386 struct dc_state *context); 387 388 bool dc_remove_plane_from_context( 389 const struct dc *dc, 390 struct dc_stream_state *stream, 391 struct dc_plane_state *plane_state, 392 struct dc_state *context); 393 394 bool dc_rem_all_planes_for_stream( 395 const struct dc *dc, 396 struct dc_stream_state *stream, 397 struct dc_state *context); 398 399 bool dc_add_all_planes_for_stream( 400 const struct dc *dc, 401 struct dc_stream_state *stream, 402 struct dc_plane_state * const *plane_states, 403 int plane_count, 404 struct dc_state *context); 405 406 bool dc_stream_add_writeback(struct dc *dc, 407 struct dc_stream_state *stream, 408 struct dc_writeback_info *wb_info); 409 410 bool dc_stream_remove_writeback(struct dc *dc, 411 struct dc_stream_state *stream, 412 uint32_t dwb_pipe_inst); 413 414 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 415 struct dc_state *state, 416 struct dc_stream_state *stream); 417 418 bool dc_stream_warmup_writeback(struct dc *dc, 419 int num_dwb, 420 struct dc_writeback_info *wb_info); 421 422 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); 423 424 bool dc_stream_set_dynamic_metadata(struct dc *dc, 425 struct dc_stream_state *stream, 426 struct dc_dmdata_attributes *dmdata_attr); 427 428 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); 429 430 /* 431 * Set up streams and links associated to drive sinks 432 * The streams parameter is an absolute set of all active streams. 433 * 434 * After this call: 435 * Phy, Encoder, Timing Generator are programmed and enabled. 436 * New streams are enabled with blank stream; no memory read. 437 */ 438 /* 439 * Enable stereo when commit_streams is not required, 440 * for example, frame alternate. 441 */ 442 void dc_enable_stereo( 443 struct dc *dc, 444 struct dc_state *context, 445 struct dc_stream_state *streams[], 446 uint8_t stream_count); 447 448 /* Triggers multi-stream synchronization. */ 449 void dc_trigger_sync(struct dc *dc, struct dc_state *context); 450 451 enum surface_update_type dc_check_update_surfaces_for_stream( 452 struct dc *dc, 453 struct dc_surface_update *updates, 454 int surface_count, 455 struct dc_stream_update *stream_update, 456 const struct dc_stream_status *stream_status); 457 458 /** 459 * Create a new default stream for the requested sink 460 */ 461 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); 462 463 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream); 464 465 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink); 466 467 void dc_stream_retain(struct dc_stream_state *dc_stream); 468 void dc_stream_release(struct dc_stream_state *dc_stream); 469 470 struct dc_stream_status *dc_stream_get_status_from_state( 471 struct dc_state *state, 472 struct dc_stream_state *stream); 473 struct dc_stream_status *dc_stream_get_status( 474 struct dc_stream_state *dc_stream); 475 476 #ifndef TRIM_FSFT 477 bool dc_optimize_timing_for_fsft( 478 struct dc_stream_state *pStream, 479 unsigned int max_input_rate_in_khz); 480 #endif 481 482 /******************************************************************************* 483 * Cursor interfaces - To manages the cursor within a stream 484 ******************************************************************************/ 485 /* TODO: Deprecated once we switch to dc_set_cursor_position */ 486 bool dc_stream_set_cursor_attributes( 487 struct dc_stream_state *stream, 488 const struct dc_cursor_attributes *attributes); 489 490 bool dc_stream_set_cursor_position( 491 struct dc_stream_state *stream, 492 const struct dc_cursor_position *position); 493 494 495 bool dc_stream_adjust_vmin_vmax(struct dc *dc, 496 struct dc_stream_state *stream, 497 struct dc_crtc_timing_adjust *adjust); 498 499 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, 500 struct dc_stream_state *stream, 501 uint32_t *refresh_rate); 502 503 bool dc_stream_get_crtc_position(struct dc *dc, 504 struct dc_stream_state **stream, 505 int num_streams, 506 unsigned int *v_pos, 507 unsigned int *nom_v_pos); 508 509 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 510 bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream, 511 struct crc_params *crc_window); 512 bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc, 513 struct dc_stream_state *stream); 514 #endif 515 516 bool dc_stream_configure_crc(struct dc *dc, 517 struct dc_stream_state *stream, 518 struct crc_params *crc_window, 519 bool enable, 520 bool continuous); 521 522 bool dc_stream_get_crc(struct dc *dc, 523 struct dc_stream_state *stream, 524 uint32_t *r_cr, 525 uint32_t *g_y, 526 uint32_t *b_cb); 527 528 void dc_stream_set_static_screen_params(struct dc *dc, 529 struct dc_stream_state **stream, 530 int num_streams, 531 const struct dc_static_screen_params *params); 532 533 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, 534 enum dc_dynamic_expansion option); 535 536 void dc_stream_set_dither_option(struct dc_stream_state *stream, 537 enum dc_dither_option option); 538 539 bool dc_stream_set_gamut_remap(struct dc *dc, 540 const struct dc_stream_state *stream); 541 542 bool dc_stream_program_csc_matrix(struct dc *dc, 543 struct dc_stream_state *stream); 544 545 bool dc_stream_get_crtc_position(struct dc *dc, 546 struct dc_stream_state **stream, 547 int num_streams, 548 unsigned int *v_pos, 549 unsigned int *nom_v_pos); 550 551 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream); 552 553 #endif /* DC_STREAM_H_ */ 554