1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_STREAM_H_ 27 #define DC_STREAM_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 32 /******************************************************************************* 33 * Stream Interfaces 34 ******************************************************************************/ 35 struct timing_sync_info { 36 int group_id; 37 int group_size; 38 bool master; 39 }; 40 41 struct dc_stream_status { 42 int primary_otg_inst; 43 int stream_enc_inst; 44 int plane_count; 45 int audio_inst; 46 struct timing_sync_info timing_sync_info; 47 struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; 48 }; 49 50 // TODO: References to this needs to be removed.. 51 struct freesync_context { 52 bool dummy; 53 }; 54 55 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 56 enum hubp_dmdata_mode { 57 DMDATA_SW_MODE, 58 DMDATA_HW_MODE 59 }; 60 61 struct dc_dmdata_attributes { 62 /* Specifies whether dynamic meta data will be updated by software 63 * or has to be fetched by hardware (DMA mode) 64 */ 65 enum hubp_dmdata_mode dmdata_mode; 66 /* Specifies if current dynamic meta data is to be used only for the current frame */ 67 bool dmdata_repeat; 68 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ 69 uint32_t dmdata_size; 70 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ 71 bool dmdata_updated; 72 /* If hardware mode is used, the base address where DMDATA surface is located */ 73 PHYSICAL_ADDRESS_LOC address; 74 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ 75 bool dmdata_qos_mode; 76 /* If qos_mode = 1, this is the QOS value to be used: */ 77 uint32_t dmdata_qos_level; 78 /* Specifies the value in unit of REFCLK cycles to be added to the 79 * current time to produce the Amortized deadline for Dynamic Metadata chunk request 80 */ 81 uint32_t dmdata_dl_delta; 82 /* An unbounded array of uint32s, represents software dmdata to be loaded */ 83 uint32_t *dmdata_sw_data; 84 }; 85 #endif 86 87 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 88 struct dc_writeback_info { 89 bool wb_enabled; 90 int dwb_pipe_inst; 91 struct dc_dwb_params dwb_params; 92 struct mcif_buf_params mcif_buf_params; 93 }; 94 95 struct dc_writeback_update { 96 unsigned int num_wb_info; 97 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 98 }; 99 #endif 100 101 enum vertical_interrupt_ref_point { 102 START_V_UPDATE = 0, 103 START_V_SYNC, 104 INVALID_POINT 105 106 //For now, only v_update interrupt is used. 107 //START_V_BLANK, 108 //START_V_ACTIVE 109 }; 110 111 struct periodic_interrupt_config { 112 enum vertical_interrupt_ref_point ref_point; 113 int lines_offset; 114 }; 115 116 union stream_update_flags { 117 struct { 118 uint32_t scaling:1; 119 uint32_t out_tf:1; 120 uint32_t out_csc:1; 121 uint32_t abm_level:1; 122 uint32_t dpms_off:1; 123 uint32_t gamut_remap:1; 124 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 125 uint32_t wb_update:1; 126 #endif 127 } bits; 128 129 uint32_t raw; 130 }; 131 132 struct dc_stream_state { 133 // sink is deprecated, new code should not reference 134 // this pointer 135 struct dc_sink *sink; 136 137 struct dc_link *link; 138 struct dc_panel_patch sink_patches; 139 union display_content_support content_support; 140 struct dc_crtc_timing timing; 141 struct dc_crtc_timing_adjust adjust; 142 struct dc_info_packet vrr_infopacket; 143 struct dc_info_packet vsc_infopacket; 144 struct dc_info_packet vsp_infopacket; 145 146 struct rect src; /* composition area */ 147 struct rect dst; /* stream addressable area */ 148 149 // TODO: References to this needs to be removed.. 150 struct freesync_context freesync_ctx; 151 152 struct audio_info audio_info; 153 154 struct dc_info_packet hdr_static_metadata; 155 PHYSICAL_ADDRESS_LOC dmdata_address; 156 bool use_dynamic_meta; 157 158 struct dc_transfer_func *out_transfer_func; 159 struct colorspace_transform gamut_remap_matrix; 160 struct dc_csc_transform csc_color_matrix; 161 162 enum dc_color_space output_color_space; 163 enum dc_dither_option dither_option; 164 165 enum view_3d_format view_format; 166 167 bool ignore_msa_timing_param; 168 bool converter_disable_audio; 169 uint8_t qs_bit; 170 uint8_t qy_bit; 171 172 /* TODO: custom INFO packets */ 173 /* TODO: ABM info (DMCU) */ 174 /* PSR info */ 175 unsigned char psr_version; 176 /* TODO: CEA VIC */ 177 178 /* DMCU info */ 179 unsigned int abm_level; 180 181 struct periodic_interrupt_config periodic_interrupt0; 182 struct periodic_interrupt_config periodic_interrupt1; 183 184 /* from core_stream struct */ 185 struct dc_context *ctx; 186 187 /* used by DCP and FMT */ 188 struct bit_depth_reduction_params bit_depth_params; 189 struct clamping_and_pixel_encoding_params clamping; 190 191 int phy_pix_clk; 192 enum signal_type signal; 193 bool dpms_off; 194 195 void *dm_stream_context; 196 197 struct dc_cursor_attributes cursor_attributes; 198 struct dc_cursor_position cursor_position; 199 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 200 201 /* from stream struct */ 202 struct kref refcount; 203 204 struct crtc_trigger_info triggered_crtc_reset; 205 206 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 207 /* writeback */ 208 unsigned int num_wb_info; 209 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 210 #endif 211 /* Computed state bits */ 212 bool mode_changed : 1; 213 214 /* Output from DC when stream state is committed or altered 215 * DC may only access these values during: 216 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams 217 * values may not change outside of those calls 218 */ 219 struct { 220 // For interrupt management, some hardware instance 221 // offsets need to be exposed to DM 222 uint8_t otg_offset; 223 } out; 224 225 bool apply_edp_fast_boot_optimization; 226 bool apply_seamless_boot_optimization; 227 228 uint32_t stream_id; 229 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 230 bool is_dsc_enabled; 231 #endif 232 union stream_update_flags update_flags; 233 }; 234 235 #define ABM_LEVEL_IMMEDIATE_DISABLE 0xFFFFFFFF 236 237 struct dc_stream_update { 238 struct dc_stream_state *stream; 239 240 struct rect src; 241 struct rect dst; 242 struct dc_transfer_func *out_transfer_func; 243 struct dc_info_packet *hdr_static_metadata; 244 unsigned int *abm_level; 245 246 struct periodic_interrupt_config *periodic_interrupt0; 247 struct periodic_interrupt_config *periodic_interrupt1; 248 249 struct dc_info_packet *vrr_infopacket; 250 struct dc_info_packet *vsc_infopacket; 251 struct dc_info_packet *vsp_infopacket; 252 253 bool *dpms_off; 254 255 struct colorspace_transform *gamut_remap; 256 enum dc_color_space *output_color_space; 257 enum dc_dither_option *dither_option; 258 259 struct dc_csc_transform *output_csc_transform; 260 261 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 262 struct dc_writeback_update *wb_update; 263 #endif 264 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) 265 struct dc_dsc_config *dsc_config; 266 #endif 267 }; 268 269 bool dc_is_stream_unchanged( 270 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 271 bool dc_is_stream_scaling_unchanged( 272 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 273 274 /* 275 * Set up surface attributes and associate to a stream 276 * The surfaces parameter is an absolute set of all surface active for the stream. 277 * If no surfaces are provided, the stream will be blanked; no memory read. 278 * Any flip related attribute changes must be done through this interface. 279 * 280 * After this call: 281 * Surfaces attributes are programmed and configured to be composed into stream. 282 * This does not trigger a flip. No surface address is programmed. 283 */ 284 285 void dc_commit_updates_for_stream(struct dc *dc, 286 struct dc_surface_update *srf_updates, 287 int surface_count, 288 struct dc_stream_state *stream, 289 struct dc_stream_update *stream_update, 290 struct dc_state *state); 291 /* 292 * Log the current stream state. 293 */ 294 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream); 295 296 uint8_t dc_get_current_stream_count(struct dc *dc); 297 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); 298 299 /* 300 * Return the current frame counter. 301 */ 302 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); 303 304 /* 305 * Send dp sdp message. 306 */ 307 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 308 const uint8_t *custom_sdp_message, 309 unsigned int sdp_message_size); 310 311 /* TODO: Return parsed values rather than direct register read 312 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos) 313 * being refactored properly to be dce-specific 314 */ 315 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 316 uint32_t *v_blank_start, 317 uint32_t *v_blank_end, 318 uint32_t *h_position, 319 uint32_t *v_position); 320 321 enum dc_status dc_add_stream_to_ctx( 322 struct dc *dc, 323 struct dc_state *new_ctx, 324 struct dc_stream_state *stream); 325 326 enum dc_status dc_remove_stream_from_ctx( 327 struct dc *dc, 328 struct dc_state *new_ctx, 329 struct dc_stream_state *stream); 330 331 332 bool dc_add_plane_to_context( 333 const struct dc *dc, 334 struct dc_stream_state *stream, 335 struct dc_plane_state *plane_state, 336 struct dc_state *context); 337 338 bool dc_remove_plane_from_context( 339 const struct dc *dc, 340 struct dc_stream_state *stream, 341 struct dc_plane_state *plane_state, 342 struct dc_state *context); 343 344 bool dc_rem_all_planes_for_stream( 345 const struct dc *dc, 346 struct dc_stream_state *stream, 347 struct dc_state *context); 348 349 bool dc_add_all_planes_for_stream( 350 const struct dc *dc, 351 struct dc_stream_state *stream, 352 struct dc_plane_state * const *plane_states, 353 int plane_count, 354 struct dc_state *context); 355 356 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 357 bool dc_stream_add_writeback(struct dc *dc, 358 struct dc_stream_state *stream, 359 struct dc_writeback_info *wb_info); 360 bool dc_stream_remove_writeback(struct dc *dc, 361 struct dc_stream_state *stream, 362 uint32_t dwb_pipe_inst); 363 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); 364 bool dc_stream_set_dynamic_metadata(struct dc *dc, 365 struct dc_stream_state *stream, 366 struct dc_dmdata_attributes *dmdata_attr); 367 #endif 368 369 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); 370 371 /* 372 * Set up streams and links associated to drive sinks 373 * The streams parameter is an absolute set of all active streams. 374 * 375 * After this call: 376 * Phy, Encoder, Timing Generator are programmed and enabled. 377 * New streams are enabled with blank stream; no memory read. 378 */ 379 /* 380 * Enable stereo when commit_streams is not required, 381 * for example, frame alternate. 382 */ 383 bool dc_enable_stereo( 384 struct dc *dc, 385 struct dc_state *context, 386 struct dc_stream_state *streams[], 387 uint8_t stream_count); 388 389 390 enum surface_update_type dc_check_update_surfaces_for_stream( 391 struct dc *dc, 392 struct dc_surface_update *updates, 393 int surface_count, 394 struct dc_stream_update *stream_update, 395 const struct dc_stream_status *stream_status); 396 397 /** 398 * Create a new default stream for the requested sink 399 */ 400 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); 401 402 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream); 403 404 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink); 405 406 void dc_stream_retain(struct dc_stream_state *dc_stream); 407 void dc_stream_release(struct dc_stream_state *dc_stream); 408 409 struct dc_stream_status *dc_stream_get_status_from_state( 410 struct dc_state *state, 411 struct dc_stream_state *stream); 412 struct dc_stream_status *dc_stream_get_status( 413 struct dc_stream_state *dc_stream); 414 415 /******************************************************************************* 416 * Cursor interfaces - To manages the cursor within a stream 417 ******************************************************************************/ 418 /* TODO: Deprecated once we switch to dc_set_cursor_position */ 419 bool dc_stream_set_cursor_attributes( 420 struct dc_stream_state *stream, 421 const struct dc_cursor_attributes *attributes); 422 423 bool dc_stream_set_cursor_position( 424 struct dc_stream_state *stream, 425 const struct dc_cursor_position *position); 426 427 428 bool dc_stream_adjust_vmin_vmax(struct dc *dc, 429 struct dc_stream_state *stream, 430 struct dc_crtc_timing_adjust *adjust); 431 432 bool dc_stream_get_crtc_position(struct dc *dc, 433 struct dc_stream_state **stream, 434 int num_streams, 435 unsigned int *v_pos, 436 unsigned int *nom_v_pos); 437 438 bool dc_stream_configure_crc(struct dc *dc, 439 struct dc_stream_state *stream, 440 bool enable, 441 bool continuous); 442 443 bool dc_stream_get_crc(struct dc *dc, 444 struct dc_stream_state *stream, 445 uint32_t *r_cr, 446 uint32_t *g_y, 447 uint32_t *b_cb); 448 449 void dc_stream_set_static_screen_events(struct dc *dc, 450 struct dc_stream_state **stream, 451 int num_streams, 452 const struct dc_static_screen_events *events); 453 454 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, 455 enum dc_dynamic_expansion option); 456 457 void dc_stream_set_dither_option(struct dc_stream_state *stream, 458 enum dc_dither_option option); 459 460 bool dc_stream_set_gamut_remap(struct dc *dc, 461 const struct dc_stream_state *stream); 462 463 bool dc_stream_program_csc_matrix(struct dc *dc, 464 struct dc_stream_state *stream); 465 466 bool dc_stream_get_crtc_position(struct dc *dc, 467 struct dc_stream_state **stream, 468 int num_streams, 469 unsigned int *v_pos, 470 unsigned int *nom_v_pos); 471 472 #endif /* DC_STREAM_H_ */ 473