1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_STREAM_H_ 27 #define DC_STREAM_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 32 /******************************************************************************* 33 * Stream Interfaces 34 ******************************************************************************/ 35 struct timing_sync_info { 36 int group_id; 37 int group_size; 38 bool master; 39 }; 40 41 struct dc_stream_status { 42 int primary_otg_inst; 43 int stream_enc_inst; 44 int plane_count; 45 struct timing_sync_info timing_sync_info; 46 struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; 47 }; 48 49 // TODO: References to this needs to be removed.. 50 struct freesync_context { 51 bool dummy; 52 }; 53 54 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 55 enum hubp_dmdata_mode { 56 DMDATA_SW_MODE, 57 DMDATA_HW_MODE 58 }; 59 60 struct dc_dmdata_attributes { 61 /* Specifies whether dynamic meta data will be updated by software 62 * or has to be fetched by hardware (DMA mode) 63 */ 64 enum hubp_dmdata_mode dmdata_mode; 65 /* Specifies if current dynamic meta data is to be used only for the current frame */ 66 bool dmdata_repeat; 67 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ 68 uint32_t dmdata_size; 69 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ 70 bool dmdata_updated; 71 /* If hardware mode is used, the base address where DMDATA surface is located */ 72 PHYSICAL_ADDRESS_LOC address; 73 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ 74 bool dmdata_qos_mode; 75 /* If qos_mode = 1, this is the QOS value to be used: */ 76 uint32_t dmdata_qos_level; 77 /* Specifies the value in unit of REFCLK cycles to be added to the 78 * current time to produce the Amortized deadline for Dynamic Metadata chunk request 79 */ 80 uint32_t dmdata_dl_delta; 81 /* An unbounded array of uint32s, represents software dmdata to be loaded */ 82 uint32_t *dmdata_sw_data; 83 }; 84 #endif 85 86 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 87 struct dc_writeback_info { 88 bool wb_enabled; 89 int dwb_pipe_inst; 90 struct dc_dwb_params dwb_params; 91 struct mcif_buf_params mcif_buf_params; 92 }; 93 94 struct dc_writeback_update { 95 unsigned int num_wb_info; 96 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 97 }; 98 #endif 99 100 enum vertical_interrupt_ref_point { 101 START_V_UPDATE = 0, 102 START_V_SYNC, 103 INVALID_POINT 104 105 //For now, only v_update interrupt is used. 106 //START_V_BLANK, 107 //START_V_ACTIVE 108 }; 109 110 struct periodic_interrupt_config { 111 enum vertical_interrupt_ref_point ref_point; 112 int lines_offset; 113 }; 114 115 116 struct dc_stream_state { 117 // sink is deprecated, new code should not reference 118 // this pointer 119 struct dc_sink *sink; 120 121 struct dc_link *link; 122 struct dc_panel_patch sink_patches; 123 union display_content_support content_support; 124 struct dc_crtc_timing timing; 125 struct dc_crtc_timing_adjust adjust; 126 struct dc_info_packet vrr_infopacket; 127 struct dc_info_packet vsc_infopacket; 128 struct dc_info_packet vsp_infopacket; 129 130 struct rect src; /* composition area */ 131 struct rect dst; /* stream addressable area */ 132 133 // TODO: References to this needs to be removed.. 134 struct freesync_context freesync_ctx; 135 136 struct audio_info audio_info; 137 138 struct dc_info_packet hdr_static_metadata; 139 PHYSICAL_ADDRESS_LOC dmdata_address; 140 bool use_dynamic_meta; 141 142 struct dc_transfer_func *out_transfer_func; 143 struct colorspace_transform gamut_remap_matrix; 144 struct dc_csc_transform csc_color_matrix; 145 146 enum dc_color_space output_color_space; 147 enum dc_dither_option dither_option; 148 149 enum view_3d_format view_format; 150 151 bool ignore_msa_timing_param; 152 bool converter_disable_audio; 153 uint8_t qs_bit; 154 uint8_t qy_bit; 155 156 /* TODO: custom INFO packets */ 157 /* TODO: ABM info (DMCU) */ 158 /* PSR info */ 159 unsigned char psr_version; 160 /* TODO: CEA VIC */ 161 162 /* DMCU info */ 163 unsigned int abm_level; 164 165 struct periodic_interrupt_config periodic_interrupt0; 166 struct periodic_interrupt_config periodic_interrupt1; 167 168 /* from core_stream struct */ 169 struct dc_context *ctx; 170 171 /* used by DCP and FMT */ 172 struct bit_depth_reduction_params bit_depth_params; 173 struct clamping_and_pixel_encoding_params clamping; 174 175 int phy_pix_clk; 176 enum signal_type signal; 177 bool dpms_off; 178 179 void *dm_stream_context; 180 181 struct dc_cursor_attributes cursor_attributes; 182 struct dc_cursor_position cursor_position; 183 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 184 185 /* from stream struct */ 186 struct kref refcount; 187 188 struct crtc_trigger_info triggered_crtc_reset; 189 190 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 191 /* writeback */ 192 unsigned int num_wb_info; 193 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 194 #endif 195 /* Computed state bits */ 196 bool mode_changed : 1; 197 198 /* Output from DC when stream state is committed or altered 199 * DC may only access these values during: 200 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams 201 * values may not change outside of those calls 202 */ 203 struct { 204 // For interrupt management, some hardware instance 205 // offsets need to be exposed to DM 206 uint8_t otg_offset; 207 } out; 208 209 bool apply_edp_fast_boot_optimization; 210 bool apply_seamless_boot_optimization; 211 212 uint32_t stream_id; 213 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 214 bool is_dsc_enabled; 215 #endif 216 }; 217 218 struct dc_stream_update { 219 struct rect src; 220 struct rect dst; 221 struct dc_transfer_func *out_transfer_func; 222 struct dc_info_packet *hdr_static_metadata; 223 unsigned int *abm_level; 224 225 struct periodic_interrupt_config *periodic_interrupt0; 226 struct periodic_interrupt_config *periodic_interrupt1; 227 228 struct dc_info_packet *vrr_infopacket; 229 struct dc_info_packet *vsc_infopacket; 230 struct dc_info_packet *vsp_infopacket; 231 232 bool *dpms_off; 233 234 struct colorspace_transform *gamut_remap; 235 enum dc_color_space *output_color_space; 236 enum dc_dither_option *dither_option; 237 238 struct dc_csc_transform *output_csc_transform; 239 240 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 241 struct dc_writeback_update *wb_update; 242 #endif 243 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) 244 struct dc_dsc_config *dsc_config; 245 #endif 246 }; 247 248 bool dc_is_stream_unchanged( 249 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 250 bool dc_is_stream_scaling_unchanged( 251 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 252 253 /* 254 * Set up surface attributes and associate to a stream 255 * The surfaces parameter is an absolute set of all surface active for the stream. 256 * If no surfaces are provided, the stream will be blanked; no memory read. 257 * Any flip related attribute changes must be done through this interface. 258 * 259 * After this call: 260 * Surfaces attributes are programmed and configured to be composed into stream. 261 * This does not trigger a flip. No surface address is programmed. 262 */ 263 264 void dc_commit_updates_for_stream(struct dc *dc, 265 struct dc_surface_update *srf_updates, 266 int surface_count, 267 struct dc_stream_state *stream, 268 struct dc_stream_update *stream_update, 269 struct dc_state *state); 270 /* 271 * Log the current stream state. 272 */ 273 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream); 274 275 uint8_t dc_get_current_stream_count(struct dc *dc); 276 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); 277 278 /* 279 * Return the current frame counter. 280 */ 281 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); 282 283 /* 284 * Send dp sdp message. 285 */ 286 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 287 const uint8_t *custom_sdp_message, 288 unsigned int sdp_message_size); 289 290 /* TODO: Return parsed values rather than direct register read 291 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos) 292 * being refactored properly to be dce-specific 293 */ 294 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 295 uint32_t *v_blank_start, 296 uint32_t *v_blank_end, 297 uint32_t *h_position, 298 uint32_t *v_position); 299 300 enum dc_status dc_add_stream_to_ctx( 301 struct dc *dc, 302 struct dc_state *new_ctx, 303 struct dc_stream_state *stream); 304 305 enum dc_status dc_remove_stream_from_ctx( 306 struct dc *dc, 307 struct dc_state *new_ctx, 308 struct dc_stream_state *stream); 309 310 311 bool dc_add_plane_to_context( 312 const struct dc *dc, 313 struct dc_stream_state *stream, 314 struct dc_plane_state *plane_state, 315 struct dc_state *context); 316 317 bool dc_remove_plane_from_context( 318 const struct dc *dc, 319 struct dc_stream_state *stream, 320 struct dc_plane_state *plane_state, 321 struct dc_state *context); 322 323 bool dc_rem_all_planes_for_stream( 324 const struct dc *dc, 325 struct dc_stream_state *stream, 326 struct dc_state *context); 327 328 bool dc_add_all_planes_for_stream( 329 const struct dc *dc, 330 struct dc_stream_state *stream, 331 struct dc_plane_state * const *plane_states, 332 int plane_count, 333 struct dc_state *context); 334 335 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 336 bool dc_stream_add_writeback(struct dc *dc, 337 struct dc_stream_state *stream, 338 struct dc_writeback_info *wb_info); 339 bool dc_stream_remove_writeback(struct dc *dc, 340 struct dc_stream_state *stream, 341 uint32_t dwb_pipe_inst); 342 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); 343 bool dc_stream_set_dynamic_metadata(struct dc *dc, 344 struct dc_stream_state *stream, 345 struct dc_dmdata_attributes *dmdata_attr); 346 #endif 347 348 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); 349 350 /* 351 * Set up streams and links associated to drive sinks 352 * The streams parameter is an absolute set of all active streams. 353 * 354 * After this call: 355 * Phy, Encoder, Timing Generator are programmed and enabled. 356 * New streams are enabled with blank stream; no memory read. 357 */ 358 /* 359 * Enable stereo when commit_streams is not required, 360 * for example, frame alternate. 361 */ 362 bool dc_enable_stereo( 363 struct dc *dc, 364 struct dc_state *context, 365 struct dc_stream_state *streams[], 366 uint8_t stream_count); 367 368 369 enum surface_update_type dc_check_update_surfaces_for_stream( 370 struct dc *dc, 371 struct dc_surface_update *updates, 372 int surface_count, 373 struct dc_stream_update *stream_update, 374 const struct dc_stream_status *stream_status); 375 376 /** 377 * Create a new default stream for the requested sink 378 */ 379 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); 380 381 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream); 382 383 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink); 384 385 void dc_stream_retain(struct dc_stream_state *dc_stream); 386 void dc_stream_release(struct dc_stream_state *dc_stream); 387 388 struct dc_stream_status *dc_stream_get_status_from_state( 389 struct dc_state *state, 390 struct dc_stream_state *stream); 391 struct dc_stream_status *dc_stream_get_status( 392 struct dc_stream_state *dc_stream); 393 394 /******************************************************************************* 395 * Cursor interfaces - To manages the cursor within a stream 396 ******************************************************************************/ 397 /* TODO: Deprecated once we switch to dc_set_cursor_position */ 398 bool dc_stream_set_cursor_attributes( 399 struct dc_stream_state *stream, 400 const struct dc_cursor_attributes *attributes); 401 402 bool dc_stream_set_cursor_position( 403 struct dc_stream_state *stream, 404 const struct dc_cursor_position *position); 405 406 407 bool dc_stream_adjust_vmin_vmax(struct dc *dc, 408 struct dc_stream_state *stream, 409 struct dc_crtc_timing_adjust *adjust); 410 411 bool dc_stream_get_crtc_position(struct dc *dc, 412 struct dc_stream_state **stream, 413 int num_streams, 414 unsigned int *v_pos, 415 unsigned int *nom_v_pos); 416 417 bool dc_stream_configure_crc(struct dc *dc, 418 struct dc_stream_state *stream, 419 bool enable, 420 bool continuous); 421 422 bool dc_stream_get_crc(struct dc *dc, 423 struct dc_stream_state *stream, 424 uint32_t *r_cr, 425 uint32_t *g_y, 426 uint32_t *b_cb); 427 428 void dc_stream_set_static_screen_events(struct dc *dc, 429 struct dc_stream_state **stream, 430 int num_streams, 431 const struct dc_static_screen_events *events); 432 433 void dc_stream_set_dither_option(struct dc_stream_state *stream, 434 enum dc_dither_option option); 435 436 bool dc_stream_set_gamut_remap(struct dc *dc, 437 const struct dc_stream_state *stream); 438 439 bool dc_stream_program_csc_matrix(struct dc *dc, 440 struct dc_stream_state *stream); 441 442 bool dc_stream_get_crtc_position(struct dc *dc, 443 struct dc_stream_state **stream, 444 int num_streams, 445 unsigned int *v_pos, 446 unsigned int *nom_v_pos); 447 448 #endif /* DC_STREAM_H_ */ 449