1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_STREAM_H_ 27 #define DC_STREAM_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 32 /******************************************************************************* 33 * Stream Interfaces 34 ******************************************************************************/ 35 struct timing_sync_info { 36 int group_id; 37 int group_size; 38 bool master; 39 }; 40 41 struct dc_stream_status { 42 int primary_otg_inst; 43 int stream_enc_inst; 44 45 /** 46 * @plane_count: Total of planes attached to a single stream 47 */ 48 int plane_count; 49 int audio_inst; 50 struct timing_sync_info timing_sync_info; 51 struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; 52 bool is_abm_supported; 53 }; 54 55 enum hubp_dmdata_mode { 56 DMDATA_SW_MODE, 57 DMDATA_HW_MODE 58 }; 59 60 struct dc_dmdata_attributes { 61 /* Specifies whether dynamic meta data will be updated by software 62 * or has to be fetched by hardware (DMA mode) 63 */ 64 enum hubp_dmdata_mode dmdata_mode; 65 /* Specifies if current dynamic meta data is to be used only for the current frame */ 66 bool dmdata_repeat; 67 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ 68 uint32_t dmdata_size; 69 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ 70 bool dmdata_updated; 71 /* If hardware mode is used, the base address where DMDATA surface is located */ 72 PHYSICAL_ADDRESS_LOC address; 73 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ 74 bool dmdata_qos_mode; 75 /* If qos_mode = 1, this is the QOS value to be used: */ 76 uint32_t dmdata_qos_level; 77 /* Specifies the value in unit of REFCLK cycles to be added to the 78 * current time to produce the Amortized deadline for Dynamic Metadata chunk request 79 */ 80 uint32_t dmdata_dl_delta; 81 /* An unbounded array of uint32s, represents software dmdata to be loaded */ 82 uint32_t *dmdata_sw_data; 83 }; 84 85 struct dc_writeback_info { 86 bool wb_enabled; 87 int dwb_pipe_inst; 88 struct dc_dwb_params dwb_params; 89 struct mcif_buf_params mcif_buf_params; 90 struct mcif_warmup_params mcif_warmup_params; 91 /* the plane that is the input to TOP_MUX for MPCC that is the DWB source */ 92 struct dc_plane_state *writeback_source_plane; 93 /* source MPCC instance. for use by internally by dc */ 94 int mpcc_inst; 95 }; 96 97 struct dc_writeback_update { 98 unsigned int num_wb_info; 99 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 100 }; 101 102 enum vertical_interrupt_ref_point { 103 START_V_UPDATE = 0, 104 START_V_SYNC, 105 INVALID_POINT 106 107 //For now, only v_update interrupt is used. 108 //START_V_BLANK, 109 //START_V_ACTIVE 110 }; 111 112 struct periodic_interrupt_config { 113 enum vertical_interrupt_ref_point ref_point; 114 int lines_offset; 115 }; 116 117 struct dc_mst_stream_bw_update { 118 bool is_increase; // is bandwidth reduced or increased 119 uint32_t mst_stream_bw; // new mst bandwidth in kbps 120 }; 121 122 union stream_update_flags { 123 struct { 124 uint32_t scaling:1; 125 uint32_t out_tf:1; 126 uint32_t out_csc:1; 127 uint32_t abm_level:1; 128 uint32_t dpms_off:1; 129 uint32_t gamut_remap:1; 130 uint32_t wb_update:1; 131 uint32_t dsc_changed : 1; 132 uint32_t mst_bw : 1; 133 uint32_t crtc_timing_adjust : 1; 134 } bits; 135 136 uint32_t raw; 137 }; 138 139 struct test_pattern { 140 enum dp_test_pattern type; 141 enum dp_test_pattern_color_space color_space; 142 struct link_training_settings const *p_link_settings; 143 unsigned char const *p_custom_pattern; 144 unsigned int cust_pattern_size; 145 }; 146 147 #define SUBVP_DRR_MARGIN_US 600 // 600us for DRR margin (SubVP + DRR) 148 149 enum mall_stream_type { 150 SUBVP_NONE, // subvp not in use 151 SUBVP_MAIN, // subvp in use, this stream is main stream 152 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream 153 }; 154 155 struct mall_stream_config { 156 /* MALL stream config to indicate if the stream is phantom or not. 157 * We will use a phantom stream to indicate that the pipe is phantom. 158 */ 159 enum mall_stream_type type; 160 struct dc_stream_state *paired_stream; // master / slave stream 161 }; 162 163 /* Temp struct used to save and restore MALL config 164 * during validation. 165 * 166 * TODO: Move MALL config into dc_state instead of stream struct 167 * to avoid needing to save/restore. 168 */ 169 struct mall_temp_config { 170 struct mall_stream_config mall_stream_config[MAX_PIPES]; 171 bool is_phantom_plane[MAX_PIPES]; 172 }; 173 174 struct dc_stream_state { 175 // sink is deprecated, new code should not reference 176 // this pointer 177 struct dc_sink *sink; 178 179 struct dc_link *link; 180 /* For dynamic link encoder assignment, update the link encoder assigned to 181 * a stream via the volatile dc_state rather than the static dc_link. 182 */ 183 struct link_encoder *link_enc; 184 struct dc_panel_patch sink_patches; 185 union display_content_support content_support; 186 struct dc_crtc_timing timing; 187 struct dc_crtc_timing_adjust adjust; 188 struct dc_info_packet vrr_infopacket; 189 struct dc_info_packet vsc_infopacket; 190 struct dc_info_packet vsp_infopacket; 191 struct dc_info_packet hfvsif_infopacket; 192 struct dc_info_packet vtem_infopacket; 193 struct dc_info_packet adaptive_sync_infopacket; 194 uint8_t dsc_packed_pps[128]; 195 struct rect src; /* composition area */ 196 struct rect dst; /* stream addressable area */ 197 198 struct audio_info audio_info; 199 200 struct dc_info_packet hdr_static_metadata; 201 PHYSICAL_ADDRESS_LOC dmdata_address; 202 bool use_dynamic_meta; 203 204 struct dc_transfer_func *out_transfer_func; 205 struct colorspace_transform gamut_remap_matrix; 206 struct dc_csc_transform csc_color_matrix; 207 208 enum dc_color_space output_color_space; 209 enum dc_dither_option dither_option; 210 211 enum view_3d_format view_format; 212 213 bool use_vsc_sdp_for_colorimetry; 214 bool ignore_msa_timing_param; 215 216 /** 217 * @allow_freesync: 218 * 219 * It say if Freesync is enabled or not. 220 */ 221 bool allow_freesync; 222 223 /** 224 * @vrr_active_variable: 225 * 226 * It describes if VRR is in use. 227 */ 228 bool vrr_active_variable; 229 bool freesync_on_desktop; 230 231 bool converter_disable_audio; 232 uint8_t qs_bit; 233 uint8_t qy_bit; 234 235 /* TODO: custom INFO packets */ 236 /* TODO: ABM info (DMCU) */ 237 /* TODO: CEA VIC */ 238 239 /* DMCU info */ 240 unsigned int abm_level; 241 242 struct periodic_interrupt_config periodic_interrupt; 243 244 /* from core_stream struct */ 245 struct dc_context *ctx; 246 247 /* used by DCP and FMT */ 248 struct bit_depth_reduction_params bit_depth_params; 249 struct clamping_and_pixel_encoding_params clamping; 250 251 int phy_pix_clk; 252 enum signal_type signal; 253 bool dpms_off; 254 255 void *dm_stream_context; 256 257 struct dc_cursor_attributes cursor_attributes; 258 struct dc_cursor_position cursor_position; 259 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 260 261 /* from stream struct */ 262 struct kref refcount; 263 264 struct crtc_trigger_info triggered_crtc_reset; 265 266 /* writeback */ 267 unsigned int num_wb_info; 268 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 269 const struct dc_transfer_func *func_shaper; 270 const struct dc_3dlut *lut3d_func; 271 /* Computed state bits */ 272 bool mode_changed : 1; 273 274 /* Output from DC when stream state is committed or altered 275 * DC may only access these values during: 276 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams 277 * values may not change outside of those calls 278 */ 279 struct { 280 // For interrupt management, some hardware instance 281 // offsets need to be exposed to DM 282 uint8_t otg_offset; 283 } out; 284 285 bool apply_edp_fast_boot_optimization; 286 bool apply_seamless_boot_optimization; 287 uint32_t apply_boot_odm_mode; 288 289 uint32_t stream_id; 290 291 struct test_pattern test_pattern; 292 union stream_update_flags update_flags; 293 294 bool has_non_synchronizable_pclk; 295 bool vblank_synchronized; 296 struct mall_stream_config mall_stream_config; 297 }; 298 299 #define ABM_LEVEL_IMMEDIATE_DISABLE 255 300 301 struct dc_stream_update { 302 struct dc_stream_state *stream; 303 304 struct rect src; 305 struct rect dst; 306 struct dc_transfer_func *out_transfer_func; 307 struct dc_info_packet *hdr_static_metadata; 308 unsigned int *abm_level; 309 310 struct periodic_interrupt_config *periodic_interrupt; 311 312 struct dc_info_packet *vrr_infopacket; 313 struct dc_info_packet *vsc_infopacket; 314 struct dc_info_packet *vsp_infopacket; 315 struct dc_info_packet *hfvsif_infopacket; 316 struct dc_info_packet *vtem_infopacket; 317 struct dc_info_packet *adaptive_sync_infopacket; 318 bool *dpms_off; 319 bool integer_scaling_update; 320 bool *allow_freesync; 321 bool *vrr_active_variable; 322 323 struct colorspace_transform *gamut_remap; 324 enum dc_color_space *output_color_space; 325 enum dc_dither_option *dither_option; 326 327 struct dc_csc_transform *output_csc_transform; 328 329 struct dc_writeback_update *wb_update; 330 struct dc_dsc_config *dsc_config; 331 struct dc_mst_stream_bw_update *mst_bw_update; 332 struct dc_transfer_func *func_shaper; 333 struct dc_3dlut *lut3d_func; 334 335 struct test_pattern *pending_test_pattern; 336 struct dc_crtc_timing_adjust *crtc_timing_adjust; 337 }; 338 339 bool dc_is_stream_unchanged( 340 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 341 bool dc_is_stream_scaling_unchanged( 342 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 343 344 /* 345 * Setup stream attributes if no stream updates are provided 346 * there will be no impact on the stream parameters 347 * 348 * Set up surface attributes and associate to a stream 349 * The surfaces parameter is an absolute set of all surface active for the stream. 350 * If no surfaces are provided, the stream will be blanked; no memory read. 351 * Any flip related attribute changes must be done through this interface. 352 * 353 * After this call: 354 * Surfaces attributes are programmed and configured to be composed into stream. 355 * This does not trigger a flip. No surface address is programmed. 356 * 357 */ 358 bool dc_update_planes_and_stream(struct dc *dc, 359 struct dc_surface_update *surface_updates, int surface_count, 360 struct dc_stream_state *dc_stream, 361 struct dc_stream_update *stream_update); 362 363 /* 364 * Set up surface attributes and associate to a stream 365 * The surfaces parameter is an absolute set of all surface active for the stream. 366 * If no surfaces are provided, the stream will be blanked; no memory read. 367 * Any flip related attribute changes must be done through this interface. 368 * 369 * After this call: 370 * Surfaces attributes are programmed and configured to be composed into stream. 371 * This does not trigger a flip. No surface address is programmed. 372 */ 373 void dc_commit_updates_for_stream(struct dc *dc, 374 struct dc_surface_update *srf_updates, 375 int surface_count, 376 struct dc_stream_state *stream, 377 struct dc_stream_update *stream_update, 378 struct dc_state *state); 379 /* 380 * Log the current stream state. 381 */ 382 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream); 383 384 uint8_t dc_get_current_stream_count(struct dc *dc); 385 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); 386 387 /* 388 * Return the current frame counter. 389 */ 390 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); 391 392 /* 393 * Send dp sdp message. 394 */ 395 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 396 const uint8_t *custom_sdp_message, 397 unsigned int sdp_message_size); 398 399 /* TODO: Return parsed values rather than direct register read 400 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos) 401 * being refactored properly to be dce-specific 402 */ 403 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 404 uint32_t *v_blank_start, 405 uint32_t *v_blank_end, 406 uint32_t *h_position, 407 uint32_t *v_position); 408 409 enum dc_status dc_add_stream_to_ctx( 410 struct dc *dc, 411 struct dc_state *new_ctx, 412 struct dc_stream_state *stream); 413 414 enum dc_status dc_remove_stream_from_ctx( 415 struct dc *dc, 416 struct dc_state *new_ctx, 417 struct dc_stream_state *stream); 418 419 420 bool dc_add_plane_to_context( 421 const struct dc *dc, 422 struct dc_stream_state *stream, 423 struct dc_plane_state *plane_state, 424 struct dc_state *context); 425 426 bool dc_remove_plane_from_context( 427 const struct dc *dc, 428 struct dc_stream_state *stream, 429 struct dc_plane_state *plane_state, 430 struct dc_state *context); 431 432 bool dc_rem_all_planes_for_stream( 433 const struct dc *dc, 434 struct dc_stream_state *stream, 435 struct dc_state *context); 436 437 bool dc_add_all_planes_for_stream( 438 const struct dc *dc, 439 struct dc_stream_state *stream, 440 struct dc_plane_state * const *plane_states, 441 int plane_count, 442 struct dc_state *context); 443 444 bool dc_stream_add_writeback(struct dc *dc, 445 struct dc_stream_state *stream, 446 struct dc_writeback_info *wb_info); 447 448 bool dc_stream_remove_writeback(struct dc *dc, 449 struct dc_stream_state *stream, 450 uint32_t dwb_pipe_inst); 451 452 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 453 struct dc_state *state, 454 struct dc_stream_state *stream); 455 456 bool dc_stream_warmup_writeback(struct dc *dc, 457 int num_dwb, 458 struct dc_writeback_info *wb_info); 459 460 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); 461 462 bool dc_stream_set_dynamic_metadata(struct dc *dc, 463 struct dc_stream_state *stream, 464 struct dc_dmdata_attributes *dmdata_attr); 465 466 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); 467 468 /* 469 * Set up streams and links associated to drive sinks 470 * The streams parameter is an absolute set of all active streams. 471 * 472 * After this call: 473 * Phy, Encoder, Timing Generator are programmed and enabled. 474 * New streams are enabled with blank stream; no memory read. 475 */ 476 /* 477 * Enable stereo when commit_streams is not required, 478 * for example, frame alternate. 479 */ 480 void dc_enable_stereo( 481 struct dc *dc, 482 struct dc_state *context, 483 struct dc_stream_state *streams[], 484 uint8_t stream_count); 485 486 /* Triggers multi-stream synchronization. */ 487 void dc_trigger_sync(struct dc *dc, struct dc_state *context); 488 489 enum surface_update_type dc_check_update_surfaces_for_stream( 490 struct dc *dc, 491 struct dc_surface_update *updates, 492 int surface_count, 493 struct dc_stream_update *stream_update, 494 const struct dc_stream_status *stream_status); 495 496 /** 497 * Create a new default stream for the requested sink 498 */ 499 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); 500 501 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream); 502 503 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink); 504 505 void dc_stream_retain(struct dc_stream_state *dc_stream); 506 void dc_stream_release(struct dc_stream_state *dc_stream); 507 508 struct dc_stream_status *dc_stream_get_status_from_state( 509 struct dc_state *state, 510 struct dc_stream_state *stream); 511 struct dc_stream_status *dc_stream_get_status( 512 struct dc_stream_state *dc_stream); 513 514 #ifndef TRIM_FSFT 515 bool dc_optimize_timing_for_fsft( 516 struct dc_stream_state *pStream, 517 unsigned int max_input_rate_in_khz); 518 #endif 519 520 /******************************************************************************* 521 * Cursor interfaces - To manages the cursor within a stream 522 ******************************************************************************/ 523 /* TODO: Deprecated once we switch to dc_set_cursor_position */ 524 bool dc_stream_set_cursor_attributes( 525 struct dc_stream_state *stream, 526 const struct dc_cursor_attributes *attributes); 527 528 bool dc_stream_set_cursor_position( 529 struct dc_stream_state *stream, 530 const struct dc_cursor_position *position); 531 532 533 bool dc_stream_adjust_vmin_vmax(struct dc *dc, 534 struct dc_stream_state *stream, 535 struct dc_crtc_timing_adjust *adjust); 536 537 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, 538 struct dc_stream_state *stream, 539 uint32_t *refresh_rate); 540 541 bool dc_stream_get_crtc_position(struct dc *dc, 542 struct dc_stream_state **stream, 543 int num_streams, 544 unsigned int *v_pos, 545 unsigned int *nom_v_pos); 546 547 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 548 bool dc_stream_forward_crc_window(struct dc_stream_state *stream, 549 struct rect *rect, 550 bool is_stop); 551 #endif 552 553 bool dc_stream_configure_crc(struct dc *dc, 554 struct dc_stream_state *stream, 555 struct crc_params *crc_window, 556 bool enable, 557 bool continuous); 558 559 bool dc_stream_get_crc(struct dc *dc, 560 struct dc_stream_state *stream, 561 uint32_t *r_cr, 562 uint32_t *g_y, 563 uint32_t *b_cb); 564 565 void dc_stream_set_static_screen_params(struct dc *dc, 566 struct dc_stream_state **stream, 567 int num_streams, 568 const struct dc_static_screen_params *params); 569 570 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, 571 enum dc_dynamic_expansion option); 572 573 void dc_stream_set_dither_option(struct dc_stream_state *stream, 574 enum dc_dither_option option); 575 576 bool dc_stream_set_gamut_remap(struct dc *dc, 577 const struct dc_stream_state *stream); 578 579 bool dc_stream_program_csc_matrix(struct dc *dc, 580 struct dc_stream_state *stream); 581 582 bool dc_stream_get_crtc_position(struct dc *dc, 583 struct dc_stream_state **stream, 584 int num_streams, 585 unsigned int *v_pos, 586 unsigned int *nom_v_pos); 587 588 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream); 589 590 void dc_dmub_update_dirty_rect(struct dc *dc, 591 int surface_count, 592 struct dc_stream_state *stream, 593 struct dc_surface_update *srf_updates, 594 struct dc_state *context); 595 #endif /* DC_STREAM_H_ */ 596