1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_STREAM_H_ 27 #define DC_STREAM_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 32 /******************************************************************************* 33 * Stream Interfaces 34 ******************************************************************************/ 35 struct timing_sync_info { 36 int group_id; 37 int group_size; 38 bool master; 39 }; 40 41 struct dc_stream_status { 42 int primary_otg_inst; 43 int stream_enc_inst; 44 45 /** 46 * @plane_count: Total of planes attached to a single stream 47 */ 48 int plane_count; 49 int audio_inst; 50 struct timing_sync_info timing_sync_info; 51 struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; 52 bool is_abm_supported; 53 }; 54 55 enum hubp_dmdata_mode { 56 DMDATA_SW_MODE, 57 DMDATA_HW_MODE 58 }; 59 60 struct dc_dmdata_attributes { 61 /* Specifies whether dynamic meta data will be updated by software 62 * or has to be fetched by hardware (DMA mode) 63 */ 64 enum hubp_dmdata_mode dmdata_mode; 65 /* Specifies if current dynamic meta data is to be used only for the current frame */ 66 bool dmdata_repeat; 67 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ 68 uint32_t dmdata_size; 69 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ 70 bool dmdata_updated; 71 /* If hardware mode is used, the base address where DMDATA surface is located */ 72 PHYSICAL_ADDRESS_LOC address; 73 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ 74 bool dmdata_qos_mode; 75 /* If qos_mode = 1, this is the QOS value to be used: */ 76 uint32_t dmdata_qos_level; 77 /* Specifies the value in unit of REFCLK cycles to be added to the 78 * current time to produce the Amortized deadline for Dynamic Metadata chunk request 79 */ 80 uint32_t dmdata_dl_delta; 81 /* An unbounded array of uint32s, represents software dmdata to be loaded */ 82 uint32_t *dmdata_sw_data; 83 }; 84 85 struct dc_writeback_info { 86 bool wb_enabled; 87 int dwb_pipe_inst; 88 struct dc_dwb_params dwb_params; 89 struct mcif_buf_params mcif_buf_params; 90 struct mcif_warmup_params mcif_warmup_params; 91 /* the plane that is the input to TOP_MUX for MPCC that is the DWB source */ 92 struct dc_plane_state *writeback_source_plane; 93 /* source MPCC instance. for use by internally by dc */ 94 int mpcc_inst; 95 }; 96 97 struct dc_writeback_update { 98 unsigned int num_wb_info; 99 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 100 }; 101 102 enum vertical_interrupt_ref_point { 103 START_V_UPDATE = 0, 104 START_V_SYNC, 105 INVALID_POINT 106 107 //For now, only v_update interrupt is used. 108 //START_V_BLANK, 109 //START_V_ACTIVE 110 }; 111 112 struct periodic_interrupt_config { 113 enum vertical_interrupt_ref_point ref_point; 114 int lines_offset; 115 }; 116 117 struct dc_mst_stream_bw_update { 118 bool is_increase; // is bandwidth reduced or increased 119 uint32_t mst_stream_bw; // new mst bandwidth in kbps 120 }; 121 122 union stream_update_flags { 123 struct { 124 uint32_t scaling:1; 125 uint32_t out_tf:1; 126 uint32_t out_csc:1; 127 uint32_t abm_level:1; 128 uint32_t dpms_off:1; 129 uint32_t gamut_remap:1; 130 uint32_t wb_update:1; 131 uint32_t dsc_changed : 1; 132 uint32_t mst_bw : 1; 133 uint32_t crtc_timing_adjust : 1; 134 } bits; 135 136 uint32_t raw; 137 }; 138 139 struct test_pattern { 140 enum dp_test_pattern type; 141 enum dp_test_pattern_color_space color_space; 142 struct link_training_settings const *p_link_settings; 143 unsigned char const *p_custom_pattern; 144 unsigned int cust_pattern_size; 145 }; 146 147 #define SUBVP_DRR_MARGIN_US 600 // 600us for DRR margin (SubVP + DRR) 148 149 enum mall_stream_type { 150 SUBVP_NONE, // subvp not in use 151 SUBVP_MAIN, // subvp in use, this stream is main stream 152 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream 153 }; 154 155 struct mall_stream_config { 156 /* MALL stream config to indicate if the stream is phantom or not. 157 * We will use a phantom stream to indicate that the pipe is phantom. 158 */ 159 enum mall_stream_type type; 160 struct dc_stream_state *paired_stream; // master / slave stream 161 }; 162 163 /* Temp struct used to save and restore MALL config 164 * during validation. 165 * 166 * TODO: Move MALL config into dc_state instead of stream struct 167 * to avoid needing to save/restore. 168 */ 169 struct mall_temp_config { 170 struct mall_stream_config mall_stream_config[MAX_PIPES]; 171 bool is_phantom_plane[MAX_PIPES]; 172 }; 173 174 struct dc_stream_state { 175 // sink is deprecated, new code should not reference 176 // this pointer 177 struct dc_sink *sink; 178 179 struct dc_link *link; 180 /* For dynamic link encoder assignment, update the link encoder assigned to 181 * a stream via the volatile dc_state rather than the static dc_link. 182 */ 183 struct link_encoder *link_enc; 184 struct dc_panel_patch sink_patches; 185 union display_content_support content_support; 186 struct dc_crtc_timing timing; 187 struct dc_crtc_timing_adjust adjust; 188 struct dc_info_packet vrr_infopacket; 189 struct dc_info_packet vsc_infopacket; 190 struct dc_info_packet vsp_infopacket; 191 struct dc_info_packet hfvsif_infopacket; 192 struct dc_info_packet vtem_infopacket; 193 uint8_t dsc_packed_pps[128]; 194 struct rect src; /* composition area */ 195 struct rect dst; /* stream addressable area */ 196 197 struct audio_info audio_info; 198 199 struct dc_info_packet hdr_static_metadata; 200 PHYSICAL_ADDRESS_LOC dmdata_address; 201 bool use_dynamic_meta; 202 203 struct dc_transfer_func *out_transfer_func; 204 struct colorspace_transform gamut_remap_matrix; 205 struct dc_csc_transform csc_color_matrix; 206 207 enum dc_color_space output_color_space; 208 enum dc_dither_option dither_option; 209 210 enum view_3d_format view_format; 211 212 bool use_vsc_sdp_for_colorimetry; 213 bool ignore_msa_timing_param; 214 215 /** 216 * @allow_freesync: 217 * 218 * It say if Freesync is enabled or not. 219 */ 220 bool allow_freesync; 221 222 /** 223 * @vrr_active_variable: 224 * 225 * It describes if VRR is in use. 226 */ 227 bool vrr_active_variable; 228 bool freesync_on_desktop; 229 230 bool converter_disable_audio; 231 uint8_t qs_bit; 232 uint8_t qy_bit; 233 234 /* TODO: custom INFO packets */ 235 /* TODO: ABM info (DMCU) */ 236 /* TODO: CEA VIC */ 237 238 /* DMCU info */ 239 unsigned int abm_level; 240 241 struct periodic_interrupt_config periodic_interrupt; 242 243 /* from core_stream struct */ 244 struct dc_context *ctx; 245 246 /* used by DCP and FMT */ 247 struct bit_depth_reduction_params bit_depth_params; 248 struct clamping_and_pixel_encoding_params clamping; 249 250 int phy_pix_clk; 251 enum signal_type signal; 252 bool dpms_off; 253 254 void *dm_stream_context; 255 256 struct dc_cursor_attributes cursor_attributes; 257 struct dc_cursor_position cursor_position; 258 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 259 260 /* from stream struct */ 261 struct kref refcount; 262 263 struct crtc_trigger_info triggered_crtc_reset; 264 265 /* writeback */ 266 unsigned int num_wb_info; 267 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 268 const struct dc_transfer_func *func_shaper; 269 const struct dc_3dlut *lut3d_func; 270 /* Computed state bits */ 271 bool mode_changed : 1; 272 273 /* Output from DC when stream state is committed or altered 274 * DC may only access these values during: 275 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams 276 * values may not change outside of those calls 277 */ 278 struct { 279 // For interrupt management, some hardware instance 280 // offsets need to be exposed to DM 281 uint8_t otg_offset; 282 } out; 283 284 bool apply_edp_fast_boot_optimization; 285 bool apply_seamless_boot_optimization; 286 uint32_t apply_boot_odm_mode; 287 288 uint32_t stream_id; 289 290 struct test_pattern test_pattern; 291 union stream_update_flags update_flags; 292 293 bool has_non_synchronizable_pclk; 294 bool vblank_synchronized; 295 struct mall_stream_config mall_stream_config; 296 }; 297 298 #define ABM_LEVEL_IMMEDIATE_DISABLE 255 299 300 struct dc_stream_update { 301 struct dc_stream_state *stream; 302 303 struct rect src; 304 struct rect dst; 305 struct dc_transfer_func *out_transfer_func; 306 struct dc_info_packet *hdr_static_metadata; 307 unsigned int *abm_level; 308 309 struct periodic_interrupt_config *periodic_interrupt; 310 311 struct dc_info_packet *vrr_infopacket; 312 struct dc_info_packet *vsc_infopacket; 313 struct dc_info_packet *vsp_infopacket; 314 struct dc_info_packet *hfvsif_infopacket; 315 struct dc_info_packet *vtem_infopacket; 316 bool *dpms_off; 317 bool integer_scaling_update; 318 bool *allow_freesync; 319 bool *vrr_active_variable; 320 321 struct colorspace_transform *gamut_remap; 322 enum dc_color_space *output_color_space; 323 enum dc_dither_option *dither_option; 324 325 struct dc_csc_transform *output_csc_transform; 326 327 struct dc_writeback_update *wb_update; 328 struct dc_dsc_config *dsc_config; 329 struct dc_mst_stream_bw_update *mst_bw_update; 330 struct dc_transfer_func *func_shaper; 331 struct dc_3dlut *lut3d_func; 332 333 struct test_pattern *pending_test_pattern; 334 struct dc_crtc_timing_adjust *crtc_timing_adjust; 335 }; 336 337 bool dc_is_stream_unchanged( 338 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 339 bool dc_is_stream_scaling_unchanged( 340 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 341 342 /* 343 * Setup stream attributes if no stream updates are provided 344 * there will be no impact on the stream parameters 345 * 346 * Set up surface attributes and associate to a stream 347 * The surfaces parameter is an absolute set of all surface active for the stream. 348 * If no surfaces are provided, the stream will be blanked; no memory read. 349 * Any flip related attribute changes must be done through this interface. 350 * 351 * After this call: 352 * Surfaces attributes are programmed and configured to be composed into stream. 353 * This does not trigger a flip. No surface address is programmed. 354 * 355 */ 356 bool dc_update_planes_and_stream(struct dc *dc, 357 struct dc_surface_update *surface_updates, int surface_count, 358 struct dc_stream_state *dc_stream, 359 struct dc_stream_update *stream_update); 360 361 /* 362 * Set up surface attributes and associate to a stream 363 * The surfaces parameter is an absolute set of all surface active for the stream. 364 * If no surfaces are provided, the stream will be blanked; no memory read. 365 * Any flip related attribute changes must be done through this interface. 366 * 367 * After this call: 368 * Surfaces attributes are programmed and configured to be composed into stream. 369 * This does not trigger a flip. No surface address is programmed. 370 */ 371 void dc_commit_updates_for_stream(struct dc *dc, 372 struct dc_surface_update *srf_updates, 373 int surface_count, 374 struct dc_stream_state *stream, 375 struct dc_stream_update *stream_update, 376 struct dc_state *state); 377 /* 378 * Log the current stream state. 379 */ 380 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream); 381 382 uint8_t dc_get_current_stream_count(struct dc *dc); 383 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); 384 385 /* 386 * Return the current frame counter. 387 */ 388 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); 389 390 /* 391 * Send dp sdp message. 392 */ 393 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 394 const uint8_t *custom_sdp_message, 395 unsigned int sdp_message_size); 396 397 /* TODO: Return parsed values rather than direct register read 398 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos) 399 * being refactored properly to be dce-specific 400 */ 401 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 402 uint32_t *v_blank_start, 403 uint32_t *v_blank_end, 404 uint32_t *h_position, 405 uint32_t *v_position); 406 407 enum dc_status dc_add_stream_to_ctx( 408 struct dc *dc, 409 struct dc_state *new_ctx, 410 struct dc_stream_state *stream); 411 412 enum dc_status dc_remove_stream_from_ctx( 413 struct dc *dc, 414 struct dc_state *new_ctx, 415 struct dc_stream_state *stream); 416 417 418 bool dc_add_plane_to_context( 419 const struct dc *dc, 420 struct dc_stream_state *stream, 421 struct dc_plane_state *plane_state, 422 struct dc_state *context); 423 424 bool dc_remove_plane_from_context( 425 const struct dc *dc, 426 struct dc_stream_state *stream, 427 struct dc_plane_state *plane_state, 428 struct dc_state *context); 429 430 bool dc_rem_all_planes_for_stream( 431 const struct dc *dc, 432 struct dc_stream_state *stream, 433 struct dc_state *context); 434 435 bool dc_add_all_planes_for_stream( 436 const struct dc *dc, 437 struct dc_stream_state *stream, 438 struct dc_plane_state * const *plane_states, 439 int plane_count, 440 struct dc_state *context); 441 442 bool dc_stream_add_writeback(struct dc *dc, 443 struct dc_stream_state *stream, 444 struct dc_writeback_info *wb_info); 445 446 bool dc_stream_remove_writeback(struct dc *dc, 447 struct dc_stream_state *stream, 448 uint32_t dwb_pipe_inst); 449 450 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 451 struct dc_state *state, 452 struct dc_stream_state *stream); 453 454 bool dc_stream_warmup_writeback(struct dc *dc, 455 int num_dwb, 456 struct dc_writeback_info *wb_info); 457 458 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); 459 460 bool dc_stream_set_dynamic_metadata(struct dc *dc, 461 struct dc_stream_state *stream, 462 struct dc_dmdata_attributes *dmdata_attr); 463 464 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); 465 466 /* 467 * Set up streams and links associated to drive sinks 468 * The streams parameter is an absolute set of all active streams. 469 * 470 * After this call: 471 * Phy, Encoder, Timing Generator are programmed and enabled. 472 * New streams are enabled with blank stream; no memory read. 473 */ 474 /* 475 * Enable stereo when commit_streams is not required, 476 * for example, frame alternate. 477 */ 478 void dc_enable_stereo( 479 struct dc *dc, 480 struct dc_state *context, 481 struct dc_stream_state *streams[], 482 uint8_t stream_count); 483 484 /* Triggers multi-stream synchronization. */ 485 void dc_trigger_sync(struct dc *dc, struct dc_state *context); 486 487 enum surface_update_type dc_check_update_surfaces_for_stream( 488 struct dc *dc, 489 struct dc_surface_update *updates, 490 int surface_count, 491 struct dc_stream_update *stream_update, 492 const struct dc_stream_status *stream_status); 493 494 /** 495 * Create a new default stream for the requested sink 496 */ 497 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); 498 499 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream); 500 501 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink); 502 503 void dc_stream_retain(struct dc_stream_state *dc_stream); 504 void dc_stream_release(struct dc_stream_state *dc_stream); 505 506 struct dc_stream_status *dc_stream_get_status_from_state( 507 struct dc_state *state, 508 struct dc_stream_state *stream); 509 struct dc_stream_status *dc_stream_get_status( 510 struct dc_stream_state *dc_stream); 511 512 #ifndef TRIM_FSFT 513 bool dc_optimize_timing_for_fsft( 514 struct dc_stream_state *pStream, 515 unsigned int max_input_rate_in_khz); 516 #endif 517 518 /******************************************************************************* 519 * Cursor interfaces - To manages the cursor within a stream 520 ******************************************************************************/ 521 /* TODO: Deprecated once we switch to dc_set_cursor_position */ 522 bool dc_stream_set_cursor_attributes( 523 struct dc_stream_state *stream, 524 const struct dc_cursor_attributes *attributes); 525 526 bool dc_stream_set_cursor_position( 527 struct dc_stream_state *stream, 528 const struct dc_cursor_position *position); 529 530 531 bool dc_stream_adjust_vmin_vmax(struct dc *dc, 532 struct dc_stream_state *stream, 533 struct dc_crtc_timing_adjust *adjust); 534 535 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, 536 struct dc_stream_state *stream, 537 uint32_t *refresh_rate); 538 539 bool dc_stream_get_crtc_position(struct dc *dc, 540 struct dc_stream_state **stream, 541 int num_streams, 542 unsigned int *v_pos, 543 unsigned int *nom_v_pos); 544 545 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 546 bool dc_stream_forward_crc_window(struct dc *dc, 547 struct rect *rect, 548 struct dc_stream_state *stream, 549 bool is_stop); 550 #endif 551 552 bool dc_stream_configure_crc(struct dc *dc, 553 struct dc_stream_state *stream, 554 struct crc_params *crc_window, 555 bool enable, 556 bool continuous); 557 558 bool dc_stream_get_crc(struct dc *dc, 559 struct dc_stream_state *stream, 560 uint32_t *r_cr, 561 uint32_t *g_y, 562 uint32_t *b_cb); 563 564 void dc_stream_set_static_screen_params(struct dc *dc, 565 struct dc_stream_state **stream, 566 int num_streams, 567 const struct dc_static_screen_params *params); 568 569 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, 570 enum dc_dynamic_expansion option); 571 572 void dc_stream_set_dither_option(struct dc_stream_state *stream, 573 enum dc_dither_option option); 574 575 bool dc_stream_set_gamut_remap(struct dc *dc, 576 const struct dc_stream_state *stream); 577 578 bool dc_stream_program_csc_matrix(struct dc *dc, 579 struct dc_stream_state *stream); 580 581 bool dc_stream_get_crtc_position(struct dc *dc, 582 struct dc_stream_state **stream, 583 int num_streams, 584 unsigned int *v_pos, 585 unsigned int *nom_v_pos); 586 587 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream); 588 589 void dc_dmub_update_dirty_rect(struct dc *dc, 590 int surface_count, 591 struct dc_stream_state *stream, 592 struct dc_surface_update *srf_updates, 593 struct dc_state *context); 594 #endif /* DC_STREAM_H_ */ 595