1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 /* 24 * dc_helper.c 25 * 26 * Created on: Aug 30, 2016 27 * Author: agrodzov 28 */ 29 30 #include <linux/delay.h> 31 32 #include "dm_services.h" 33 #include <stdarg.h> 34 35 #include "dc.h" 36 #include "dc_dmub_srv.h" 37 38 static inline void submit_dmub_read_modify_write( 39 struct dc_reg_helper_state *offload, 40 const struct dc_context *ctx) 41 { 42 struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write; 43 bool gather = false; 44 45 offload->should_burst_write = 46 (offload->same_addr_count == (DMUB_READ_MODIFY_WRITE_SEQ__MAX - 1)); 47 cmd_buf->header.payload_bytes = 48 sizeof(struct dmub_cmd_read_modify_write_sequence) * offload->reg_seq_count; 49 50 gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress; 51 ctx->dmub_srv->reg_helper_offload.gather_in_progress = false; 52 53 dc_dmub_srv_cmd_queue(ctx->dmub_srv, &cmd_buf->header); 54 55 ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather; 56 57 memset(cmd_buf, 0, sizeof(*cmd_buf)); 58 59 offload->reg_seq_count = 0; 60 offload->same_addr_count = 0; 61 } 62 63 static inline void submit_dmub_burst_write( 64 struct dc_reg_helper_state *offload, 65 const struct dc_context *ctx) 66 { 67 struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write; 68 bool gather = false; 69 70 cmd_buf->header.payload_bytes = 71 sizeof(uint32_t) * offload->reg_seq_count; 72 73 gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress; 74 ctx->dmub_srv->reg_helper_offload.gather_in_progress = false; 75 76 dc_dmub_srv_cmd_queue(ctx->dmub_srv, &cmd_buf->header); 77 78 ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather; 79 80 memset(cmd_buf, 0, sizeof(*cmd_buf)); 81 82 offload->reg_seq_count = 0; 83 } 84 85 static inline void submit_dmub_reg_wait( 86 struct dc_reg_helper_state *offload, 87 const struct dc_context *ctx) 88 { 89 struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait; 90 bool gather = false; 91 92 gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress; 93 ctx->dmub_srv->reg_helper_offload.gather_in_progress = false; 94 95 dc_dmub_srv_cmd_queue(ctx->dmub_srv, &cmd_buf->header); 96 97 memset(cmd_buf, 0, sizeof(*cmd_buf)); 98 offload->reg_seq_count = 0; 99 100 ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather; 101 } 102 103 struct dc_reg_value_masks { 104 uint32_t value; 105 uint32_t mask; 106 }; 107 108 struct dc_reg_sequence { 109 uint32_t addr; 110 struct dc_reg_value_masks value_masks; 111 }; 112 113 static inline void set_reg_field_value_masks( 114 struct dc_reg_value_masks *field_value_mask, 115 uint32_t value, 116 uint32_t mask, 117 uint8_t shift) 118 { 119 ASSERT(mask != 0); 120 121 field_value_mask->value = (field_value_mask->value & ~mask) | (mask & (value << shift)); 122 field_value_mask->mask = field_value_mask->mask | mask; 123 } 124 125 static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask, 126 uint32_t addr, int n, 127 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 128 va_list ap) 129 { 130 uint32_t shift, mask, field_value; 131 int i = 1; 132 133 /* gather all bits value/mask getting updated in this register */ 134 set_reg_field_value_masks(field_value_mask, 135 field_value1, mask1, shift1); 136 137 while (i < n) { 138 shift = va_arg(ap, uint32_t); 139 mask = va_arg(ap, uint32_t); 140 field_value = va_arg(ap, uint32_t); 141 142 set_reg_field_value_masks(field_value_mask, 143 field_value, mask, shift); 144 i++; 145 } 146 } 147 148 static void dmub_flush_buffer_execute( 149 struct dc_reg_helper_state *offload, 150 const struct dc_context *ctx) 151 { 152 submit_dmub_read_modify_write(offload, ctx); 153 dc_dmub_srv_cmd_execute(ctx->dmub_srv); 154 } 155 156 static void dmub_flush_burst_write_buffer_execute( 157 struct dc_reg_helper_state *offload, 158 const struct dc_context *ctx) 159 { 160 submit_dmub_burst_write(offload, ctx); 161 dc_dmub_srv_cmd_execute(ctx->dmub_srv); 162 } 163 164 static bool dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t addr, 165 uint32_t reg_val) 166 { 167 struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload; 168 struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write; 169 170 /* flush command if buffer is full */ 171 if (offload->reg_seq_count == DMUB_BURST_WRITE_VALUES__MAX) 172 dmub_flush_burst_write_buffer_execute(offload, ctx); 173 174 if (offload->cmd_data.cmd_common.header.type == DMUB_CMD__REG_SEQ_BURST_WRITE && 175 addr != cmd_buf->addr) { 176 dmub_flush_burst_write_buffer_execute(offload, ctx); 177 return false; 178 } 179 180 cmd_buf->header.type = DMUB_CMD__REG_SEQ_BURST_WRITE; 181 cmd_buf->addr = addr; 182 cmd_buf->write_values[offload->reg_seq_count] = reg_val; 183 offload->reg_seq_count++; 184 185 return true; 186 } 187 188 static uint32_t dmub_reg_value_pack(const struct dc_context *ctx, uint32_t addr, 189 struct dc_reg_value_masks *field_value_mask) 190 { 191 struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload; 192 struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write; 193 struct dmub_cmd_read_modify_write_sequence *seq; 194 195 /* flush command if buffer is full */ 196 if (offload->cmd_data.cmd_common.header.type != DMUB_CMD__REG_SEQ_BURST_WRITE && 197 offload->reg_seq_count == DMUB_READ_MODIFY_WRITE_SEQ__MAX) 198 dmub_flush_buffer_execute(offload, ctx); 199 200 if (offload->should_burst_write) { 201 if (dmub_reg_value_burst_set_pack(ctx, addr, field_value_mask->value)) 202 return field_value_mask->value; 203 else 204 offload->should_burst_write = false; 205 } 206 207 /* pack commands */ 208 cmd_buf->header.type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE; 209 seq = &cmd_buf->seq[offload->reg_seq_count]; 210 211 if (offload->reg_seq_count) { 212 if (cmd_buf->seq[offload->reg_seq_count - 1].addr == addr) 213 offload->same_addr_count++; 214 else 215 offload->same_addr_count = 0; 216 } 217 218 seq->addr = addr; 219 seq->modify_mask = field_value_mask->mask; 220 seq->modify_value = field_value_mask->value; 221 offload->reg_seq_count++; 222 223 return field_value_mask->value; 224 } 225 226 static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr, 227 uint32_t mask, uint32_t shift, uint32_t condition_value, uint32_t time_out_us) 228 { 229 struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload; 230 struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait; 231 232 cmd_buf->header.type = DMUB_CMD__REG_REG_WAIT; 233 cmd_buf->reg_wait.addr = addr; 234 cmd_buf->reg_wait.condition_field_value = mask & (condition_value << shift); 235 cmd_buf->reg_wait.mask = mask; 236 cmd_buf->reg_wait.time_out_us = time_out_us; 237 } 238 239 uint32_t generic_reg_update_ex(const struct dc_context *ctx, 240 uint32_t addr, int n, 241 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 242 ...) 243 { 244 struct dc_reg_value_masks field_value_mask = {0}; 245 uint32_t reg_val; 246 va_list ap; 247 248 va_start(ap, field_value1); 249 250 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, 251 field_value1, ap); 252 253 va_end(ap); 254 255 if (ctx->dmub_srv && 256 ctx->dmub_srv->reg_helper_offload.gather_in_progress) 257 return dmub_reg_value_pack(ctx, addr, &field_value_mask); 258 /* todo: return void so we can decouple code running in driver from register states */ 259 260 /* mmio write directly */ 261 reg_val = dm_read_reg(ctx, addr); 262 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; 263 dm_write_reg(ctx, addr, reg_val); 264 return reg_val; 265 } 266 267 uint32_t generic_reg_set_ex(const struct dc_context *ctx, 268 uint32_t addr, uint32_t reg_val, int n, 269 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 270 ...) 271 { 272 struct dc_reg_value_masks field_value_mask = {0}; 273 va_list ap; 274 275 va_start(ap, field_value1); 276 277 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, 278 field_value1, ap); 279 280 va_end(ap); 281 282 283 /* mmio write directly */ 284 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; 285 286 if (ctx->dmub_srv && 287 ctx->dmub_srv->reg_helper_offload.gather_in_progress) { 288 return dmub_reg_value_burst_set_pack(ctx, addr, reg_val); 289 /* todo: return void so we can decouple code running in driver from register states */ 290 } 291 292 dm_write_reg(ctx, addr, reg_val); 293 return reg_val; 294 } 295 296 uint32_t dm_read_reg_func( 297 const struct dc_context *ctx, 298 uint32_t address, 299 const char *func_name) 300 { 301 uint32_t value; 302 #ifdef DM_CHECK_ADDR_0 303 if (address == 0) { 304 DC_ERR("invalid register read; address = 0\n"); 305 return 0; 306 } 307 #endif 308 309 if (ctx->dmub_srv && 310 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 311 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 312 ASSERT(false); 313 return 0; 314 } 315 316 value = cgs_read_register(ctx->cgs_device, address); 317 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 318 319 return value; 320 } 321 322 uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr, 323 uint8_t shift, uint32_t mask, uint32_t *field_value) 324 { 325 uint32_t reg_val = dm_read_reg(ctx, addr); 326 *field_value = get_reg_field_value_ex(reg_val, mask, shift); 327 return reg_val; 328 } 329 330 uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr, 331 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 332 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) 333 { 334 uint32_t reg_val = dm_read_reg(ctx, addr); 335 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 336 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 337 return reg_val; 338 } 339 340 uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, 341 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 342 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 343 uint8_t shift3, uint32_t mask3, uint32_t *field_value3) 344 { 345 uint32_t reg_val = dm_read_reg(ctx, addr); 346 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 347 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 348 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 349 return reg_val; 350 } 351 352 uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr, 353 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 354 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 355 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 356 uint8_t shift4, uint32_t mask4, uint32_t *field_value4) 357 { 358 uint32_t reg_val = dm_read_reg(ctx, addr); 359 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 360 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 361 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 362 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 363 return reg_val; 364 } 365 366 uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, 367 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 368 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 369 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 370 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 371 uint8_t shift5, uint32_t mask5, uint32_t *field_value5) 372 { 373 uint32_t reg_val = dm_read_reg(ctx, addr); 374 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 375 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 376 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 377 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 378 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 379 return reg_val; 380 } 381 382 uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr, 383 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 384 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 385 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 386 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 387 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 388 uint8_t shift6, uint32_t mask6, uint32_t *field_value6) 389 { 390 uint32_t reg_val = dm_read_reg(ctx, addr); 391 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 392 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 393 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 394 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 395 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 396 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); 397 return reg_val; 398 } 399 400 uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr, 401 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 402 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 403 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 404 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 405 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 406 uint8_t shift6, uint32_t mask6, uint32_t *field_value6, 407 uint8_t shift7, uint32_t mask7, uint32_t *field_value7) 408 { 409 uint32_t reg_val = dm_read_reg(ctx, addr); 410 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 411 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 412 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 413 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 414 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 415 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); 416 *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7); 417 return reg_val; 418 } 419 420 uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr, 421 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 422 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 423 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 424 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 425 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 426 uint8_t shift6, uint32_t mask6, uint32_t *field_value6, 427 uint8_t shift7, uint32_t mask7, uint32_t *field_value7, 428 uint8_t shift8, uint32_t mask8, uint32_t *field_value8) 429 { 430 uint32_t reg_val = dm_read_reg(ctx, addr); 431 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 432 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 433 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 434 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 435 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 436 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); 437 *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7); 438 *field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8); 439 return reg_val; 440 } 441 /* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer 442 * compiler won't be able to check for size match and is prone to stack corruption type of bugs 443 444 uint32_t generic_reg_get(const struct dc_context *ctx, 445 uint32_t addr, int n, ...) 446 { 447 uint32_t shift, mask; 448 uint32_t *field_value; 449 uint32_t reg_val; 450 int i = 0; 451 452 reg_val = dm_read_reg(ctx, addr); 453 454 va_list ap; 455 va_start(ap, n); 456 457 while (i < n) { 458 shift = va_arg(ap, uint32_t); 459 mask = va_arg(ap, uint32_t); 460 field_value = va_arg(ap, uint32_t *); 461 462 *field_value = get_reg_field_value_ex(reg_val, mask, shift); 463 i++; 464 } 465 466 va_end(ap); 467 468 return reg_val; 469 } 470 */ 471 472 void generic_reg_wait(const struct dc_context *ctx, 473 uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value, 474 unsigned int delay_between_poll_us, unsigned int time_out_num_tries, 475 const char *func_name, int line) 476 { 477 uint32_t field_value; 478 uint32_t reg_val; 479 int i; 480 481 if (ctx->dmub_srv && 482 ctx->dmub_srv->reg_helper_offload.gather_in_progress) { 483 dmub_reg_wait_done_pack(ctx, addr, mask, shift, condition_value, 484 delay_between_poll_us * time_out_num_tries); 485 return; 486 } 487 488 /* something is terribly wrong if time out is > 200ms. (5Hz) */ 489 ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000); 490 491 for (i = 0; i <= time_out_num_tries; i++) { 492 if (i) { 493 if (delay_between_poll_us >= 1000) 494 msleep(delay_between_poll_us/1000); 495 else if (delay_between_poll_us > 0) 496 udelay(delay_between_poll_us); 497 } 498 499 reg_val = dm_read_reg(ctx, addr); 500 501 field_value = get_reg_field_value_ex(reg_val, mask, shift); 502 503 if (field_value == condition_value) { 504 if (i * delay_between_poll_us > 1000 && 505 !IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 506 DC_LOG_DC("REG_WAIT taking a while: %dms in %s line:%d\n", 507 delay_between_poll_us * i / 1000, 508 func_name, line); 509 return; 510 } 511 } 512 513 DC_LOG_WARNING("REG_WAIT timeout %dus * %d tries - %s line:%d\n", 514 delay_between_poll_us, time_out_num_tries, 515 func_name, line); 516 517 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 518 BREAK_TO_DEBUGGER(); 519 } 520 521 void generic_write_indirect_reg(const struct dc_context *ctx, 522 uint32_t addr_index, uint32_t addr_data, 523 uint32_t index, uint32_t data) 524 { 525 dm_write_reg(ctx, addr_index, index); 526 dm_write_reg(ctx, addr_data, data); 527 } 528 529 uint32_t generic_read_indirect_reg(const struct dc_context *ctx, 530 uint32_t addr_index, uint32_t addr_data, 531 uint32_t index) 532 { 533 uint32_t value = 0; 534 535 // when reg read, there should not be any offload. 536 if (ctx->dmub_srv && 537 ctx->dmub_srv->reg_helper_offload.gather_in_progress) { 538 ASSERT(false); 539 } 540 541 dm_write_reg(ctx, addr_index, index); 542 value = dm_read_reg(ctx, addr_data); 543 544 return value; 545 } 546 547 548 uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx, 549 uint32_t addr_index, uint32_t addr_data, 550 uint32_t index, uint32_t reg_val, int n, 551 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 552 ...) 553 { 554 uint32_t shift, mask, field_value; 555 int i = 1; 556 557 va_list ap; 558 559 va_start(ap, field_value1); 560 561 reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1); 562 563 while (i < n) { 564 shift = va_arg(ap, uint32_t); 565 mask = va_arg(ap, uint32_t); 566 field_value = va_arg(ap, uint32_t); 567 568 reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); 569 i++; 570 } 571 572 generic_write_indirect_reg(ctx, addr_index, addr_data, index, reg_val); 573 va_end(ap); 574 575 return reg_val; 576 } 577 578 void reg_sequence_start_gather(const struct dc_context *ctx) 579 { 580 /* if reg sequence is supported and enabled, set flag to 581 * indicate we want to have REG_SET, REG_UPDATE macro build 582 * reg sequence command buffer rather than MMIO directly. 583 */ 584 585 if (ctx->dmub_srv && ctx->dc->debug.dmub_offload_enabled) { 586 struct dc_reg_helper_state *offload = 587 &ctx->dmub_srv->reg_helper_offload; 588 589 /* caller sequence mismatch. need to debug caller. offload will not work!!! */ 590 ASSERT(!offload->gather_in_progress); 591 592 offload->gather_in_progress = true; 593 } 594 } 595 596 void reg_sequence_start_execute(const struct dc_context *ctx) 597 { 598 struct dc_reg_helper_state *offload; 599 600 if (!ctx->dmub_srv) 601 return; 602 603 offload = &ctx->dmub_srv->reg_helper_offload; 604 605 if (offload && offload->gather_in_progress) { 606 offload->gather_in_progress = false; 607 offload->should_burst_write = false; 608 switch (offload->cmd_data.cmd_common.header.type) { 609 case DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE: 610 submit_dmub_read_modify_write(offload, ctx); 611 break; 612 case DMUB_CMD__REG_REG_WAIT: 613 submit_dmub_reg_wait(offload, ctx); 614 break; 615 case DMUB_CMD__REG_SEQ_BURST_WRITE: 616 submit_dmub_burst_write(offload, ctx); 617 break; 618 default: 619 return; 620 } 621 622 dc_dmub_srv_cmd_execute(ctx->dmub_srv); 623 } 624 } 625 626 void reg_sequence_wait_done(const struct dc_context *ctx) 627 { 628 /* callback to DM to poll for last submission done*/ 629 struct dc_reg_helper_state *offload; 630 631 if (!ctx->dmub_srv) 632 return; 633 634 offload = &ctx->dmub_srv->reg_helper_offload; 635 636 if (offload && 637 ctx->dc->debug.dmub_offload_enabled && 638 !ctx->dc->debug.dmcub_emulation) { 639 dc_dmub_srv_wait_idle(ctx->dmub_srv); 640 } 641 } 642