1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 /* 24 * dc_helper.c 25 * 26 * Created on: Aug 30, 2016 27 * Author: agrodzov 28 */ 29 #include "dm_services.h" 30 #include <stdarg.h> 31 32 struct dc_reg_value_masks { 33 uint32_t value; 34 uint32_t mask; 35 }; 36 37 struct dc_reg_sequence { 38 uint32_t addr; 39 struct dc_reg_value_masks value_masks; 40 }; 41 42 static inline void set_reg_field_value_masks( 43 struct dc_reg_value_masks *field_value_mask, 44 uint32_t value, 45 uint32_t mask, 46 uint8_t shift) 47 { 48 ASSERT(mask != 0); 49 50 field_value_mask->value = (field_value_mask->value & ~mask) | (mask & (value << shift)); 51 field_value_mask->mask = field_value_mask->mask | mask; 52 } 53 54 uint32_t generic_reg_update_ex(const struct dc_context *ctx, 55 uint32_t addr, uint32_t reg_val, int n, 56 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 57 ...) 58 { 59 struct dc_reg_value_masks field_value_mask = {0}; 60 uint32_t shift, mask, field_value; 61 int i = 1; 62 63 va_list ap; 64 va_start(ap, field_value1); 65 66 /* gather all bits value/mask getting updated in this register */ 67 set_reg_field_value_masks(&field_value_mask, 68 field_value1, mask1, shift1); 69 70 while (i < n) { 71 shift = va_arg(ap, uint32_t); 72 mask = va_arg(ap, uint32_t); 73 field_value = va_arg(ap, uint32_t); 74 75 set_reg_field_value_masks(&field_value_mask, 76 field_value, mask, shift); 77 i++; 78 } 79 va_end(ap); 80 81 82 /* mmio write directly */ 83 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; 84 dm_write_reg(ctx, addr, reg_val); 85 return reg_val; 86 } 87 88 uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr, 89 uint8_t shift, uint32_t mask, uint32_t *field_value) 90 { 91 uint32_t reg_val = dm_read_reg(ctx, addr); 92 *field_value = get_reg_field_value_ex(reg_val, mask, shift); 93 return reg_val; 94 } 95 96 uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr, 97 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 98 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) 99 { 100 uint32_t reg_val = dm_read_reg(ctx, addr); 101 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 102 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 103 return reg_val; 104 } 105 106 uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, 107 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 108 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 109 uint8_t shift3, uint32_t mask3, uint32_t *field_value3) 110 { 111 uint32_t reg_val = dm_read_reg(ctx, addr); 112 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 113 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 114 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 115 return reg_val; 116 } 117 118 uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr, 119 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 120 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 121 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 122 uint8_t shift4, uint32_t mask4, uint32_t *field_value4) 123 { 124 uint32_t reg_val = dm_read_reg(ctx, addr); 125 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 126 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 127 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 128 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 129 return reg_val; 130 } 131 132 uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, 133 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 134 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 135 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 136 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 137 uint8_t shift5, uint32_t mask5, uint32_t *field_value5) 138 { 139 uint32_t reg_val = dm_read_reg(ctx, addr); 140 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 141 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 142 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 143 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 144 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 145 return reg_val; 146 } 147 148 uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr, 149 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 150 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 151 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 152 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 153 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 154 uint8_t shift6, uint32_t mask6, uint32_t *field_value6) 155 { 156 uint32_t reg_val = dm_read_reg(ctx, addr); 157 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 158 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 159 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 160 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 161 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 162 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); 163 return reg_val; 164 } 165 166 uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr, 167 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 168 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 169 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 170 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 171 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 172 uint8_t shift6, uint32_t mask6, uint32_t *field_value6, 173 uint8_t shift7, uint32_t mask7, uint32_t *field_value7) 174 { 175 uint32_t reg_val = dm_read_reg(ctx, addr); 176 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 177 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 178 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 179 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 180 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 181 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); 182 *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7); 183 return reg_val; 184 } 185 186 uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr, 187 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 188 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 189 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 190 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 191 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 192 uint8_t shift6, uint32_t mask6, uint32_t *field_value6, 193 uint8_t shift7, uint32_t mask7, uint32_t *field_value7, 194 uint8_t shift8, uint32_t mask8, uint32_t *field_value8) 195 { 196 uint32_t reg_val = dm_read_reg(ctx, addr); 197 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 198 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 199 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 200 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 201 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 202 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); 203 *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7); 204 *field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8); 205 return reg_val; 206 } 207 /* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer 208 * compiler won't be able to check for size match and is prone to stack corruption type of bugs 209 210 uint32_t generic_reg_get(const struct dc_context *ctx, 211 uint32_t addr, int n, ...) 212 { 213 uint32_t shift, mask; 214 uint32_t *field_value; 215 uint32_t reg_val; 216 int i = 0; 217 218 reg_val = dm_read_reg(ctx, addr); 219 220 va_list ap; 221 va_start(ap, n); 222 223 while (i < n) { 224 shift = va_arg(ap, uint32_t); 225 mask = va_arg(ap, uint32_t); 226 field_value = va_arg(ap, uint32_t *); 227 228 *field_value = get_reg_field_value_ex(reg_val, mask, shift); 229 i++; 230 } 231 232 va_end(ap); 233 234 return reg_val; 235 } 236 */ 237 238 uint32_t generic_reg_wait(const struct dc_context *ctx, 239 uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value, 240 unsigned int delay_between_poll_us, unsigned int time_out_num_tries, 241 const char *func_name, int line) 242 { 243 uint32_t field_value; 244 uint32_t reg_val; 245 int i; 246 247 /* something is terribly wrong if time out is > 200ms. (5Hz) */ 248 ASSERT(delay_between_poll_us * time_out_num_tries <= 200000); 249 250 for (i = 0; i <= time_out_num_tries; i++) { 251 if (i) { 252 if (delay_between_poll_us >= 1000) 253 msleep(delay_between_poll_us/1000); 254 else if (delay_between_poll_us > 0) 255 udelay(delay_between_poll_us); 256 } 257 258 reg_val = dm_read_reg(ctx, addr); 259 260 field_value = get_reg_field_value_ex(reg_val, mask, shift); 261 262 if (field_value == condition_value) { 263 if (i * delay_between_poll_us > 1000 && 264 !IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 265 DC_LOG_DC("REG_WAIT taking a while: %dms in %s line:%d\n", 266 delay_between_poll_us * i / 1000, 267 func_name, line); 268 return reg_val; 269 } 270 } 271 272 DC_LOG_WARNING("REG_WAIT timeout %dus * %d tries - %s line:%d\n", 273 delay_between_poll_us, time_out_num_tries, 274 func_name, line); 275 276 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 277 BREAK_TO_DEBUGGER(); 278 279 return reg_val; 280 } 281 282 void generic_write_indirect_reg(const struct dc_context *ctx, 283 uint32_t addr_index, uint32_t addr_data, 284 uint32_t index, uint32_t data) 285 { 286 dm_write_reg(ctx, addr_index, index); 287 dm_write_reg(ctx, addr_data, data); 288 } 289 290 uint32_t generic_read_indirect_reg(const struct dc_context *ctx, 291 uint32_t addr_index, uint32_t addr_data, 292 uint32_t index) 293 { 294 uint32_t value = 0; 295 296 dm_write_reg(ctx, addr_index, index); 297 value = dm_read_reg(ctx, addr_data); 298 299 return value; 300 } 301 302 303 uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx, 304 uint32_t addr_index, uint32_t addr_data, 305 uint32_t index, uint32_t reg_val, int n, 306 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 307 ...) 308 { 309 uint32_t shift, mask, field_value; 310 int i = 1; 311 312 va_list ap; 313 314 va_start(ap, field_value1); 315 316 reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1); 317 318 while (i < n) { 319 shift = va_arg(ap, uint32_t); 320 mask = va_arg(ap, uint32_t); 321 field_value = va_arg(ap, uint32_t); 322 323 reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); 324 i++; 325 } 326 327 generic_write_indirect_reg(ctx, addr_index, addr_data, index, reg_val); 328 va_end(ap); 329 330 return reg_val; 331 } 332