1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 31 enum dc_lane_count { 32 LANE_COUNT_UNKNOWN = 0, 33 LANE_COUNT_ONE = 1, 34 LANE_COUNT_TWO = 2, 35 LANE_COUNT_FOUR = 4, 36 LANE_COUNT_EIGHT = 8, 37 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 38 }; 39 40 /* This is actually a reference clock (27MHz) multiplier 41 * 162MBps bandwidth for 1.62GHz like rate, 42 * 270MBps for 2.70GHz, 43 * 324MBps for 3.24Ghz, 44 * 540MBps for 5.40GHz 45 * 810MBps for 8.10GHz 46 */ 47 enum dc_link_rate { 48 LINK_RATE_UNKNOWN = 0, 49 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 50 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 51 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 52 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 53 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane 54 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 55 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane 56 #if defined(CONFIG_DRM_AMD_DC_DCN) 57 LINK_RATE_HIGH3 = 0x1E, // Rate_8 (HBR3)- 8.10 Gbps/Lane 58 /* Starting from DP2.0 link rate enum directly represents actual 59 * link rate value in unit of 10 mbps 60 */ 61 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane 62 LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane 63 LINK_RATE_UHBR20 = 2000, // UHBR10 - 20.0 Gbps/Lane 64 #else 65 LINK_RATE_HIGH3 = 0x1E // Rate_8 (HBR3)- 8.10 Gbps/Lane 66 #endif 67 }; 68 69 enum dc_link_spread { 70 LINK_SPREAD_DISABLED = 0x00, 71 /* 0.5 % downspread 30 kHz */ 72 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 73 /* 0.5 % downspread 33 kHz */ 74 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 75 }; 76 77 enum dc_voltage_swing { 78 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 79 VOLTAGE_SWING_LEVEL1, 80 VOLTAGE_SWING_LEVEL2, 81 VOLTAGE_SWING_LEVEL3, 82 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 83 }; 84 85 enum dc_pre_emphasis { 86 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 87 PRE_EMPHASIS_LEVEL1, 88 PRE_EMPHASIS_LEVEL2, 89 PRE_EMPHASIS_LEVEL3, 90 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 91 }; 92 /* Post Cursor 2 is optional for transmitter 93 * and it applies only to the main link operating at HBR2 94 */ 95 enum dc_post_cursor2 { 96 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 97 POST_CURSOR2_LEVEL1, 98 POST_CURSOR2_LEVEL2, 99 POST_CURSOR2_LEVEL3, 100 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 101 }; 102 103 #if defined(CONFIG_DRM_AMD_DC_DCN) 104 enum dc_dp_ffe_preset_level { 105 DP_FFE_PRESET_LEVEL0 = 0, 106 DP_FFE_PRESET_LEVEL1, 107 DP_FFE_PRESET_LEVEL2, 108 DP_FFE_PRESET_LEVEL3, 109 DP_FFE_PRESET_LEVEL4, 110 DP_FFE_PRESET_LEVEL5, 111 DP_FFE_PRESET_LEVEL6, 112 DP_FFE_PRESET_LEVEL7, 113 DP_FFE_PRESET_LEVEL8, 114 DP_FFE_PRESET_LEVEL9, 115 DP_FFE_PRESET_LEVEL10, 116 DP_FFE_PRESET_LEVEL11, 117 DP_FFE_PRESET_LEVEL12, 118 DP_FFE_PRESET_LEVEL13, 119 DP_FFE_PRESET_LEVEL14, 120 DP_FFE_PRESET_LEVEL15, 121 DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15, 122 }; 123 #endif 124 125 enum dc_dp_training_pattern { 126 DP_TRAINING_PATTERN_SEQUENCE_1 = 0, 127 DP_TRAINING_PATTERN_SEQUENCE_2, 128 DP_TRAINING_PATTERN_SEQUENCE_3, 129 DP_TRAINING_PATTERN_SEQUENCE_4, 130 DP_TRAINING_PATTERN_VIDEOIDLE, 131 #if defined(CONFIG_DRM_AMD_DC_DCN) 132 DP_128b_132b_TPS1, 133 DP_128b_132b_TPS2, 134 DP_128b_132b_TPS2_CDS, 135 #endif 136 }; 137 138 enum dp_link_encoding { 139 DP_UNKNOWN_ENCODING = 0, 140 DP_8b_10b_ENCODING = 1, 141 #if defined(CONFIG_DRM_AMD_DC_DCN) 142 DP_128b_132b_ENCODING = 2, 143 #endif 144 }; 145 146 struct dc_link_settings { 147 enum dc_lane_count lane_count; 148 enum dc_link_rate link_rate; 149 enum dc_link_spread link_spread; 150 bool use_link_rate_set; 151 uint8_t link_rate_set; 152 bool dpcd_source_device_specific_field_support; 153 }; 154 155 #if defined(CONFIG_DRM_AMD_DC_DCN) 156 union dc_dp_ffe_preset { 157 struct { 158 uint8_t level : 4; 159 uint8_t reserved : 1; 160 uint8_t no_preshoot : 1; 161 uint8_t no_deemphasis : 1; 162 uint8_t method2 : 1; 163 } settings; 164 uint8_t raw; 165 }; 166 #endif 167 168 struct dc_lane_settings { 169 enum dc_voltage_swing VOLTAGE_SWING; 170 enum dc_pre_emphasis PRE_EMPHASIS; 171 enum dc_post_cursor2 POST_CURSOR2; 172 #if defined(CONFIG_DRM_AMD_DC_DCN) 173 union dc_dp_ffe_preset FFE_PRESET; 174 #endif 175 }; 176 177 struct dc_link_training_overrides { 178 enum dc_voltage_swing *voltage_swing; 179 enum dc_pre_emphasis *pre_emphasis; 180 enum dc_post_cursor2 *post_cursor2; 181 #if defined(CONFIG_DRM_AMD_DC_DCN) 182 union dc_dp_ffe_preset *ffe_preset; 183 #endif 184 185 uint16_t *cr_pattern_time; 186 uint16_t *eq_pattern_time; 187 enum dc_dp_training_pattern *pattern_for_cr; 188 enum dc_dp_training_pattern *pattern_for_eq; 189 190 enum dc_link_spread *downspread; 191 bool *alternate_scrambler_reset; 192 bool *enhanced_framing; 193 bool *mst_enable; 194 bool *fec_enable; 195 }; 196 197 #if defined(CONFIG_DRM_AMD_DC_DCN) 198 union payload_table_update_status { 199 struct { 200 uint8_t VC_PAYLOAD_TABLE_UPDATED:1; 201 uint8_t ACT_HANDLED:1; 202 } bits; 203 uint8_t raw; 204 }; 205 #endif 206 207 union dpcd_rev { 208 struct { 209 uint8_t MINOR:4; 210 uint8_t MAJOR:4; 211 } bits; 212 uint8_t raw; 213 }; 214 215 union max_lane_count { 216 struct { 217 uint8_t MAX_LANE_COUNT:5; 218 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 219 uint8_t TPS3_SUPPORTED:1; 220 uint8_t ENHANCED_FRAME_CAP:1; 221 } bits; 222 uint8_t raw; 223 }; 224 225 union max_down_spread { 226 struct { 227 uint8_t MAX_DOWN_SPREAD:1; 228 uint8_t RESERVED:5; 229 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 230 uint8_t TPS4_SUPPORTED:1; 231 } bits; 232 uint8_t raw; 233 }; 234 235 union mstm_cap { 236 struct { 237 uint8_t MST_CAP:1; 238 uint8_t RESERVED:7; 239 } bits; 240 uint8_t raw; 241 }; 242 243 union lane_count_set { 244 struct { 245 uint8_t LANE_COUNT_SET:5; 246 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 247 uint8_t RESERVED:1; 248 uint8_t ENHANCED_FRAMING:1; 249 } bits; 250 uint8_t raw; 251 }; 252 253 union lane_status { 254 struct { 255 uint8_t CR_DONE_0:1; 256 uint8_t CHANNEL_EQ_DONE_0:1; 257 uint8_t SYMBOL_LOCKED_0:1; 258 uint8_t RESERVED0:1; 259 uint8_t CR_DONE_1:1; 260 uint8_t CHANNEL_EQ_DONE_1:1; 261 uint8_t SYMBOL_LOCKED_1:1; 262 uint8_t RESERVED_1:1; 263 } bits; 264 uint8_t raw; 265 }; 266 267 union device_service_irq { 268 struct { 269 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 270 uint8_t AUTOMATED_TEST:1; 271 uint8_t CP_IRQ:1; 272 uint8_t MCCS_IRQ:1; 273 uint8_t DOWN_REP_MSG_RDY:1; 274 uint8_t UP_REQ_MSG_RDY:1; 275 uint8_t SINK_SPECIFIC:1; 276 uint8_t reserved:1; 277 } bits; 278 uint8_t raw; 279 }; 280 281 union sink_count { 282 struct { 283 uint8_t SINK_COUNT:6; 284 uint8_t CPREADY:1; 285 uint8_t RESERVED:1; 286 } bits; 287 uint8_t raw; 288 }; 289 290 union lane_align_status_updated { 291 struct { 292 uint8_t INTERLANE_ALIGN_DONE:1; 293 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 294 #if defined(CONFIG_DRM_AMD_DC_DCN) 295 uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1; 296 uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1; 297 uint8_t LT_FAILED_128b_132b:1; 298 uint8_t RESERVED:1; 299 #else 300 uint8_t RESERVED:4; 301 #endif 302 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 303 uint8_t LINK_STATUS_UPDATED:1; 304 } bits; 305 uint8_t raw; 306 }; 307 308 union lane_adjust { 309 struct { 310 uint8_t VOLTAGE_SWING_LANE:2; 311 uint8_t PRE_EMPHASIS_LANE:2; 312 uint8_t RESERVED:4; 313 } bits; 314 #if defined(CONFIG_DRM_AMD_DC_DCN) 315 struct { 316 uint8_t PRESET_VALUE :4; 317 uint8_t RESERVED :4; 318 } tx_ffe; 319 #endif 320 uint8_t raw; 321 }; 322 323 union dpcd_training_pattern { 324 struct { 325 uint8_t TRAINING_PATTERN_SET:4; 326 uint8_t RECOVERED_CLOCK_OUT_EN:1; 327 uint8_t SCRAMBLING_DISABLE:1; 328 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 329 } v1_4; 330 struct { 331 uint8_t TRAINING_PATTERN_SET:2; 332 uint8_t LINK_QUAL_PATTERN_SET:2; 333 uint8_t RESERVED:4; 334 } v1_3; 335 uint8_t raw; 336 }; 337 338 /* Training Lane is used to configure downstream DP device's voltage swing 339 and pre-emphasis levels*/ 340 /* The DPCD addresses are from 0x103 to 0x106*/ 341 union dpcd_training_lane { 342 struct { 343 uint8_t VOLTAGE_SWING_SET:2; 344 uint8_t MAX_SWING_REACHED:1; 345 uint8_t PRE_EMPHASIS_SET:2; 346 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 347 uint8_t RESERVED:2; 348 } bits; 349 #if defined(CONFIG_DRM_AMD_DC_DCN) 350 struct { 351 uint8_t PRESET_VALUE :4; 352 uint8_t RESERVED :4; 353 } tx_ffe; 354 #endif 355 uint8_t raw; 356 }; 357 358 /* TMDS-converter related */ 359 union dwnstream_port_caps_byte0 { 360 struct { 361 uint8_t DWN_STRM_PORTX_TYPE:3; 362 uint8_t DWN_STRM_PORTX_HPD:1; 363 uint8_t RESERVERD:4; 364 } bits; 365 uint8_t raw; 366 }; 367 368 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 369 enum dpcd_downstream_port_detailed_type { 370 DOWN_STREAM_DETAILED_DP = 0, 371 DOWN_STREAM_DETAILED_VGA, 372 DOWN_STREAM_DETAILED_DVI, 373 DOWN_STREAM_DETAILED_HDMI, 374 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 375 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 376 }; 377 378 union dwnstream_port_caps_byte2 { 379 struct { 380 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 381 #if defined(CONFIG_DRM_AMD_DC_DCN) 382 uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3; 383 uint8_t SOURCE_CONTROL_MODE_SUPPORT:1; 384 uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1; 385 uint8_t RESERVED:1; 386 #else 387 uint8_t RESERVED:6; 388 #endif 389 } bits; 390 uint8_t raw; 391 }; 392 393 union dp_downstream_port_present { 394 uint8_t byte; 395 struct { 396 uint8_t PORT_PRESENT:1; 397 uint8_t PORT_TYPE:2; 398 uint8_t FMT_CONVERSION:1; 399 uint8_t DETAILED_CAPS:1; 400 uint8_t RESERVED:3; 401 } fields; 402 }; 403 404 union dwnstream_port_caps_byte3_dvi { 405 struct { 406 uint8_t RESERVED1:1; 407 uint8_t DUAL_LINK:1; 408 uint8_t HIGH_COLOR_DEPTH:1; 409 uint8_t RESERVED2:5; 410 } bits; 411 uint8_t raw; 412 }; 413 414 union dwnstream_port_caps_byte3_hdmi { 415 struct { 416 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 417 uint8_t YCrCr422_PASS_THROUGH:1; 418 uint8_t YCrCr420_PASS_THROUGH:1; 419 uint8_t YCrCr422_CONVERSION:1; 420 uint8_t YCrCr420_CONVERSION:1; 421 uint8_t RESERVED:3; 422 } bits; 423 uint8_t raw; 424 }; 425 426 #if defined(CONFIG_DRM_AMD_DC_DCN) 427 union hdmi_sink_encoded_link_bw_support { 428 struct { 429 uint8_t HDMI_SINK_ENCODED_LINK_BW_SUPPORT:3; 430 uint8_t RESERVED:5; 431 } bits; 432 uint8_t raw; 433 }; 434 435 union hdmi_encoded_link_bw { 436 struct { 437 uint8_t FRL_MODE:1; // Bit 0 438 uint8_t BW_9Gbps:1; 439 uint8_t BW_18Gbps:1; 440 uint8_t BW_24Gbps:1; 441 uint8_t BW_32Gbps:1; 442 uint8_t BW_40Gbps:1; 443 uint8_t BW_48Gbps:1; 444 uint8_t RESERVED:1; // Bit 7 445 } bits; 446 uint8_t raw; 447 }; 448 #endif 449 450 /*4-byte structure for detailed capabilities of a down-stream port 451 (DP-to-TMDS converter).*/ 452 union dwnstream_portxcaps { 453 struct { 454 union dwnstream_port_caps_byte0 byte0; 455 unsigned char max_TMDS_clock; //byte1 456 union dwnstream_port_caps_byte2 byte2; 457 458 union { 459 union dwnstream_port_caps_byte3_dvi byteDVI; 460 union dwnstream_port_caps_byte3_hdmi byteHDMI; 461 } byte3; 462 } bytes; 463 464 unsigned char raw[4]; 465 }; 466 467 union downstream_port { 468 struct { 469 unsigned char present:1; 470 unsigned char type:2; 471 unsigned char format_conv:1; 472 unsigned char detailed_caps:1; 473 unsigned char reserved:3; 474 } bits; 475 unsigned char raw; 476 }; 477 478 479 union sink_status { 480 struct { 481 uint8_t RX_PORT0_STATUS:1; 482 uint8_t RX_PORT1_STATUS:1; 483 uint8_t RESERVED:6; 484 } bits; 485 uint8_t raw; 486 }; 487 488 /*6-byte structure corresponding to 6 registers (200h-205h) 489 read during handling of HPD-IRQ*/ 490 union hpd_irq_data { 491 struct { 492 union sink_count sink_cnt;/* 200h */ 493 union device_service_irq device_service_irq;/* 201h */ 494 union lane_status lane01_status;/* 202h */ 495 union lane_status lane23_status;/* 203h */ 496 union lane_align_status_updated lane_status_updated;/* 204h */ 497 union sink_status sink_status; 498 } bytes; 499 uint8_t raw[6]; 500 }; 501 502 union down_stream_port_count { 503 struct { 504 uint8_t DOWN_STR_PORT_COUNT:4; 505 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 506 /*Bit 6 = MSA_TIMING_PAR_IGNORED 507 0 = Sink device requires the MSA timing parameters 508 1 = Sink device is capable of rendering incoming video 509 stream without MSA timing parameters*/ 510 uint8_t IGNORE_MSA_TIMING_PARAM:1; 511 /*Bit 7 = OUI Support 512 0 = OUI not supported 513 1 = OUI supported 514 (OUI and Device Identification mandatory for DP 1.2)*/ 515 uint8_t OUI_SUPPORT:1; 516 } bits; 517 uint8_t raw; 518 }; 519 520 union down_spread_ctrl { 521 struct { 522 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 523 /* Bits 4 = SPREAD_AMP. Spreading amplitude 524 0 = Main link signal is not downspread 525 1 = Main link signal is downspread <= 0.5% 526 with frequency in the range of 30kHz ~ 33kHz*/ 527 uint8_t SPREAD_AMP:1; 528 uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/ 529 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 530 0 = Source device will send valid data for the MSA Timing Params 531 1 = Source device may send invalid data for these MSA Timing Params*/ 532 uint8_t IGNORE_MSA_TIMING_PARAM:1; 533 } bits; 534 uint8_t raw; 535 }; 536 537 union dpcd_edp_config { 538 struct { 539 uint8_t PANEL_MODE_EDP:1; 540 uint8_t FRAMING_CHANGE_ENABLE:1; 541 uint8_t RESERVED:5; 542 uint8_t PANEL_SELF_TEST_ENABLE:1; 543 } bits; 544 uint8_t raw; 545 }; 546 547 struct dp_device_vendor_id { 548 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 549 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 550 }; 551 552 struct dp_sink_hw_fw_revision { 553 uint8_t ieee_hw_rev; 554 uint8_t ieee_fw_rev[2]; 555 }; 556 557 struct dpcd_vendor_signature { 558 bool is_valid; 559 560 union dpcd_ieee_vendor_signature { 561 struct { 562 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 563 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 564 uint8_t ieee_hw_rev; 565 uint8_t ieee_fw_rev[2]; 566 }; 567 uint8_t raw[12]; 568 } data; 569 }; 570 571 struct dpcd_amd_signature { 572 uint8_t AMD_IEEE_TxSignature_byte1; 573 uint8_t AMD_IEEE_TxSignature_byte2; 574 uint8_t AMD_IEEE_TxSignature_byte3; 575 }; 576 577 struct dpcd_amd_device_id { 578 uint8_t device_id_byte1; 579 uint8_t device_id_byte2; 580 uint8_t zero[4]; 581 uint8_t dce_version; 582 uint8_t dal_version_byte1; 583 uint8_t dal_version_byte2; 584 }; 585 586 struct dpcd_source_backlight_set { 587 struct { 588 uint8_t byte0; 589 uint8_t byte1; 590 uint8_t byte2; 591 uint8_t byte3; 592 } backlight_level_millinits; 593 594 struct { 595 uint8_t byte0; 596 uint8_t byte1; 597 } backlight_transition_time_ms; 598 }; 599 600 union dpcd_source_backlight_get { 601 struct { 602 uint32_t backlight_millinits_peak; /* 326h */ 603 uint32_t backlight_millinits_avg; /* 32Ah */ 604 } bytes; 605 uint8_t raw[8]; 606 }; 607 608 /*DPCD register of DP receiver capability field bits-*/ 609 union edp_configuration_cap { 610 struct { 611 uint8_t ALT_SCRAMBLER_RESET:1; 612 uint8_t FRAMING_CHANGE:1; 613 uint8_t RESERVED:1; 614 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 615 uint8_t RESERVED2:4; 616 } bits; 617 uint8_t raw; 618 }; 619 620 union dprx_feature { 621 struct { 622 uint8_t GTC_CAP:1; // bit 0: DP 1.3+ 623 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4 624 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+ 625 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+ 626 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4 627 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4 628 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4 629 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4 630 } bits; 631 uint8_t raw; 632 }; 633 634 union training_aux_rd_interval { 635 struct { 636 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 637 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1; 638 } bits; 639 uint8_t raw; 640 }; 641 642 /* Automated test structures */ 643 union test_request { 644 struct { 645 uint8_t LINK_TRAINING :1; 646 uint8_t LINK_TEST_PATTRN :1; 647 uint8_t EDID_READ :1; 648 uint8_t PHY_TEST_PATTERN :1; 649 uint8_t RESERVED :1; 650 uint8_t AUDIO_TEST_PATTERN :1; 651 uint8_t TEST_AUDIO_DISABLED_VIDEO :1; 652 } bits; 653 uint8_t raw; 654 }; 655 656 union test_response { 657 struct { 658 uint8_t ACK :1; 659 uint8_t NO_ACK :1; 660 uint8_t EDID_CHECKSUM_WRITE:1; 661 uint8_t RESERVED :5; 662 } bits; 663 uint8_t raw; 664 }; 665 666 union phy_test_pattern { 667 struct { 668 #if defined(CONFIG_DRM_AMD_DC_DCN) 669 /* This field is 7 bits for DP2.0 */ 670 uint8_t PATTERN :7; 671 uint8_t RESERVED :1; 672 #else 673 /* DpcdPhyTestPatterns. This field is 2 bits for DP1.1 674 * and 3 bits for DP1.2. 675 */ 676 uint8_t PATTERN :3; 677 /* BY speci, bit7:2 is 0 for DP1.1. */ 678 uint8_t RESERVED :5; 679 #endif 680 } bits; 681 uint8_t raw; 682 }; 683 684 /* States of Compliance Test Specification (CTS DP1.2). */ 685 union compliance_test_state { 686 struct { 687 unsigned char STEREO_3D_RUNNING : 1; 688 unsigned char RESERVED : 7; 689 } bits; 690 unsigned char raw; 691 }; 692 693 union link_test_pattern { 694 struct { 695 /* dpcd_link_test_patterns */ 696 unsigned char PATTERN :2; 697 unsigned char RESERVED:6; 698 } bits; 699 unsigned char raw; 700 }; 701 702 union test_misc { 703 struct dpcd_test_misc_bits { 704 unsigned char SYNC_CLOCK :1; 705 /* dpcd_test_color_format */ 706 unsigned char CLR_FORMAT :2; 707 /* dpcd_test_dyn_range */ 708 unsigned char DYN_RANGE :1; 709 unsigned char YCBCR_COEFS :1; 710 /* dpcd_test_bit_depth */ 711 unsigned char BPC :3; 712 } bits; 713 unsigned char raw; 714 }; 715 716 union audio_test_mode { 717 struct { 718 unsigned char sampling_rate :4; 719 unsigned char channel_count :4; 720 } bits; 721 unsigned char raw; 722 }; 723 724 union audio_test_pattern_period { 725 struct { 726 unsigned char pattern_period :4; 727 unsigned char reserved :4; 728 } bits; 729 unsigned char raw; 730 }; 731 732 struct audio_test_pattern_type { 733 unsigned char value; 734 }; 735 736 struct dp_audio_test_data_flags { 737 uint8_t test_requested :1; 738 uint8_t disable_video :1; 739 }; 740 741 struct dp_audio_test_data { 742 743 struct dp_audio_test_data_flags flags; 744 uint8_t sampling_rate; 745 uint8_t channel_count; 746 uint8_t pattern_type; 747 uint8_t pattern_period[8]; 748 }; 749 750 /* FEC capability DPCD register field bits-*/ 751 union dpcd_fec_capability { 752 struct { 753 uint8_t FEC_CAPABLE:1; 754 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 755 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 756 uint8_t BIT_ERROR_COUNT_CAPABLE:1; 757 #if defined(CONFIG_DRM_AMD_DC_DCN) 758 uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1; 759 uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1; 760 uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1; 761 uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1; 762 #else 763 uint8_t RESERVED:4; 764 #endif 765 } bits; 766 uint8_t raw; 767 }; 768 769 /* DSC capability DPCD register field bits-*/ 770 struct dpcd_dsc_support { 771 uint8_t DSC_SUPPORT :1; 772 uint8_t DSC_PASSTHROUGH_SUPPORT :1; 773 uint8_t RESERVED :6; 774 }; 775 776 struct dpcd_dsc_algorithm_revision { 777 uint8_t DSC_VERSION_MAJOR :4; 778 uint8_t DSC_VERSION_MINOR :4; 779 }; 780 781 struct dpcd_dsc_rc_buffer_block_size { 782 uint8_t RC_BLOCK_BUFFER_SIZE :2; 783 uint8_t RESERVED :6; 784 }; 785 786 struct dpcd_dsc_slice_capability1 { 787 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; 788 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; 789 uint8_t RESERVED :1; 790 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; 791 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; 792 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; 793 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; 794 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; 795 }; 796 797 struct dpcd_dsc_line_buffer_bit_depth { 798 uint8_t LINE_BUFFER_BIT_DEPTH :4; 799 uint8_t RESERVED :4; 800 }; 801 802 struct dpcd_dsc_block_prediction_support { 803 uint8_t BLOCK_PREDICTION_SUPPORT:1; 804 uint8_t RESERVED :7; 805 }; 806 807 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { 808 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; 809 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; 810 uint8_t RESERVED :2; 811 }; 812 813 struct dpcd_dsc_decoder_color_format_capabilities { 814 uint8_t RGB_SUPPORT :1; 815 uint8_t Y_CB_CR_444_SUPPORT :1; 816 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; 817 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; 818 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; 819 uint8_t RESERVED :3; 820 }; 821 822 struct dpcd_dsc_decoder_color_depth_capabilities { 823 uint8_t RESERVED0 :1; 824 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; 825 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; 826 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; 827 uint8_t RESERVED1 :4; 828 }; 829 830 struct dpcd_peak_dsc_throughput_dsc_sink { 831 uint8_t THROUGHPUT_MODE_0:4; 832 uint8_t THROUGHPUT_MODE_1:4; 833 }; 834 835 struct dpcd_dsc_slice_capabilities_2 { 836 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; 837 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; 838 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; 839 uint8_t RESERVED :5; 840 }; 841 842 struct dpcd_bits_per_pixel_increment{ 843 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; 844 uint8_t RESERVED :5; 845 }; 846 union dpcd_dsc_basic_capabilities { 847 struct { 848 struct dpcd_dsc_support dsc_support; 849 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; 850 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; 851 uint8_t dsc_rc_buffer_size; 852 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; 853 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; 854 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; 855 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; 856 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; 857 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; 858 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; 859 uint8_t dsc_maximum_slice_width; 860 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; 861 uint8_t reserved; 862 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; 863 } fields; 864 uint8_t raw[16]; 865 }; 866 867 union dpcd_dsc_branch_decoder_capabilities { 868 struct { 869 uint8_t BRANCH_OVERALL_THROUGHPUT_0; 870 uint8_t BRANCH_OVERALL_THROUGHPUT_1; 871 uint8_t BRANCH_MAX_LINE_WIDTH; 872 } fields; 873 uint8_t raw[3]; 874 }; 875 876 struct dpcd_dsc_capabilities { 877 union dpcd_dsc_basic_capabilities dsc_basic_caps; 878 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps; 879 }; 880 881 /* These parameters are from PSR capabilities reported by Sink DPCD */ 882 struct psr_caps { 883 unsigned char psr_version; 884 unsigned int psr_rfb_setup_time; 885 bool psr_exit_link_training_required; 886 unsigned char edp_revision; 887 unsigned char support_ver; 888 bool su_granularity_required; 889 bool y_coordinate_required; 890 uint8_t su_y_granularity; 891 bool alpm_cap; 892 bool standby_support; 893 uint8_t rate_control_caps; 894 unsigned int psr_power_opt_flag; 895 }; 896 897 /* Length of router topology ID read from DPCD in bytes. */ 898 #define DPCD_USB4_TOPOLOGY_ID_LEN 5 899 900 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */ 901 union dp_tun_cap_support { 902 struct { 903 uint8_t dp_tunneling :1; 904 uint8_t rsvd :5; 905 uint8_t panel_replay_tun_opt :1; 906 uint8_t dpia_bw_alloc :1; 907 } bits; 908 uint8_t raw; 909 }; 910 911 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */ 912 union dpia_info { 913 struct { 914 uint8_t dpia_num :5; 915 uint8_t rsvd :3; 916 } bits; 917 uint8_t raw; 918 }; 919 920 /* DP Tunneling over USB4 */ 921 struct dpcd_usb4_dp_tunneling_info { 922 union dp_tun_cap_support dp_tun_cap; 923 union dpia_info dpia_info; 924 uint8_t usb4_driver_id; 925 uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN]; 926 }; 927 928 #if defined(CONFIG_DRM_AMD_DC_DCN) 929 #ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP 930 #define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006 931 #endif 932 #ifndef DP_SINK_VIDEO_FALLBACK_FORMATS 933 #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 934 #endif 935 #ifndef DP_FEC_CAPABILITY_1 936 #define DP_FEC_CAPABILITY_1 0x091 937 #endif 938 #ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT 939 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 940 #endif 941 #ifndef DP_LINK_SQUARE_PATTERN 942 #define DP_LINK_SQUARE_PATTERN 0x10F 943 #endif 944 #ifndef DP_DSC_CONFIGURATION 945 #define DP_DSC_CONFIGURATION 0x161 946 #endif 947 #ifndef DP_PHY_SQUARE_PATTERN 948 #define DP_PHY_SQUARE_PATTERN 0x249 949 #endif 950 #ifndef DP_128b_132b_SUPPORTED_LINK_RATES 951 #define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215 952 #endif 953 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL 954 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216 955 #endif 956 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0 957 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230 958 #endif 959 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256 960 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 961 #endif 962 #ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT 963 #define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260 964 #endif 965 #ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 966 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 967 #endif 968 #ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK 969 #define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) 970 #endif 971 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK 972 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) 973 #endif 974 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 975 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 976 #endif 977 #ifndef DP_DSC_DECODER_COUNT_MASK 978 #define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) 979 #endif 980 #ifndef DP_DSC_DECODER_COUNT_SHIFT 981 #define DP_DSC_DECODER_COUNT_SHIFT 5 982 #endif 983 #ifndef DP_MAIN_LINK_CHANNEL_CODING_SET 984 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 985 #endif 986 #ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 987 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 988 #endif 989 #ifndef DP_PHY_REPEATER_128b_132b_RATES 990 #define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 991 #endif 992 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 993 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 994 #endif 995 #ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION 996 #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) 997 #endif 998 /* TODO - Use DRM header to replace above once available */ 999 1000 union dp_main_line_channel_coding_cap { 1001 struct { 1002 uint8_t DP_8b_10b_SUPPORTED :1; 1003 uint8_t DP_128b_132b_SUPPORTED :1; 1004 uint8_t RESERVED :6; 1005 } bits; 1006 uint8_t raw; 1007 }; 1008 1009 union dp_main_link_channel_coding_lttpr_cap { 1010 struct { 1011 uint8_t DP_128b_132b_SUPPORTED :1; 1012 uint8_t RESERVED :7; 1013 } bits; 1014 uint8_t raw; 1015 }; 1016 1017 union dp_128b_132b_supported_link_rates { 1018 struct { 1019 uint8_t UHBR10 :1; 1020 uint8_t UHBR20 :1; 1021 uint8_t UHBR13_5:1; 1022 uint8_t RESERVED:5; 1023 } bits; 1024 uint8_t raw; 1025 }; 1026 1027 union dp_128b_132b_supported_lttpr_link_rates { 1028 struct { 1029 uint8_t UHBR10 :1; 1030 uint8_t UHBR13_5:1; 1031 uint8_t UHBR20 :1; 1032 uint8_t RESERVED:5; 1033 } bits; 1034 uint8_t raw; 1035 }; 1036 1037 union dp_sink_video_fallback_formats { 1038 struct { 1039 uint8_t dp_1024x768_60Hz_24bpp_support :1; 1040 uint8_t dp_1280x720_60Hz_24bpp_support :1; 1041 uint8_t dp_1920x1080_60Hz_24bpp_support :1; 1042 uint8_t RESERVED :5; 1043 } bits; 1044 uint8_t raw; 1045 }; 1046 1047 union dp_fec_capability1 { 1048 struct { 1049 uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE :1; 1050 uint8_t RESERVED :7; 1051 } bits; 1052 uint8_t raw; 1053 }; 1054 1055 struct dp_color_depth_caps { 1056 uint8_t support_6bpc :1; 1057 uint8_t support_8bpc :1; 1058 uint8_t support_10bpc :1; 1059 uint8_t support_12bpc :1; 1060 uint8_t support_16bpc :1; 1061 uint8_t RESERVED :3; 1062 }; 1063 1064 struct dp_encoding_format_caps { 1065 uint8_t support_rgb :1; 1066 uint8_t support_ycbcr444:1; 1067 uint8_t support_ycbcr422:1; 1068 uint8_t support_ycbcr420:1; 1069 uint8_t RESERVED :4; 1070 }; 1071 1072 union dp_dfp_cap_ext { 1073 struct { 1074 uint8_t supported; 1075 uint8_t max_pixel_rate_in_mps[2]; 1076 uint8_t max_video_h_active_width[2]; 1077 uint8_t max_video_v_active_height[2]; 1078 struct dp_encoding_format_caps encoding_format_caps; 1079 struct dp_color_depth_caps rgb_color_depth_caps; 1080 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1081 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1082 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1083 } fields; 1084 uint8_t raw[12]; 1085 }; 1086 1087 union dp_128b_132b_training_aux_rd_interval { 1088 struct { 1089 uint8_t VALUE :7; 1090 uint8_t UNIT :1; 1091 } bits; 1092 uint8_t raw; 1093 }; 1094 #endif 1095 1096 #endif /* DC_DP_TYPES_H */ 1097