1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 31 enum dc_lane_count { 32 LANE_COUNT_UNKNOWN = 0, 33 LANE_COUNT_ONE = 1, 34 LANE_COUNT_TWO = 2, 35 LANE_COUNT_FOUR = 4, 36 LANE_COUNT_EIGHT = 8, 37 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 38 }; 39 40 /* This is actually a reference clock (27MHz) multiplier 41 * 162MBps bandwidth for 1.62GHz like rate, 42 * 270MBps for 2.70GHz, 43 * 324MBps for 3.24Ghz, 44 * 540MBps for 5.40GHz 45 * 810MBps for 8.10GHz 46 */ 47 enum dc_link_rate { 48 LINK_RATE_UNKNOWN = 0, 49 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 50 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 51 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 52 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 53 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane 54 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 55 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane 56 LINK_RATE_HIGH3 = 0x1E, // Rate_8 (HBR3)- 8.10 Gbps/Lane 57 /* Starting from DP2.0 link rate enum directly represents actual 58 * link rate value in unit of 10 mbps 59 */ 60 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane 61 LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane 62 LINK_RATE_UHBR20 = 2000, // UHBR10 - 20.0 Gbps/Lane 63 }; 64 65 enum dc_link_spread { 66 LINK_SPREAD_DISABLED = 0x00, 67 /* 0.5 % downspread 30 kHz */ 68 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 69 /* 0.5 % downspread 33 kHz */ 70 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 71 }; 72 73 enum dc_voltage_swing { 74 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 75 VOLTAGE_SWING_LEVEL1, 76 VOLTAGE_SWING_LEVEL2, 77 VOLTAGE_SWING_LEVEL3, 78 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 79 }; 80 81 enum dc_pre_emphasis { 82 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 83 PRE_EMPHASIS_LEVEL1, 84 PRE_EMPHASIS_LEVEL2, 85 PRE_EMPHASIS_LEVEL3, 86 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 87 }; 88 /* Post Cursor 2 is optional for transmitter 89 * and it applies only to the main link operating at HBR2 90 */ 91 enum dc_post_cursor2 { 92 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 93 POST_CURSOR2_LEVEL1, 94 POST_CURSOR2_LEVEL2, 95 POST_CURSOR2_LEVEL3, 96 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 97 }; 98 99 enum dc_dp_ffe_preset_level { 100 DP_FFE_PRESET_LEVEL0 = 0, 101 DP_FFE_PRESET_LEVEL1, 102 DP_FFE_PRESET_LEVEL2, 103 DP_FFE_PRESET_LEVEL3, 104 DP_FFE_PRESET_LEVEL4, 105 DP_FFE_PRESET_LEVEL5, 106 DP_FFE_PRESET_LEVEL6, 107 DP_FFE_PRESET_LEVEL7, 108 DP_FFE_PRESET_LEVEL8, 109 DP_FFE_PRESET_LEVEL9, 110 DP_FFE_PRESET_LEVEL10, 111 DP_FFE_PRESET_LEVEL11, 112 DP_FFE_PRESET_LEVEL12, 113 DP_FFE_PRESET_LEVEL13, 114 DP_FFE_PRESET_LEVEL14, 115 DP_FFE_PRESET_LEVEL15, 116 DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15, 117 }; 118 119 enum dc_dp_training_pattern { 120 DP_TRAINING_PATTERN_SEQUENCE_1 = 0, 121 DP_TRAINING_PATTERN_SEQUENCE_2, 122 DP_TRAINING_PATTERN_SEQUENCE_3, 123 DP_TRAINING_PATTERN_SEQUENCE_4, 124 DP_TRAINING_PATTERN_VIDEOIDLE, 125 DP_128b_132b_TPS1, 126 DP_128b_132b_TPS2, 127 DP_128b_132b_TPS2_CDS, 128 }; 129 130 enum dp_link_encoding { 131 DP_UNKNOWN_ENCODING = 0, 132 DP_8b_10b_ENCODING = 1, 133 DP_128b_132b_ENCODING = 2, 134 }; 135 136 struct dc_link_settings { 137 enum dc_lane_count lane_count; 138 enum dc_link_rate link_rate; 139 enum dc_link_spread link_spread; 140 bool use_link_rate_set; 141 uint8_t link_rate_set; 142 bool dpcd_source_device_specific_field_support; 143 }; 144 145 union dc_dp_ffe_preset { 146 struct { 147 uint8_t level : 4; 148 uint8_t reserved : 1; 149 uint8_t no_preshoot : 1; 150 uint8_t no_deemphasis : 1; 151 uint8_t method2 : 1; 152 } settings; 153 uint8_t raw; 154 }; 155 156 struct dc_lane_settings { 157 enum dc_voltage_swing VOLTAGE_SWING; 158 enum dc_pre_emphasis PRE_EMPHASIS; 159 enum dc_post_cursor2 POST_CURSOR2; 160 union dc_dp_ffe_preset FFE_PRESET; 161 }; 162 163 struct dc_link_training_overrides { 164 enum dc_voltage_swing *voltage_swing; 165 enum dc_pre_emphasis *pre_emphasis; 166 enum dc_post_cursor2 *post_cursor2; 167 union dc_dp_ffe_preset *ffe_preset; 168 169 uint16_t *cr_pattern_time; 170 uint16_t *eq_pattern_time; 171 enum dc_dp_training_pattern *pattern_for_cr; 172 enum dc_dp_training_pattern *pattern_for_eq; 173 174 enum dc_link_spread *downspread; 175 bool *alternate_scrambler_reset; 176 bool *enhanced_framing; 177 bool *mst_enable; 178 bool *fec_enable; 179 }; 180 181 union payload_table_update_status { 182 struct { 183 uint8_t VC_PAYLOAD_TABLE_UPDATED:1; 184 uint8_t ACT_HANDLED:1; 185 } bits; 186 uint8_t raw; 187 }; 188 189 union dpcd_rev { 190 struct { 191 uint8_t MINOR:4; 192 uint8_t MAJOR:4; 193 } bits; 194 uint8_t raw; 195 }; 196 197 union max_lane_count { 198 struct { 199 uint8_t MAX_LANE_COUNT:5; 200 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 201 uint8_t TPS3_SUPPORTED:1; 202 uint8_t ENHANCED_FRAME_CAP:1; 203 } bits; 204 uint8_t raw; 205 }; 206 207 union max_down_spread { 208 struct { 209 uint8_t MAX_DOWN_SPREAD:1; 210 uint8_t RESERVED:5; 211 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 212 uint8_t TPS4_SUPPORTED:1; 213 } bits; 214 uint8_t raw; 215 }; 216 217 union mstm_cap { 218 struct { 219 uint8_t MST_CAP:1; 220 uint8_t RESERVED:7; 221 } bits; 222 uint8_t raw; 223 }; 224 225 union lane_count_set { 226 struct { 227 uint8_t LANE_COUNT_SET:5; 228 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 229 uint8_t RESERVED:1; 230 uint8_t ENHANCED_FRAMING:1; 231 } bits; 232 uint8_t raw; 233 }; 234 235 union lane_status { 236 struct { 237 uint8_t CR_DONE_0:1; 238 uint8_t CHANNEL_EQ_DONE_0:1; 239 uint8_t SYMBOL_LOCKED_0:1; 240 uint8_t RESERVED0:1; 241 uint8_t CR_DONE_1:1; 242 uint8_t CHANNEL_EQ_DONE_1:1; 243 uint8_t SYMBOL_LOCKED_1:1; 244 uint8_t RESERVED_1:1; 245 } bits; 246 uint8_t raw; 247 }; 248 249 union device_service_irq { 250 struct { 251 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 252 uint8_t AUTOMATED_TEST:1; 253 uint8_t CP_IRQ:1; 254 uint8_t MCCS_IRQ:1; 255 uint8_t DOWN_REP_MSG_RDY:1; 256 uint8_t UP_REQ_MSG_RDY:1; 257 uint8_t SINK_SPECIFIC:1; 258 uint8_t reserved:1; 259 } bits; 260 uint8_t raw; 261 }; 262 263 union sink_count { 264 struct { 265 uint8_t SINK_COUNT:6; 266 uint8_t CPREADY:1; 267 uint8_t RESERVED:1; 268 } bits; 269 uint8_t raw; 270 }; 271 272 union lane_align_status_updated { 273 struct { 274 uint8_t INTERLANE_ALIGN_DONE:1; 275 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 276 uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1; 277 uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1; 278 uint8_t LT_FAILED_128b_132b:1; 279 uint8_t RESERVED:1; 280 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 281 uint8_t LINK_STATUS_UPDATED:1; 282 } bits; 283 uint8_t raw; 284 }; 285 286 union lane_adjust { 287 struct { 288 uint8_t VOLTAGE_SWING_LANE:2; 289 uint8_t PRE_EMPHASIS_LANE:2; 290 uint8_t RESERVED:4; 291 } bits; 292 struct { 293 uint8_t PRESET_VALUE :4; 294 uint8_t RESERVED :4; 295 } tx_ffe; 296 uint8_t raw; 297 }; 298 299 union dpcd_training_pattern { 300 struct { 301 uint8_t TRAINING_PATTERN_SET:4; 302 uint8_t RECOVERED_CLOCK_OUT_EN:1; 303 uint8_t SCRAMBLING_DISABLE:1; 304 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 305 } v1_4; 306 struct { 307 uint8_t TRAINING_PATTERN_SET:2; 308 uint8_t LINK_QUAL_PATTERN_SET:2; 309 uint8_t RESERVED:4; 310 } v1_3; 311 uint8_t raw; 312 }; 313 314 /* Training Lane is used to configure downstream DP device's voltage swing 315 and pre-emphasis levels*/ 316 /* The DPCD addresses are from 0x103 to 0x106*/ 317 union dpcd_training_lane { 318 struct { 319 uint8_t VOLTAGE_SWING_SET:2; 320 uint8_t MAX_SWING_REACHED:1; 321 uint8_t PRE_EMPHASIS_SET:2; 322 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 323 uint8_t RESERVED:2; 324 } bits; 325 struct { 326 uint8_t PRESET_VALUE :4; 327 uint8_t RESERVED :4; 328 } tx_ffe; 329 uint8_t raw; 330 }; 331 332 /* TMDS-converter related */ 333 union dwnstream_port_caps_byte0 { 334 struct { 335 uint8_t DWN_STRM_PORTX_TYPE:3; 336 uint8_t DWN_STRM_PORTX_HPD:1; 337 uint8_t RESERVERD:4; 338 } bits; 339 uint8_t raw; 340 }; 341 342 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 343 enum dpcd_downstream_port_detailed_type { 344 DOWN_STREAM_DETAILED_DP = 0, 345 DOWN_STREAM_DETAILED_VGA, 346 DOWN_STREAM_DETAILED_DVI, 347 DOWN_STREAM_DETAILED_HDMI, 348 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 349 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 350 }; 351 352 union dwnstream_port_caps_byte2 { 353 struct { 354 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 355 #if defined(CONFIG_DRM_AMD_DC_DCN) 356 uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3; 357 uint8_t SOURCE_CONTROL_MODE_SUPPORT:1; 358 uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1; 359 uint8_t RESERVED:1; 360 #else 361 uint8_t RESERVED:6; 362 #endif 363 } bits; 364 uint8_t raw; 365 }; 366 367 union dp_downstream_port_present { 368 uint8_t byte; 369 struct { 370 uint8_t PORT_PRESENT:1; 371 uint8_t PORT_TYPE:2; 372 uint8_t FMT_CONVERSION:1; 373 uint8_t DETAILED_CAPS:1; 374 uint8_t RESERVED:3; 375 } fields; 376 }; 377 378 union dwnstream_port_caps_byte3_dvi { 379 struct { 380 uint8_t RESERVED1:1; 381 uint8_t DUAL_LINK:1; 382 uint8_t HIGH_COLOR_DEPTH:1; 383 uint8_t RESERVED2:5; 384 } bits; 385 uint8_t raw; 386 }; 387 388 union dwnstream_port_caps_byte3_hdmi { 389 struct { 390 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 391 uint8_t YCrCr422_PASS_THROUGH:1; 392 uint8_t YCrCr420_PASS_THROUGH:1; 393 uint8_t YCrCr422_CONVERSION:1; 394 uint8_t YCrCr420_CONVERSION:1; 395 uint8_t RESERVED:3; 396 } bits; 397 uint8_t raw; 398 }; 399 400 #if defined(CONFIG_DRM_AMD_DC_DCN) 401 union hdmi_sink_encoded_link_bw_support { 402 struct { 403 uint8_t HDMI_SINK_ENCODED_LINK_BW_SUPPORT:3; 404 uint8_t RESERVED:5; 405 } bits; 406 uint8_t raw; 407 }; 408 409 union hdmi_encoded_link_bw { 410 struct { 411 uint8_t FRL_MODE:1; // Bit 0 412 uint8_t BW_9Gbps:1; 413 uint8_t BW_18Gbps:1; 414 uint8_t BW_24Gbps:1; 415 uint8_t BW_32Gbps:1; 416 uint8_t BW_40Gbps:1; 417 uint8_t BW_48Gbps:1; 418 uint8_t RESERVED:1; // Bit 7 419 } bits; 420 uint8_t raw; 421 }; 422 #endif 423 424 /*4-byte structure for detailed capabilities of a down-stream port 425 (DP-to-TMDS converter).*/ 426 union dwnstream_portxcaps { 427 struct { 428 union dwnstream_port_caps_byte0 byte0; 429 unsigned char max_TMDS_clock; //byte1 430 union dwnstream_port_caps_byte2 byte2; 431 432 union { 433 union dwnstream_port_caps_byte3_dvi byteDVI; 434 union dwnstream_port_caps_byte3_hdmi byteHDMI; 435 } byte3; 436 } bytes; 437 438 unsigned char raw[4]; 439 }; 440 441 union downstream_port { 442 struct { 443 unsigned char present:1; 444 unsigned char type:2; 445 unsigned char format_conv:1; 446 unsigned char detailed_caps:1; 447 unsigned char reserved:3; 448 } bits; 449 unsigned char raw; 450 }; 451 452 453 union sink_status { 454 struct { 455 uint8_t RX_PORT0_STATUS:1; 456 uint8_t RX_PORT1_STATUS:1; 457 uint8_t RESERVED:6; 458 } bits; 459 uint8_t raw; 460 }; 461 462 /*6-byte structure corresponding to 6 registers (200h-205h) 463 read during handling of HPD-IRQ*/ 464 union hpd_irq_data { 465 struct { 466 union sink_count sink_cnt;/* 200h */ 467 union device_service_irq device_service_irq;/* 201h */ 468 union lane_status lane01_status;/* 202h */ 469 union lane_status lane23_status;/* 203h */ 470 union lane_align_status_updated lane_status_updated;/* 204h */ 471 union sink_status sink_status; 472 } bytes; 473 uint8_t raw[6]; 474 }; 475 476 union down_stream_port_count { 477 struct { 478 uint8_t DOWN_STR_PORT_COUNT:4; 479 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 480 /*Bit 6 = MSA_TIMING_PAR_IGNORED 481 0 = Sink device requires the MSA timing parameters 482 1 = Sink device is capable of rendering incoming video 483 stream without MSA timing parameters*/ 484 uint8_t IGNORE_MSA_TIMING_PARAM:1; 485 /*Bit 7 = OUI Support 486 0 = OUI not supported 487 1 = OUI supported 488 (OUI and Device Identification mandatory for DP 1.2)*/ 489 uint8_t OUI_SUPPORT:1; 490 } bits; 491 uint8_t raw; 492 }; 493 494 union down_spread_ctrl { 495 struct { 496 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 497 /* Bits 4 = SPREAD_AMP. Spreading amplitude 498 0 = Main link signal is not downspread 499 1 = Main link signal is downspread <= 0.5% 500 with frequency in the range of 30kHz ~ 33kHz*/ 501 uint8_t SPREAD_AMP:1; 502 uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/ 503 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 504 0 = Source device will send valid data for the MSA Timing Params 505 1 = Source device may send invalid data for these MSA Timing Params*/ 506 uint8_t IGNORE_MSA_TIMING_PARAM:1; 507 } bits; 508 uint8_t raw; 509 }; 510 511 union dpcd_edp_config { 512 struct { 513 uint8_t PANEL_MODE_EDP:1; 514 uint8_t FRAMING_CHANGE_ENABLE:1; 515 uint8_t RESERVED:5; 516 uint8_t PANEL_SELF_TEST_ENABLE:1; 517 } bits; 518 uint8_t raw; 519 }; 520 521 struct dp_device_vendor_id { 522 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 523 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 524 }; 525 526 struct dp_sink_hw_fw_revision { 527 uint8_t ieee_hw_rev; 528 uint8_t ieee_fw_rev[2]; 529 }; 530 531 struct dpcd_vendor_signature { 532 bool is_valid; 533 534 union dpcd_ieee_vendor_signature { 535 struct { 536 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 537 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 538 uint8_t ieee_hw_rev; 539 uint8_t ieee_fw_rev[2]; 540 }; 541 uint8_t raw[12]; 542 } data; 543 }; 544 545 struct dpcd_amd_signature { 546 uint8_t AMD_IEEE_TxSignature_byte1; 547 uint8_t AMD_IEEE_TxSignature_byte2; 548 uint8_t AMD_IEEE_TxSignature_byte3; 549 }; 550 551 struct dpcd_amd_device_id { 552 uint8_t device_id_byte1; 553 uint8_t device_id_byte2; 554 uint8_t zero[4]; 555 uint8_t dce_version; 556 uint8_t dal_version_byte1; 557 uint8_t dal_version_byte2; 558 }; 559 560 struct dpcd_source_backlight_set { 561 struct { 562 uint8_t byte0; 563 uint8_t byte1; 564 uint8_t byte2; 565 uint8_t byte3; 566 } backlight_level_millinits; 567 568 struct { 569 uint8_t byte0; 570 uint8_t byte1; 571 } backlight_transition_time_ms; 572 }; 573 574 union dpcd_source_backlight_get { 575 struct { 576 uint32_t backlight_millinits_peak; /* 326h */ 577 uint32_t backlight_millinits_avg; /* 32Ah */ 578 } bytes; 579 uint8_t raw[8]; 580 }; 581 582 /*DPCD register of DP receiver capability field bits-*/ 583 union edp_configuration_cap { 584 struct { 585 uint8_t ALT_SCRAMBLER_RESET:1; 586 uint8_t FRAMING_CHANGE:1; 587 uint8_t RESERVED:1; 588 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 589 uint8_t RESERVED2:4; 590 } bits; 591 uint8_t raw; 592 }; 593 594 union dprx_feature { 595 struct { 596 uint8_t GTC_CAP:1; // bit 0: DP 1.3+ 597 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4 598 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+ 599 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+ 600 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4 601 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4 602 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4 603 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4 604 } bits; 605 uint8_t raw; 606 }; 607 608 union training_aux_rd_interval { 609 struct { 610 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 611 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1; 612 } bits; 613 uint8_t raw; 614 }; 615 616 /* Automated test structures */ 617 union test_request { 618 struct { 619 uint8_t LINK_TRAINING :1; 620 uint8_t LINK_TEST_PATTRN :1; 621 uint8_t EDID_READ :1; 622 uint8_t PHY_TEST_PATTERN :1; 623 uint8_t RESERVED :1; 624 uint8_t AUDIO_TEST_PATTERN :1; 625 uint8_t TEST_AUDIO_DISABLED_VIDEO :1; 626 } bits; 627 uint8_t raw; 628 }; 629 630 union test_response { 631 struct { 632 uint8_t ACK :1; 633 uint8_t NO_ACK :1; 634 uint8_t EDID_CHECKSUM_WRITE:1; 635 uint8_t RESERVED :5; 636 } bits; 637 uint8_t raw; 638 }; 639 640 union phy_test_pattern { 641 struct { 642 /* This field is 7 bits for DP2.0 */ 643 uint8_t PATTERN :7; 644 uint8_t RESERVED :1; 645 } bits; 646 uint8_t raw; 647 }; 648 649 /* States of Compliance Test Specification (CTS DP1.2). */ 650 union compliance_test_state { 651 struct { 652 unsigned char STEREO_3D_RUNNING : 1; 653 unsigned char RESERVED : 7; 654 } bits; 655 unsigned char raw; 656 }; 657 658 union link_test_pattern { 659 struct { 660 /* dpcd_link_test_patterns */ 661 unsigned char PATTERN :2; 662 unsigned char RESERVED:6; 663 } bits; 664 unsigned char raw; 665 }; 666 667 union test_misc { 668 struct dpcd_test_misc_bits { 669 unsigned char SYNC_CLOCK :1; 670 /* dpcd_test_color_format */ 671 unsigned char CLR_FORMAT :2; 672 /* dpcd_test_dyn_range */ 673 unsigned char DYN_RANGE :1; 674 unsigned char YCBCR_COEFS :1; 675 /* dpcd_test_bit_depth */ 676 unsigned char BPC :3; 677 } bits; 678 unsigned char raw; 679 }; 680 681 union audio_test_mode { 682 struct { 683 unsigned char sampling_rate :4; 684 unsigned char channel_count :4; 685 } bits; 686 unsigned char raw; 687 }; 688 689 union audio_test_pattern_period { 690 struct { 691 unsigned char pattern_period :4; 692 unsigned char reserved :4; 693 } bits; 694 unsigned char raw; 695 }; 696 697 struct audio_test_pattern_type { 698 unsigned char value; 699 }; 700 701 struct dp_audio_test_data_flags { 702 uint8_t test_requested :1; 703 uint8_t disable_video :1; 704 }; 705 706 struct dp_audio_test_data { 707 708 struct dp_audio_test_data_flags flags; 709 uint8_t sampling_rate; 710 uint8_t channel_count; 711 uint8_t pattern_type; 712 uint8_t pattern_period[8]; 713 }; 714 715 /* FEC capability DPCD register field bits-*/ 716 union dpcd_fec_capability { 717 struct { 718 uint8_t FEC_CAPABLE:1; 719 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 720 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 721 uint8_t BIT_ERROR_COUNT_CAPABLE:1; 722 uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1; 723 uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1; 724 uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1; 725 uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1; 726 } bits; 727 uint8_t raw; 728 }; 729 730 /* DSC capability DPCD register field bits-*/ 731 struct dpcd_dsc_support { 732 uint8_t DSC_SUPPORT :1; 733 uint8_t DSC_PASSTHROUGH_SUPPORT :1; 734 uint8_t RESERVED :6; 735 }; 736 737 struct dpcd_dsc_algorithm_revision { 738 uint8_t DSC_VERSION_MAJOR :4; 739 uint8_t DSC_VERSION_MINOR :4; 740 }; 741 742 struct dpcd_dsc_rc_buffer_block_size { 743 uint8_t RC_BLOCK_BUFFER_SIZE :2; 744 uint8_t RESERVED :6; 745 }; 746 747 struct dpcd_dsc_slice_capability1 { 748 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; 749 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; 750 uint8_t RESERVED :1; 751 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; 752 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; 753 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; 754 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; 755 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; 756 }; 757 758 struct dpcd_dsc_line_buffer_bit_depth { 759 uint8_t LINE_BUFFER_BIT_DEPTH :4; 760 uint8_t RESERVED :4; 761 }; 762 763 struct dpcd_dsc_block_prediction_support { 764 uint8_t BLOCK_PREDICTION_SUPPORT:1; 765 uint8_t RESERVED :7; 766 }; 767 768 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { 769 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; 770 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; 771 uint8_t RESERVED :2; 772 }; 773 774 struct dpcd_dsc_decoder_color_format_capabilities { 775 uint8_t RGB_SUPPORT :1; 776 uint8_t Y_CB_CR_444_SUPPORT :1; 777 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; 778 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; 779 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; 780 uint8_t RESERVED :3; 781 }; 782 783 struct dpcd_dsc_decoder_color_depth_capabilities { 784 uint8_t RESERVED0 :1; 785 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; 786 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; 787 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; 788 uint8_t RESERVED1 :4; 789 }; 790 791 struct dpcd_peak_dsc_throughput_dsc_sink { 792 uint8_t THROUGHPUT_MODE_0:4; 793 uint8_t THROUGHPUT_MODE_1:4; 794 }; 795 796 struct dpcd_dsc_slice_capabilities_2 { 797 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; 798 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; 799 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; 800 uint8_t RESERVED :5; 801 }; 802 803 struct dpcd_bits_per_pixel_increment{ 804 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; 805 uint8_t RESERVED :5; 806 }; 807 union dpcd_dsc_basic_capabilities { 808 struct { 809 struct dpcd_dsc_support dsc_support; 810 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; 811 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; 812 uint8_t dsc_rc_buffer_size; 813 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; 814 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; 815 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; 816 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; 817 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; 818 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; 819 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; 820 uint8_t dsc_maximum_slice_width; 821 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; 822 uint8_t reserved; 823 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; 824 } fields; 825 uint8_t raw[16]; 826 }; 827 828 union dpcd_dsc_branch_decoder_capabilities { 829 struct { 830 uint8_t BRANCH_OVERALL_THROUGHPUT_0; 831 uint8_t BRANCH_OVERALL_THROUGHPUT_1; 832 uint8_t BRANCH_MAX_LINE_WIDTH; 833 } fields; 834 uint8_t raw[3]; 835 }; 836 837 struct dpcd_dsc_capabilities { 838 union dpcd_dsc_basic_capabilities dsc_basic_caps; 839 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps; 840 }; 841 842 /* These parameters are from PSR capabilities reported by Sink DPCD */ 843 struct psr_caps { 844 unsigned char psr_version; 845 unsigned int psr_rfb_setup_time; 846 bool psr_exit_link_training_required; 847 unsigned char edp_revision; 848 unsigned char support_ver; 849 bool su_granularity_required; 850 bool y_coordinate_required; 851 uint8_t su_y_granularity; 852 bool alpm_cap; 853 bool standby_support; 854 uint8_t rate_control_caps; 855 unsigned int psr_power_opt_flag; 856 }; 857 858 /* Length of router topology ID read from DPCD in bytes. */ 859 #define DPCD_USB4_TOPOLOGY_ID_LEN 5 860 861 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */ 862 union dp_tun_cap_support { 863 struct { 864 uint8_t dp_tunneling :1; 865 uint8_t rsvd :5; 866 uint8_t panel_replay_tun_opt :1; 867 uint8_t dpia_bw_alloc :1; 868 } bits; 869 uint8_t raw; 870 }; 871 872 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */ 873 union dpia_info { 874 struct { 875 uint8_t dpia_num :5; 876 uint8_t rsvd :3; 877 } bits; 878 uint8_t raw; 879 }; 880 881 /* DP Tunneling over USB4 */ 882 struct dpcd_usb4_dp_tunneling_info { 883 union dp_tun_cap_support dp_tun_cap; 884 union dpia_info dpia_info; 885 uint8_t usb4_driver_id; 886 uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN]; 887 }; 888 889 #ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP 890 #define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006 891 #endif 892 #ifndef DP_SINK_VIDEO_FALLBACK_FORMATS 893 #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 894 #endif 895 #ifndef DP_FEC_CAPABILITY_1 896 #define DP_FEC_CAPABILITY_1 0x091 897 #endif 898 #ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT 899 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 900 #endif 901 #ifndef DP_LINK_SQUARE_PATTERN 902 #define DP_LINK_SQUARE_PATTERN 0x10F 903 #endif 904 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 905 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 0x110 906 #endif 907 #ifndef DP_DSC_CONFIGURATION 908 #define DP_DSC_CONFIGURATION 0x161 909 #endif 910 #ifndef DP_PHY_SQUARE_PATTERN 911 #define DP_PHY_SQUARE_PATTERN 0x249 912 #endif 913 #ifndef DP_128b_132b_SUPPORTED_LINK_RATES 914 #define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215 915 #endif 916 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL 917 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216 918 #endif 919 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 920 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 0x2217 921 #endif 922 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0 923 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230 924 #endif 925 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256 926 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 927 #endif 928 #ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT 929 #define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260 930 #endif 931 #ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 932 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 933 #endif 934 #ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK 935 #define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) 936 #endif 937 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK 938 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) 939 #endif 940 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 941 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 942 #endif 943 #ifndef DP_DSC_DECODER_COUNT_MASK 944 #define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) 945 #endif 946 #ifndef DP_DSC_DECODER_COUNT_SHIFT 947 #define DP_DSC_DECODER_COUNT_SHIFT 5 948 #endif 949 #ifndef DP_MAIN_LINK_CHANNEL_CODING_SET 950 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 951 #endif 952 #ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 953 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 954 #endif 955 #ifndef DP_PHY_REPEATER_128b_132b_RATES 956 #define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 957 #endif 958 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 959 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 960 #endif 961 #ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION 962 #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) 963 /* TODO - Use DRM header to replace above once available */ 964 #endif // DP_INTRA_HOP_AUX_REPLY_INDICATION 965 966 union dp_main_line_channel_coding_cap { 967 struct { 968 uint8_t DP_8b_10b_SUPPORTED :1; 969 uint8_t DP_128b_132b_SUPPORTED :1; 970 uint8_t RESERVED :6; 971 } bits; 972 uint8_t raw; 973 }; 974 975 union dp_main_link_channel_coding_lttpr_cap { 976 struct { 977 uint8_t DP_128b_132b_SUPPORTED :1; 978 uint8_t RESERVED :7; 979 } bits; 980 uint8_t raw; 981 }; 982 983 union dp_128b_132b_supported_link_rates { 984 struct { 985 uint8_t UHBR10 :1; 986 uint8_t UHBR20 :1; 987 uint8_t UHBR13_5:1; 988 uint8_t RESERVED:5; 989 } bits; 990 uint8_t raw; 991 }; 992 993 union dp_128b_132b_supported_lttpr_link_rates { 994 struct { 995 uint8_t UHBR10 :1; 996 uint8_t UHBR13_5:1; 997 uint8_t UHBR20 :1; 998 uint8_t RESERVED:5; 999 } bits; 1000 uint8_t raw; 1001 }; 1002 1003 union dp_sink_video_fallback_formats { 1004 struct { 1005 uint8_t dp_1024x768_60Hz_24bpp_support :1; 1006 uint8_t dp_1280x720_60Hz_24bpp_support :1; 1007 uint8_t dp_1920x1080_60Hz_24bpp_support :1; 1008 uint8_t RESERVED :5; 1009 } bits; 1010 uint8_t raw; 1011 }; 1012 1013 union dp_fec_capability1 { 1014 struct { 1015 uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE :1; 1016 uint8_t RESERVED :7; 1017 } bits; 1018 uint8_t raw; 1019 }; 1020 1021 union dp_cable_id { 1022 struct { 1023 uint8_t UHBR10_20_CAPABILITY :2; 1024 uint8_t UHBR13_5_CAPABILITY :1; 1025 uint8_t CABLE_TYPE :3; 1026 uint8_t RESERVED :2; 1027 } bits; 1028 uint8_t raw; 1029 }; 1030 1031 struct dp_color_depth_caps { 1032 uint8_t support_6bpc :1; 1033 uint8_t support_8bpc :1; 1034 uint8_t support_10bpc :1; 1035 uint8_t support_12bpc :1; 1036 uint8_t support_16bpc :1; 1037 uint8_t RESERVED :3; 1038 }; 1039 1040 struct dp_encoding_format_caps { 1041 uint8_t support_rgb :1; 1042 uint8_t support_ycbcr444:1; 1043 uint8_t support_ycbcr422:1; 1044 uint8_t support_ycbcr420:1; 1045 uint8_t RESERVED :4; 1046 }; 1047 1048 union dp_dfp_cap_ext { 1049 struct { 1050 uint8_t supported; 1051 uint8_t max_pixel_rate_in_mps[2]; 1052 uint8_t max_video_h_active_width[2]; 1053 uint8_t max_video_v_active_height[2]; 1054 struct dp_encoding_format_caps encoding_format_caps; 1055 struct dp_color_depth_caps rgb_color_depth_caps; 1056 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1057 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1058 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1059 } fields; 1060 uint8_t raw[12]; 1061 }; 1062 1063 union dp_128b_132b_training_aux_rd_interval { 1064 struct { 1065 uint8_t VALUE :7; 1066 uint8_t UNIT :1; 1067 } bits; 1068 uint8_t raw; 1069 }; 1070 1071 union edp_alpm_caps { 1072 struct { 1073 uint8_t AUX_WAKE_ALPM_CAP :1; 1074 uint8_t PM_STATE_2A_SUPPORT :1; 1075 uint8_t AUX_LESS_ALPM_CAP :1; 1076 uint8_t RESERVED :5; 1077 } bits; 1078 uint8_t raw; 1079 }; 1080 1081 union edp_psr_dpcd_caps { 1082 struct { 1083 uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED :1; 1084 uint8_t PSR_SETUP_TIME :3; 1085 uint8_t Y_COORDINATE_REQUIRED :1; 1086 uint8_t SU_GRANULARITY_REQUIRED :1; 1087 uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1; 1088 uint8_t RESERVED :1; 1089 } bits; 1090 uint8_t raw; 1091 }; 1092 1093 struct edp_psr_info { 1094 uint8_t psr_version; 1095 union edp_psr_dpcd_caps psr_dpcd_caps; 1096 uint8_t psr2_su_y_granularity_cap; 1097 uint8_t force_psrsu_cap; 1098 }; 1099 1100 #endif /* DC_DP_TYPES_H */ 1101