1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dc.h"
27 #include "dc_dmub_srv.h"
28 #include "../dmub/dmub_srv.h"
29 #include "dm_helpers.h"
30 #include "dc_hw_types.h"
31 #include "core_types.h"
32 #include "../basics/conversion.h"
33 #include "cursor_reg_cache.h"
34 
35 #define CTX dc_dmub_srv->ctx
36 #define DC_LOGGER CTX->logger
37 
38 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,
39 				  struct dmub_srv *dmub)
40 {
41 	dc_srv->dmub = dmub;
42 	dc_srv->ctx = dc->ctx;
43 }
44 
45 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)
46 {
47 	struct dc_dmub_srv *dc_srv =
48 		kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL);
49 
50 	if (dc_srv == NULL) {
51 		BREAK_TO_DEBUGGER();
52 		return NULL;
53 	}
54 
55 	dc_dmub_srv_construct(dc_srv, dc, dmub);
56 
57 	return dc_srv;
58 }
59 
60 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)
61 {
62 	if (*dmub_srv) {
63 		kfree(*dmub_srv);
64 		*dmub_srv = NULL;
65 	}
66 }
67 
68 void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv,
69 			   union dmub_rb_cmd *cmd)
70 {
71 	struct dmub_srv *dmub = dc_dmub_srv->dmub;
72 	struct dc_context *dc_ctx = dc_dmub_srv->ctx;
73 	enum dmub_status status;
74 
75 	status = dmub_srv_cmd_queue(dmub, cmd);
76 	if (status == DMUB_STATUS_OK)
77 		return;
78 
79 	if (status != DMUB_STATUS_QUEUE_FULL)
80 		goto error;
81 
82 	/* Execute and wait for queue to become empty again. */
83 	dc_dmub_srv_cmd_execute(dc_dmub_srv);
84 	dc_dmub_srv_wait_idle(dc_dmub_srv);
85 
86 	/* Requeue the command. */
87 	status = dmub_srv_cmd_queue(dmub, cmd);
88 	if (status == DMUB_STATUS_OK)
89 		return;
90 
91 error:
92 	DC_ERROR("Error queuing DMUB command: status=%d\n", status);
93 	dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
94 }
95 
96 void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv)
97 {
98 	struct dmub_srv *dmub = dc_dmub_srv->dmub;
99 	struct dc_context *dc_ctx = dc_dmub_srv->ctx;
100 	enum dmub_status status;
101 
102 	status = dmub_srv_cmd_execute(dmub);
103 	if (status != DMUB_STATUS_OK) {
104 		DC_ERROR("Error starting DMUB execution: status=%d\n", status);
105 		dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
106 	}
107 }
108 
109 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
110 {
111 	struct dmub_srv *dmub = dc_dmub_srv->dmub;
112 	struct dc_context *dc_ctx = dc_dmub_srv->ctx;
113 	enum dmub_status status;
114 
115 	status = dmub_srv_wait_for_idle(dmub, 100000);
116 	if (status != DMUB_STATUS_OK) {
117 		DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
118 		dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
119 	}
120 }
121 
122 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv)
123 {
124 	struct dmub_srv *dmub = dmub_srv->dmub;
125 	struct dc_context *dc_ctx = dmub_srv->ctx;
126 	enum dmub_status status = DMUB_STATUS_OK;
127 
128 	status = dmub_srv_clear_inbox0_ack(dmub);
129 	if (status != DMUB_STATUS_OK) {
130 		DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status);
131 		dc_dmub_srv_log_diagnostic_data(dmub_srv);
132 	}
133 }
134 
135 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv)
136 {
137 	struct dmub_srv *dmub = dmub_srv->dmub;
138 	struct dc_context *dc_ctx = dmub_srv->ctx;
139 	enum dmub_status status = DMUB_STATUS_OK;
140 
141 	status = dmub_srv_wait_for_inbox0_ack(dmub, 100000);
142 	if (status != DMUB_STATUS_OK) {
143 		DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n");
144 		dc_dmub_srv_log_diagnostic_data(dmub_srv);
145 	}
146 }
147 
148 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
149 		union dmub_inbox0_data_register data)
150 {
151 	struct dmub_srv *dmub = dmub_srv->dmub;
152 	struct dc_context *dc_ctx = dmub_srv->ctx;
153 	enum dmub_status status = DMUB_STATUS_OK;
154 
155 	status = dmub_srv_send_inbox0_cmd(dmub, data);
156 	if (status != DMUB_STATUS_OK) {
157 		DC_ERROR("Error sending INBOX0 cmd\n");
158 		dc_dmub_srv_log_diagnostic_data(dmub_srv);
159 	}
160 }
161 
162 bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd)
163 {
164 	struct dmub_srv *dmub;
165 	enum dmub_status status;
166 
167 	if (!dc_dmub_srv || !dc_dmub_srv->dmub)
168 		return false;
169 
170 	dmub = dc_dmub_srv->dmub;
171 
172 	status = dmub_srv_cmd_with_reply_data(dmub, cmd);
173 	if (status != DMUB_STATUS_OK) {
174 		DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
175 		return false;
176 	}
177 
178 	return true;
179 }
180 
181 void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
182 {
183 	struct dmub_srv *dmub = dc_dmub_srv->dmub;
184 	struct dc_context *dc_ctx = dc_dmub_srv->ctx;
185 	enum dmub_status status;
186 
187 	for (;;) {
188 		/* Wait up to a second for PHY init. */
189 		status = dmub_srv_wait_for_phy_init(dmub, 1000000);
190 		if (status == DMUB_STATUS_OK)
191 			/* Initialization OK */
192 			break;
193 
194 		DC_ERROR("DMCUB PHY init failed: status=%d\n", status);
195 		ASSERT(0);
196 
197 		if (status != DMUB_STATUS_TIMEOUT)
198 			/*
199 			 * Server likely initialized or we don't have
200 			 * DMCUB HW support - this won't end.
201 			 */
202 			break;
203 
204 		/* Continue spinning so we don't hang the ASIC. */
205 	}
206 }
207 
208 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
209 				    unsigned int stream_mask)
210 {
211 	struct dmub_srv *dmub;
212 	const uint32_t timeout = 30;
213 
214 	if (!dc_dmub_srv || !dc_dmub_srv->dmub)
215 		return false;
216 
217 	dmub = dc_dmub_srv->dmub;
218 
219 	return dmub_srv_send_gpint_command(
220 		       dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
221 		       stream_mask, timeout) == DMUB_STATUS_OK;
222 }
223 
224 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
225 {
226 	struct dmub_srv *dmub;
227 	struct dc_context *dc_ctx;
228 	union dmub_fw_boot_status boot_status;
229 	enum dmub_status status;
230 
231 	if (!dc_dmub_srv || !dc_dmub_srv->dmub)
232 		return false;
233 
234 	dmub = dc_dmub_srv->dmub;
235 	dc_ctx = dc_dmub_srv->ctx;
236 
237 	status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
238 	if (status != DMUB_STATUS_OK) {
239 		DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
240 		return false;
241 	}
242 
243 	return boot_status.bits.restore_required;
244 }
245 
246 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
247 {
248 	struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;
249 	return dmub_srv_get_outbox0_msg(dmub, entry);
250 }
251 
252 void dc_dmub_trace_event_control(struct dc *dc, bool enable)
253 {
254 	dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
255 }
256 
257 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)
258 {
259 	union dmub_rb_cmd cmd = { 0 };
260 
261 	cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
262 	cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE;
263 	cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max;
264 	cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min;
265 	cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
266 
267 	cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
268 
269 	// Send the command to the DMCUB.
270 	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
271 	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
272 	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
273 }
274 
275 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
276 {
277 	union dmub_rb_cmd cmd = { 0 };
278 
279 	cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
280 	cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
281 	cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
282 
283 	cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
284 
285 	// Send the command to the DMCUB.
286 	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
287 	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
288 	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
289 }
290 
291 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)
292 {
293 	uint8_t pipes = 0;
294 	int i = 0;
295 
296 	for (i = 0; i < MAX_PIPES; i++) {
297 		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
298 
299 		if (pipe->stream == stream && pipe->stream_res.tg)
300 			pipes = i;
301 	}
302 	return pipes;
303 }
304 
305 static int dc_dmub_srv_get_timing_generator_offset(struct dc *dc, struct dc_stream_state *stream)
306 {
307 	int  tg_inst = 0;
308 	int i = 0;
309 
310 	for (i = 0; i < MAX_PIPES; i++) {
311 		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
312 
313 		if (pipe->stream == stream && pipe->stream_res.tg) {
314 			tg_inst = pipe->stream_res.tg->inst;
315 			break;
316 		}
317 	}
318 	return tg_inst;
319 }
320 
321 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
322 {
323 	union dmub_rb_cmd cmd = { 0 };
324 	struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data;
325 	int i = 0;
326 	int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it.
327 	uint8_t visual_confirm_enabled;
328 
329 	if (dc == NULL)
330 		return false;
331 
332 	visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;
333 
334 	// Format command.
335 	cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
336 	cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL;
337 	cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate;
338 	cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled;
339 
340 	for (i = 0; context && i < context->stream_count; i++) {
341 		struct dc_stream_state *stream = context->streams[i];
342 		uint8_t min_refresh_in_hz = (stream->timing.min_refresh_in_uhz + 999999) / 1000000;
343 		int  tg_inst = dc_dmub_srv_get_timing_generator_offset(dc, stream);
344 
345 		config_data->pipe_data[tg_inst].pix_clk_100hz = stream->timing.pix_clk_100hz;
346 		config_data->pipe_data[tg_inst].min_refresh_in_hz = min_refresh_in_hz;
347 		config_data->pipe_data[tg_inst].max_ramp_step = ramp_up_num_steps;
348 		config_data->pipe_data[tg_inst].pipes = dc_dmub_srv_get_pipes_for_stream(dc, stream);
349 	}
350 
351 	cmd.fw_assisted_mclk_switch.header.payload_bytes =
352 		sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header);
353 
354 	// Send the command to the DMCUB.
355 	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
356 	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
357 	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
358 
359 	return true;
360 }
361 
362 void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub)
363 {
364 	union dmub_rb_cmd cmd = { 0 };
365 	enum dmub_status status;
366 
367 	if (!dmub) {
368 		return;
369 	}
370 
371 	memset(&cmd, 0, sizeof(cmd));
372 
373 	/* Prepare fw command */
374 	cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS;
375 	cmd.query_feature_caps.header.sub_type = 0;
376 	cmd.query_feature_caps.header.ret_status = 1;
377 	cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);
378 
379 	/* Send command to fw */
380 	status = dmub_srv_cmd_with_reply_data(dmub, &cmd);
381 
382 	ASSERT(status == DMUB_STATUS_OK);
383 
384 	/* If command was processed, copy feature caps to dmub srv */
385 	if (status == DMUB_STATUS_OK &&
386 	    cmd.query_feature_caps.header.ret_status == 0) {
387 		memcpy(&dmub->feature_caps,
388 		       &cmd.query_feature_caps.query_feature_caps_data,
389 		       sizeof(struct dmub_feature_caps));
390 	}
391 }
392 
393 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)
394 {
395 	union dmub_rb_cmd cmd = { 0 };
396 	enum dmub_status status;
397 	unsigned int panel_inst = 0;
398 
399 	dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst);
400 
401 	memset(&cmd, 0, sizeof(cmd));
402 
403 	// Prepare fw command
404 	cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
405 	cmd.visual_confirm_color.header.sub_type = 0;
406 	cmd.visual_confirm_color.header.ret_status = 1;
407 	cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
408 	cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
409 
410 	// Send command to fw
411 	status = dmub_srv_cmd_with_reply_data(dc->ctx->dmub_srv->dmub, &cmd);
412 
413 	ASSERT(status == DMUB_STATUS_OK);
414 
415 	// If command was processed, copy feature caps to dmub srv
416 	if (status == DMUB_STATUS_OK &&
417 		cmd.visual_confirm_color.header.ret_status == 0) {
418 		memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
419 			&cmd.visual_confirm_color.visual_confirm_color_data,
420 			sizeof(struct dmub_visual_confirm_color));
421 	}
422 }
423 
424 #ifdef CONFIG_DRM_AMD_DC_DCN
425 /**
426  * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command
427  *
428  * @dc: [in] current dc state
429  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
430  * @vblank_pipe: [in] pipe_ctx for the DRR pipe
431  * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info
432  *
433  * Populate the DMCUB SubVP command with DRR pipe info. All the information
434  * required for calculating the SubVP + DRR microschedule is populated here.
435  *
436  * High level algorithm:
437  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
438  * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule
439  * 3. Populate the drr_info with the min and max supported vtotal values
440  */
441 static void populate_subvp_cmd_drr_info(struct dc *dc,
442 		struct pipe_ctx *subvp_pipe,
443 		struct pipe_ctx *vblank_pipe,
444 		struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data)
445 {
446 	struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
447 	struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
448 	struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
449 	uint16_t drr_frame_us = 0;
450 	uint16_t min_drr_supported_us = 0;
451 	uint16_t max_drr_supported_us = 0;
452 	uint16_t max_drr_vblank_us = 0;
453 	uint16_t max_drr_mallregion_us = 0;
454 	uint16_t mall_region_us = 0;
455 	uint16_t prefetch_us = 0;
456 	uint16_t subvp_active_us = 0;
457 	uint16_t drr_active_us = 0;
458 	uint16_t min_vtotal_supported = 0;
459 	uint16_t max_vtotal_supported = 0;
460 
461 	pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;
462 	pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
463 	pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
464 
465 	drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000),
466 			(((uint64_t)drr_timing->pix_clk_100hz * 100)));
467 	// P-State allow width and FW delays already included phantom_timing->v_addressable
468 	mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000),
469 			(((uint64_t)phantom_timing->pix_clk_100hz * 100)));
470 	min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
471 	min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us),
472 			(((uint64_t)drr_timing->h_total * 1000000)));
473 
474 	prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000),
475 			(((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
476 	subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000),
477 			(((uint64_t)main_timing->pix_clk_100hz * 100)));
478 	drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000),
479 			(((uint64_t)drr_timing->pix_clk_100hz * 100)));
480 	max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us -
481 			dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us;
482 	max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;
483 	max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
484 	max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us),
485 			(((uint64_t)drr_timing->h_total * 1000000)));
486 
487 	/* When calculating the max vtotal supported for SubVP + DRR cases, add
488 	 * margin due to possible rounding errors (being off by 1 line in the
489 	 * FW calculation can incorrectly push the P-State switch to wait 1 frame
490 	 * longer).
491 	 */
492 	max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
493 
494 	pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
495 	pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
496 	pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
497 }
498 
499 /**
500  * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command
501  *
502  * @dc: [in] current dc state
503  * @context: [in] new dc state
504  * @cmd: [in] DMUB cmd to be populated with SubVP info
505  * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe
506  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
507  *
508  * Populate the DMCUB SubVP command with VBLANK pipe info. All the information
509  * required to calculate the microschedule for SubVP + VBLANK case is stored in
510  * the pipe_data (subvp_data and vblank_data).  Also check if the VBLANK pipe
511  * is a DRR display -- if it is make a call to populate drr_info.
512  */
513 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,
514 		struct dc_state *context,
515 		union dmub_rb_cmd *cmd,
516 		struct pipe_ctx *vblank_pipe,
517 		uint8_t cmd_pipe_index)
518 {
519 	uint32_t i;
520 	struct pipe_ctx *pipe = NULL;
521 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
522 			&cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
523 
524 	// Find the SubVP pipe
525 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
526 		pipe = &context->res_ctx.pipe_ctx[i];
527 
528 		// We check for master pipe, but it shouldn't matter since we only need
529 		// the pipe for timing info (stream should be same for any pipe splits)
530 		if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
531 			continue;
532 
533 		// Find the SubVP pipe
534 		if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
535 			break;
536 	}
537 
538 	pipe_data->mode = VBLANK;
539 	pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
540 	pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
541 							vblank_pipe->stream->timing.v_front_porch;
542 	pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
543 	pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;
544 	pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;
545 	pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;
546 	pipe_data->pipe_config.vblank_data.vblank_end =
547 			vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
548 
549 	if (vblank_pipe->stream->ignore_msa_timing_param)
550 		populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data);
551 }
552 
553 /**
554  * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case
555  *
556  * @dc: [in] current dc state
557  * @context: [in] new dc state
558  * @cmd: [in] DMUB cmd to be populated with SubVP info
559  * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2)
560  *
561  * For SubVP + SubVP, we use a single vertical interrupt to start the
562  * microschedule for both SubVP pipes. In order for this to work correctly, the
563  * MALL REGION of both SubVP pipes must start at the same time. This function
564  * lengthens the prefetch end to mall start delay of the SubVP pipe that has
565  * the shorter prefetch so that both MALL REGION's will start at the same time.
566  */
567 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
568 		struct dc_state *context,
569 		union dmub_rb_cmd *cmd,
570 		struct pipe_ctx *subvp_pipes[])
571 {
572 	uint32_t subvp0_prefetch_us = 0;
573 	uint32_t subvp1_prefetch_us = 0;
574 	uint32_t prefetch_delta_us = 0;
575 	struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing;
576 	struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing;
577 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
578 
579 	subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
580 			(uint64_t)phantom_timing0->h_total * 1000000),
581 			(((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
582 	subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
583 			(uint64_t)phantom_timing1->h_total * 1000000),
584 			(((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
585 
586 	// Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
587 	// should increase it's prefetch time to match the other
588 	if (subvp0_prefetch_us > subvp1_prefetch_us) {
589 		pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
590 		prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
591 		pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
592 				div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
593 					((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
594 					((uint64_t)phantom_timing1->h_total * 1000000));
595 
596 	} else if (subvp1_prefetch_us >  subvp0_prefetch_us) {
597 		pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
598 		prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
599 		pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
600 				div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
601 					((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
602 					((uint64_t)phantom_timing0->h_total * 1000000));
603 	}
604 }
605 
606 /**
607  * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command
608  *
609  * @dc: [in] current dc state
610  * @context: [in] new dc state
611  * @cmd: [in] DMUB cmd to be populated with SubVP info
612  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
613  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
614  *
615  * Populate the DMCUB SubVP command with SubVP pipe info. All the information
616  * required to calculate the microschedule for the SubVP pipe is stored in the
617  * pipe_data of the DMCUB SubVP command.
618  */
619 static void populate_subvp_cmd_pipe_info(struct dc *dc,
620 		struct dc_state *context,
621 		union dmub_rb_cmd *cmd,
622 		struct pipe_ctx *subvp_pipe,
623 		uint8_t cmd_pipe_index)
624 {
625 	uint32_t j;
626 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
627 			&cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
628 	struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
629 	struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
630 	uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;
631 
632 	pipe_data->mode = SUBVP;
633 	pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
634 	pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;
635 	pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;
636 	pipe_data->pipe_config.subvp_data.main_vblank_start =
637 			main_timing->v_total - main_timing->v_front_porch;
638 	pipe_data->pipe_config.subvp_data.main_vblank_end =
639 			main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
640 	pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
641 	pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->pipe_idx;
642 	pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param;
643 
644 	/* Calculate the scaling factor from the src and dst height.
645 	 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.
646 	 * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor"
647 	 *
648 	 * Make sure to combine stream and plane scaling together.
649 	 */
650 	reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height,
651 			&out_num_stream, &out_den_stream);
652 	reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,
653 			&out_num_plane, &out_den_plane);
654 	reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den);
655 	pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
656 	pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
657 
658 	// Prefetch lines is equal to VACTIVE + BP + VSYNC
659 	pipe_data->pipe_config.subvp_data.prefetch_lines =
660 			phantom_timing->v_total - phantom_timing->v_front_porch;
661 
662 	// Round up
663 	pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
664 			div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
665 					((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
666 	pipe_data->pipe_config.subvp_data.processing_delay_lines =
667 			div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
668 					((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
669 
670 	if (subvp_pipe->bottom_pipe) {
671 		pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;
672 	} else if (subvp_pipe->next_odm_pipe) {
673 		pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
674 	} else {
675 		pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0;
676 	}
677 
678 	// Find phantom pipe index based on phantom stream
679 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
680 		struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
681 
682 		if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) {
683 			pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->pipe_idx;
684 			if (phantom_pipe->bottom_pipe) {
685 				pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->pipe_idx;
686 			} else if (phantom_pipe->next_odm_pipe) {
687 				pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->pipe_idx;
688 			} else {
689 				pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0;
690 			}
691 			break;
692 		}
693 	}
694 }
695 
696 /**
697  * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command
698  *
699  * @dc: [in] current dc state
700  * @context: [in] new dc state
701  * @enable: [in] if true enables the pipes population
702  *
703  * This function loops through each pipe and populates the DMUB SubVP CMD info
704  * based on the pipe (e.g. SubVP, VBLANK).
705  */
706 void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
707 		struct dc_state *context,
708 		bool enable)
709 {
710 	uint8_t cmd_pipe_index = 0;
711 	uint32_t i, pipe_idx;
712 	uint8_t subvp_count = 0;
713 	union dmub_rb_cmd cmd;
714 	struct pipe_ctx *subvp_pipes[2];
715 	uint32_t wm_val_refclk = 0;
716 
717 	memset(&cmd, 0, sizeof(cmd));
718 	// FW command for SUBVP
719 	cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
720 	cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD;
721 	cmd.fw_assisted_mclk_switch_v2.header.payload_bytes =
722 			sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header);
723 
724 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
725 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
726 
727 		if (!pipe->stream)
728 			continue;
729 
730 		/* For SubVP pipe count, only count the top most (ODM / MPC) pipe
731 		 */
732 		if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe &&
733 				pipe->stream->mall_stream_config.type == SUBVP_MAIN)
734 			subvp_pipes[subvp_count++] = pipe;
735 	}
736 
737 	if (enable) {
738 		// For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd
739 		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
740 			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
741 
742 			if (!pipe->stream)
743 				continue;
744 
745 			/* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe.
746 			 * Any ODM or MPC splits being used in SubVP will be handled internally in
747 			 * populate_subvp_cmd_pipe_info
748 			 */
749 			if (pipe->plane_state && pipe->stream->mall_stream_config.paired_stream &&
750 					!pipe->top_pipe && !pipe->prev_odm_pipe &&
751 					pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
752 				populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
753 			} else if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_NONE) {
754 				// Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where
755 				// we run through DML without calculating "natural" P-state support
756 				populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
757 
758 			}
759 			pipe_idx++;
760 		}
761 		if (subvp_count == 2) {
762 			update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);
763 		}
764 		cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
765 		cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;
766 
767 		// Store the original watermark value for this SubVP config so we can lower it when the
768 		// MCLK switch starts
769 		wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
770 				(dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
771 
772 		cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
773 	}
774 	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
775 	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
776 	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
777 }
778 #endif
779 
780 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
781 {
782 	if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
783 		return false;
784 	return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data);
785 }
786 
787 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
788 {
789 	struct dmub_diagnostic_data diag_data = {0};
790 
791 	if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
792 		DC_LOG_ERROR("%s: invalid parameters.", __func__);
793 		return;
794 	}
795 
796 	if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) {
797 		DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);
798 		return;
799 	}
800 
801 	DC_LOG_DEBUG(
802 		"DMCUB STATE\n"
803 		"    dmcub_version      : %08x\n"
804 		"    scratch  [0]       : %08x\n"
805 		"    scratch  [1]       : %08x\n"
806 		"    scratch  [2]       : %08x\n"
807 		"    scratch  [3]       : %08x\n"
808 		"    scratch  [4]       : %08x\n"
809 		"    scratch  [5]       : %08x\n"
810 		"    scratch  [6]       : %08x\n"
811 		"    scratch  [7]       : %08x\n"
812 		"    scratch  [8]       : %08x\n"
813 		"    scratch  [9]       : %08x\n"
814 		"    scratch [10]       : %08x\n"
815 		"    scratch [11]       : %08x\n"
816 		"    scratch [12]       : %08x\n"
817 		"    scratch [13]       : %08x\n"
818 		"    scratch [14]       : %08x\n"
819 		"    scratch [15]       : %08x\n"
820 		"    pc                 : %08x\n"
821 		"    unk_fault_addr     : %08x\n"
822 		"    inst_fault_addr    : %08x\n"
823 		"    data_fault_addr    : %08x\n"
824 		"    inbox1_rptr        : %08x\n"
825 		"    inbox1_wptr        : %08x\n"
826 		"    inbox1_size        : %08x\n"
827 		"    inbox0_rptr        : %08x\n"
828 		"    inbox0_wptr        : %08x\n"
829 		"    inbox0_size        : %08x\n"
830 		"    is_enabled         : %d\n"
831 		"    is_soft_reset      : %d\n"
832 		"    is_secure_reset    : %d\n"
833 		"    is_traceport_en    : %d\n"
834 		"    is_cw0_en          : %d\n"
835 		"    is_cw6_en          : %d\n",
836 		diag_data.dmcub_version,
837 		diag_data.scratch[0],
838 		diag_data.scratch[1],
839 		diag_data.scratch[2],
840 		diag_data.scratch[3],
841 		diag_data.scratch[4],
842 		diag_data.scratch[5],
843 		diag_data.scratch[6],
844 		diag_data.scratch[7],
845 		diag_data.scratch[8],
846 		diag_data.scratch[9],
847 		diag_data.scratch[10],
848 		diag_data.scratch[11],
849 		diag_data.scratch[12],
850 		diag_data.scratch[13],
851 		diag_data.scratch[14],
852 		diag_data.scratch[15],
853 		diag_data.pc,
854 		diag_data.undefined_address_fault_addr,
855 		diag_data.inst_fetch_fault_addr,
856 		diag_data.data_write_fault_addr,
857 		diag_data.inbox1_rptr,
858 		diag_data.inbox1_wptr,
859 		diag_data.inbox1_size,
860 		diag_data.inbox0_rptr,
861 		diag_data.inbox0_wptr,
862 		diag_data.inbox0_size,
863 		diag_data.is_dmcub_enabled,
864 		diag_data.is_dmcub_soft_reset,
865 		diag_data.is_dmcub_secure_reset,
866 		diag_data.is_traceport_en,
867 		diag_data.is_cw0_enabled,
868 		diag_data.is_cw6_enabled);
869 }
870 
871 static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
872 {
873 	struct pipe_ctx *test_pipe, *split_pipe;
874 	const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data;
875 	struct rect r1 = scl_data->recout, r2, r2_half;
876 	int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b;
877 	int cur_layer = pipe_ctx->plane_state->layer_index;
878 
879 	/**
880 	 * Disable the cursor if there's another pipe above this with a
881 	 * plane that contains this pipe's viewport to prevent double cursor
882 	 * and incorrect scaling artifacts.
883 	 */
884 	for (test_pipe = pipe_ctx->top_pipe; test_pipe;
885 	     test_pipe = test_pipe->top_pipe) {
886 		// Skip invisible layer and pipe-split plane on same layer
887 		if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer)
888 			continue;
889 
890 		r2 = test_pipe->plane_res.scl_data.recout;
891 		r2_r = r2.x + r2.width;
892 		r2_b = r2.y + r2.height;
893 		split_pipe = test_pipe;
894 
895 		/**
896 		 * There is another half plane on same layer because of
897 		 * pipe-split, merge together per same height.
898 		 */
899 		for (split_pipe = pipe_ctx->top_pipe; split_pipe;
900 		     split_pipe = split_pipe->top_pipe)
901 			if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {
902 				r2_half = split_pipe->plane_res.scl_data.recout;
903 				r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x;
904 				r2.width = r2.width + r2_half.width;
905 				r2_r = r2.x + r2.width;
906 				break;
907 			}
908 
909 		if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b)
910 			return true;
911 	}
912 
913 	return false;
914 }
915 
916 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)
917 {
918 	if (pipe_ctx->plane_state != NULL) {
919 		if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
920 			return false;
921 
922 		if (dc_can_pipe_disable_cursor(pipe_ctx))
923 			return false;
924 	}
925 
926 	if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
927 		pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&
928 		pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)
929 		return true;
930 
931 	return false;
932 }
933 
934 static void dc_build_cursor_update_payload0(
935 		struct pipe_ctx *pipe_ctx, uint8_t p_idx,
936 		struct dmub_cmd_update_cursor_payload0 *payload)
937 {
938 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
939 	unsigned int panel_inst = 0;
940 
941 	if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
942 		pipe_ctx->stream->link, &panel_inst))
943 		return;
944 
945 	/* Payload: Cursor Rect is built from position & attribute
946 	 * x & y are obtained from postion
947 	 */
948 	payload->cursor_rect.x = hubp->cur_rect.x;
949 	payload->cursor_rect.y = hubp->cur_rect.y;
950 	/* w & h are obtained from attribute */
951 	payload->cursor_rect.width  = hubp->cur_rect.w;
952 	payload->cursor_rect.height = hubp->cur_rect.h;
953 
954 	payload->enable      = hubp->pos.cur_ctl.bits.cur_enable;
955 	payload->pipe_idx    = p_idx;
956 	payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
957 	payload->panel_inst  = panel_inst;
958 }
959 
960 static void dc_send_cmd_to_dmu(struct dc_dmub_srv *dmub_srv,
961 		union dmub_rb_cmd *cmd)
962 {
963 	dc_dmub_srv_cmd_queue(dmub_srv, cmd);
964 	dc_dmub_srv_cmd_execute(dmub_srv);
965 	dc_dmub_srv_wait_idle(dmub_srv);
966 }
967 
968 static void dc_build_cursor_position_update_payload0(
969 		struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx,
970 		const struct hubp *hubp, const struct dpp *dpp)
971 {
972 	/* Hubp */
973 	pl->position_cfg.pHubp.cur_ctl.raw  = hubp->pos.cur_ctl.raw;
974 	pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;
975 	pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;
976 	pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;
977 
978 	/* dpp */
979 	pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;
980 	pl->position_cfg.pipe_idx = p_idx;
981 }
982 
983 static void dc_build_cursor_attribute_update_payload1(
984 		struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx,
985 		const struct hubp *hubp, const struct dpp *dpp)
986 {
987 	/* Hubp */
988 	pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;
989 	pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;
990 	pl_A->aHubp.cur_ctl.raw  = hubp->att.cur_ctl.raw;
991 	pl_A->aHubp.size.raw     = hubp->att.size.raw;
992 	pl_A->aHubp.settings.raw = hubp->att.settings.raw;
993 
994 	/* dpp */
995 	pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;
996 }
997 
998 /**
999  * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command
1000  *
1001  * @pCtx: [in] pipe context
1002  * @pipe_idx: [in] pipe index
1003  *
1004  * This function would store the cursor related information and pass it into
1005  * dmub
1006  */
1007 void dc_send_update_cursor_info_to_dmu(
1008 		struct pipe_ctx *pCtx, uint8_t pipe_idx)
1009 {
1010 	union dmub_rb_cmd cmd = { 0 };
1011 	union dmub_cmd_update_cursor_info_data *update_cursor_info =
1012 					&cmd.update_cursor_info.update_cursor_info_data;
1013 
1014 	if (!dc_dmub_should_update_cursor_data(pCtx))
1015 		return;
1016 	/*
1017 	 * Since we use multi_cmd_pending for dmub command, the 2nd command is
1018 	 * only assigned to store cursor attributes info.
1019 	 * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other
1020 	 * is to store cursor position info.
1021 	 *
1022 	 * Command heaer type must be the same type if using  multi_cmd_pending.
1023 	 * Besides, while process 2nd command in DMU, the sub type is useless.
1024 	 * So it's meanless to pass the sub type header with different type.
1025 	 */
1026 
1027 	{
1028 		/* Build Payload#0 Header */
1029 		cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1030 		cmd.update_cursor_info.header.payload_bytes =
1031 				sizeof(cmd.update_cursor_info.update_cursor_info_data);
1032 		cmd.update_cursor_info.header.multi_cmd_pending = 1; /* To combine multi dmu cmd, 1st cmd */
1033 
1034 		/* Prepare Payload */
1035 		dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info->payload0);
1036 
1037 		dc_build_cursor_position_update_payload0(&update_cursor_info->payload0, pipe_idx,
1038 				pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1039 		/* Send update_curosr_info to queue */
1040 		dc_dmub_srv_cmd_queue(pCtx->stream->ctx->dmub_srv, &cmd);
1041 	}
1042 	{
1043 		/* Build Payload#1 Header */
1044 		memset(update_cursor_info, 0, sizeof(union dmub_cmd_update_cursor_info_data));
1045 		cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1046 		cmd.update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg);
1047 		cmd.update_cursor_info.header.multi_cmd_pending = 0; /* Indicate it's the last command. */
1048 
1049 		dc_build_cursor_attribute_update_payload1(
1050 				&cmd.update_cursor_info.update_cursor_info_data.payload1.attribute_cfg,
1051 				pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1052 
1053 		/* Combine 2nd cmds update_curosr_info to DMU */
1054 		dc_send_cmd_to_dmu(pCtx->stream->ctx->dmub_srv, &cmd);
1055 	}
1056 }
1057