1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc.h" 27 #include "dc_dmub_srv.h" 28 #include "../dmub/dmub_srv.h" 29 #include "dm_helpers.h" 30 #include "dc_hw_types.h" 31 #include "core_types.h" 32 #include "../basics/conversion.h" 33 #include "cursor_reg_cache.h" 34 35 #define CTX dc_dmub_srv->ctx 36 #define DC_LOGGER CTX->logger 37 38 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, 39 struct dmub_srv *dmub) 40 { 41 dc_srv->dmub = dmub; 42 dc_srv->ctx = dc->ctx; 43 } 44 45 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) 46 { 47 struct dc_dmub_srv *dc_srv = 48 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL); 49 50 if (dc_srv == NULL) { 51 BREAK_TO_DEBUGGER(); 52 return NULL; 53 } 54 55 dc_dmub_srv_construct(dc_srv, dc, dmub); 56 57 return dc_srv; 58 } 59 60 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv) 61 { 62 if (*dmub_srv) { 63 kfree(*dmub_srv); 64 *dmub_srv = NULL; 65 } 66 } 67 68 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) 69 { 70 struct dmub_srv *dmub = dc_dmub_srv->dmub; 71 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 72 enum dmub_status status; 73 74 status = dmub_srv_wait_for_idle(dmub, 100000); 75 if (status != DMUB_STATUS_OK) { 76 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); 77 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 78 } 79 } 80 81 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv) 82 { 83 struct dmub_srv *dmub = dmub_srv->dmub; 84 struct dc_context *dc_ctx = dmub_srv->ctx; 85 enum dmub_status status = DMUB_STATUS_OK; 86 87 status = dmub_srv_clear_inbox0_ack(dmub); 88 if (status != DMUB_STATUS_OK) { 89 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status); 90 dc_dmub_srv_log_diagnostic_data(dmub_srv); 91 } 92 } 93 94 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv) 95 { 96 struct dmub_srv *dmub = dmub_srv->dmub; 97 struct dc_context *dc_ctx = dmub_srv->ctx; 98 enum dmub_status status = DMUB_STATUS_OK; 99 100 status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); 101 if (status != DMUB_STATUS_OK) { 102 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n"); 103 dc_dmub_srv_log_diagnostic_data(dmub_srv); 104 } 105 } 106 107 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, 108 union dmub_inbox0_data_register data) 109 { 110 struct dmub_srv *dmub = dmub_srv->dmub; 111 struct dc_context *dc_ctx = dmub_srv->ctx; 112 enum dmub_status status = DMUB_STATUS_OK; 113 114 status = dmub_srv_send_inbox0_cmd(dmub, data); 115 if (status != DMUB_STATUS_OK) { 116 DC_ERROR("Error sending INBOX0 cmd\n"); 117 dc_dmub_srv_log_diagnostic_data(dmub_srv); 118 } 119 } 120 121 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 122 { 123 return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type); 124 } 125 126 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type) 127 { 128 struct dc_context *dc_ctx; 129 struct dmub_srv *dmub; 130 enum dmub_status status; 131 int i; 132 133 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 134 return false; 135 136 dc_ctx = dc_dmub_srv->ctx; 137 dmub = dc_dmub_srv->dmub; 138 139 for (i = 0 ; i < count; i++) { 140 // Queue command 141 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 142 143 if (status == DMUB_STATUS_QUEUE_FULL) { 144 /* Execute and wait for queue to become empty again. */ 145 dmub_srv_cmd_execute(dmub); 146 dmub_srv_wait_for_idle(dmub, 100000); 147 148 /* Requeue the command. */ 149 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 150 } 151 152 if (status != DMUB_STATUS_OK) { 153 DC_ERROR("Error queueing DMUB command: status=%d\n", status); 154 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 155 return false; 156 } 157 } 158 159 status = dmub_srv_cmd_execute(dmub); 160 if (status != DMUB_STATUS_OK) { 161 DC_ERROR("Error starting DMUB execution: status=%d\n", status); 162 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 163 return false; 164 } 165 166 // Wait for DMUB to process command 167 if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) { 168 status = dmub_srv_wait_for_idle(dmub, 100000); 169 170 if (status != DMUB_STATUS_OK) { 171 DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 172 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 173 return false; 174 } 175 176 // Copy data back from ring buffer into command 177 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) 178 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list); 179 } 180 181 return true; 182 } 183 184 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv) 185 { 186 struct dmub_srv *dmub; 187 struct dc_context *dc_ctx; 188 union dmub_fw_boot_status boot_status; 189 enum dmub_status status; 190 191 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 192 return false; 193 194 dmub = dc_dmub_srv->dmub; 195 dc_ctx = dc_dmub_srv->ctx; 196 197 status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 198 if (status != DMUB_STATUS_OK) { 199 DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 200 return false; 201 } 202 203 return boot_status.bits.optimized_init_done; 204 } 205 206 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 207 unsigned int stream_mask) 208 { 209 struct dmub_srv *dmub; 210 const uint32_t timeout = 30; 211 212 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 213 return false; 214 215 dmub = dc_dmub_srv->dmub; 216 217 return dmub_srv_send_gpint_command( 218 dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, 219 stream_mask, timeout) == DMUB_STATUS_OK; 220 } 221 222 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) 223 { 224 struct dmub_srv *dmub; 225 struct dc_context *dc_ctx; 226 union dmub_fw_boot_status boot_status; 227 enum dmub_status status; 228 229 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 230 return false; 231 232 dmub = dc_dmub_srv->dmub; 233 dc_ctx = dc_dmub_srv->ctx; 234 235 status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 236 if (status != DMUB_STATUS_OK) { 237 DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 238 return false; 239 } 240 241 return boot_status.bits.restore_required; 242 } 243 244 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) 245 { 246 struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; 247 return dmub_srv_get_outbox0_msg(dmub, entry); 248 } 249 250 void dc_dmub_trace_event_control(struct dc *dc, bool enable) 251 { 252 dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); 253 } 254 255 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) 256 { 257 union dmub_rb_cmd cmd = { 0 }; 258 259 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 260 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE; 261 cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 262 cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 263 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 264 265 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 266 267 // Send the command to the DMCUB. 268 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 269 } 270 271 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) 272 { 273 union dmub_rb_cmd cmd = { 0 }; 274 275 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 276 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER; 277 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 278 279 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 280 281 // Send the command to the DMCUB. 282 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 283 } 284 285 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) 286 { 287 uint8_t pipes = 0; 288 int i = 0; 289 290 for (i = 0; i < MAX_PIPES; i++) { 291 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 292 293 if (pipe->stream == stream && pipe->stream_res.tg) 294 pipes = i; 295 } 296 return pipes; 297 } 298 299 static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context, 300 struct pipe_ctx *head_pipe, 301 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data) 302 { 303 int j; 304 int pipe_idx = 0; 305 306 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; 307 for (j = 0; j < dc->res_pool->pipe_count; j++) { 308 struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j]; 309 310 if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) { 311 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; 312 } 313 } 314 fams_pipe_data->pipe_count = pipe_idx; 315 } 316 317 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) 318 { 319 union dmub_rb_cmd cmd = { 0 }; 320 struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; 321 int i = 0, k = 0; 322 int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. 323 uint8_t visual_confirm_enabled; 324 int pipe_idx = 0; 325 326 if (dc == NULL) 327 return false; 328 329 visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; 330 331 // Format command. 332 cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 333 cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL; 334 cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate; 335 cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; 336 337 if (should_manage_pstate) { 338 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 339 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 340 341 if (!pipe->stream) 342 continue; 343 344 /* If FAMS is being used to support P-State and there is a stream 345 * that does not use FAMS, we are in an FPO + VActive scenario. 346 * Assign vactive stretch margin in this case. 347 */ 348 if (!pipe->stream->fpo_in_use) { 349 cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us; 350 break; 351 } 352 pipe_idx++; 353 } 354 } 355 356 for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { 357 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 358 359 if (!pipe->top_pipe && !pipe->prev_odm_pipe && pipe->stream && pipe->stream->fpo_in_use) { 360 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 361 uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000; 362 363 config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz; 364 config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz; 365 config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps; 366 config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream); 367 dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]); 368 k++; 369 } 370 } 371 cmd.fw_assisted_mclk_switch.header.payload_bytes = 372 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header); 373 374 // Send the command to the DMCUB. 375 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 376 377 return true; 378 } 379 380 void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv) 381 { 382 union dmub_rb_cmd cmd = { 0 }; 383 384 if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation) 385 return; 386 387 memset(&cmd, 0, sizeof(cmd)); 388 389 /* Prepare fw command */ 390 cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; 391 cmd.query_feature_caps.header.sub_type = 0; 392 cmd.query_feature_caps.header.ret_status = 1; 393 cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); 394 395 /* If command was processed, copy feature caps to dmub srv */ 396 if (dm_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 397 cmd.query_feature_caps.header.ret_status == 0) { 398 memcpy(&dc_dmub_srv->dmub->feature_caps, 399 &cmd.query_feature_caps.query_feature_caps_data, 400 sizeof(struct dmub_feature_caps)); 401 } 402 } 403 404 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx) 405 { 406 union dmub_rb_cmd cmd = { 0 }; 407 unsigned int panel_inst = 0; 408 409 dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst); 410 411 memset(&cmd, 0, sizeof(cmd)); 412 413 // Prepare fw command 414 cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR; 415 cmd.visual_confirm_color.header.sub_type = 0; 416 cmd.visual_confirm_color.header.ret_status = 1; 417 cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data); 418 cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst; 419 420 // If command was processed, copy feature caps to dmub srv 421 if (dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 422 cmd.visual_confirm_color.header.ret_status == 0) { 423 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color, 424 &cmd.visual_confirm_color.visual_confirm_color_data, 425 sizeof(struct dmub_visual_confirm_color)); 426 } 427 } 428 429 /** 430 * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command 431 * 432 * @dc: [in] current dc state 433 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 434 * @vblank_pipe: [in] pipe_ctx for the DRR pipe 435 * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info 436 * 437 * Populate the DMCUB SubVP command with DRR pipe info. All the information 438 * required for calculating the SubVP + DRR microschedule is populated here. 439 * 440 * High level algorithm: 441 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 442 * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule 443 * 3. Populate the drr_info with the min and max supported vtotal values 444 */ 445 static void populate_subvp_cmd_drr_info(struct dc *dc, 446 struct pipe_ctx *subvp_pipe, 447 struct pipe_ctx *vblank_pipe, 448 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data) 449 { 450 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 451 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 452 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 453 uint16_t drr_frame_us = 0; 454 uint16_t min_drr_supported_us = 0; 455 uint16_t max_drr_supported_us = 0; 456 uint16_t max_drr_vblank_us = 0; 457 uint16_t max_drr_mallregion_us = 0; 458 uint16_t mall_region_us = 0; 459 uint16_t prefetch_us = 0; 460 uint16_t subvp_active_us = 0; 461 uint16_t drr_active_us = 0; 462 uint16_t min_vtotal_supported = 0; 463 uint16_t max_vtotal_supported = 0; 464 465 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; 466 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping 467 pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now 468 469 drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000), 470 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 471 // P-State allow width and FW delays already included phantom_timing->v_addressable 472 mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000), 473 (((uint64_t)phantom_timing->pix_clk_100hz * 100))); 474 min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 475 min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us), 476 (((uint64_t)drr_timing->h_total * 1000000))); 477 478 prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000), 479 (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 480 subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000), 481 (((uint64_t)main_timing->pix_clk_100hz * 100))); 482 drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000), 483 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 484 max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - 485 dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us; 486 max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us; 487 max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; 488 max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us), 489 (((uint64_t)drr_timing->h_total * 1000000))); 490 491 /* When calculating the max vtotal supported for SubVP + DRR cases, add 492 * margin due to possible rounding errors (being off by 1 line in the 493 * FW calculation can incorrectly push the P-State switch to wait 1 frame 494 * longer). 495 */ 496 max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us; 497 498 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; 499 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; 500 pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us; 501 } 502 503 /** 504 * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command 505 * 506 * @dc: [in] current dc state 507 * @context: [in] new dc state 508 * @cmd: [in] DMUB cmd to be populated with SubVP info 509 * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe 510 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 511 * 512 * Populate the DMCUB SubVP command with VBLANK pipe info. All the information 513 * required to calculate the microschedule for SubVP + VBLANK case is stored in 514 * the pipe_data (subvp_data and vblank_data). Also check if the VBLANK pipe 515 * is a DRR display -- if it is make a call to populate drr_info. 516 */ 517 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, 518 struct dc_state *context, 519 union dmub_rb_cmd *cmd, 520 struct pipe_ctx *vblank_pipe, 521 uint8_t cmd_pipe_index) 522 { 523 uint32_t i; 524 struct pipe_ctx *pipe = NULL; 525 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 526 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 527 528 // Find the SubVP pipe 529 for (i = 0; i < dc->res_pool->pipe_count; i++) { 530 pipe = &context->res_ctx.pipe_ctx[i]; 531 532 // We check for master pipe, but it shouldn't matter since we only need 533 // the pipe for timing info (stream should be same for any pipe splits) 534 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 535 continue; 536 537 // Find the SubVP pipe 538 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 539 break; 540 } 541 542 pipe_data->mode = VBLANK; 543 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; 544 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - 545 vblank_pipe->stream->timing.v_front_porch; 546 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; 547 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; 548 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; 549 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; 550 pipe_data->pipe_config.vblank_data.vblank_end = 551 vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; 552 553 if (vblank_pipe->stream->ignore_msa_timing_param) 554 populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data); 555 } 556 557 /** 558 * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case 559 * 560 * @dc: [in] current dc state 561 * @context: [in] new dc state 562 * @cmd: [in] DMUB cmd to be populated with SubVP info 563 * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2) 564 * 565 * For SubVP + SubVP, we use a single vertical interrupt to start the 566 * microschedule for both SubVP pipes. In order for this to work correctly, the 567 * MALL REGION of both SubVP pipes must start at the same time. This function 568 * lengthens the prefetch end to mall start delay of the SubVP pipe that has 569 * the shorter prefetch so that both MALL REGION's will start at the same time. 570 */ 571 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, 572 struct dc_state *context, 573 union dmub_rb_cmd *cmd, 574 struct pipe_ctx *subvp_pipes[]) 575 { 576 uint32_t subvp0_prefetch_us = 0; 577 uint32_t subvp1_prefetch_us = 0; 578 uint32_t prefetch_delta_us = 0; 579 struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing; 580 struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing; 581 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL; 582 583 subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * 584 (uint64_t)phantom_timing0->h_total * 1000000), 585 (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 586 subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * 587 (uint64_t)phantom_timing1->h_total * 1000000), 588 (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 589 590 // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) 591 // should increase it's prefetch time to match the other 592 if (subvp0_prefetch_us > subvp1_prefetch_us) { 593 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; 594 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; 595 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 596 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 597 ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), 598 ((uint64_t)phantom_timing1->h_total * 1000000)); 599 600 } else if (subvp1_prefetch_us > subvp0_prefetch_us) { 601 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; 602 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; 603 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 604 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 605 ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), 606 ((uint64_t)phantom_timing0->h_total * 1000000)); 607 } 608 } 609 610 /** 611 * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command 612 * 613 * @dc: [in] current dc state 614 * @context: [in] new dc state 615 * @cmd: [in] DMUB cmd to be populated with SubVP info 616 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 617 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 618 * 619 * Populate the DMCUB SubVP command with SubVP pipe info. All the information 620 * required to calculate the microschedule for the SubVP pipe is stored in the 621 * pipe_data of the DMCUB SubVP command. 622 */ 623 static void populate_subvp_cmd_pipe_info(struct dc *dc, 624 struct dc_state *context, 625 union dmub_rb_cmd *cmd, 626 struct pipe_ctx *subvp_pipe, 627 uint8_t cmd_pipe_index) 628 { 629 uint32_t j; 630 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 631 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 632 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 633 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 634 uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den; 635 636 pipe_data->mode = SUBVP; 637 pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; 638 pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; 639 pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; 640 pipe_data->pipe_config.subvp_data.main_vblank_start = 641 main_timing->v_total - main_timing->v_front_porch; 642 pipe_data->pipe_config.subvp_data.main_vblank_end = 643 main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; 644 pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; 645 pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst; 646 pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param; 647 648 /* Calculate the scaling factor from the src and dst height. 649 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2. 650 * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor" 651 * 652 * Make sure to combine stream and plane scaling together. 653 */ 654 reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height, 655 &out_num_stream, &out_den_stream); 656 reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height, 657 &out_num_plane, &out_den_plane); 658 reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den); 659 pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num; 660 pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den; 661 662 // Prefetch lines is equal to VACTIVE + BP + VSYNC 663 pipe_data->pipe_config.subvp_data.prefetch_lines = 664 phantom_timing->v_total - phantom_timing->v_front_porch; 665 666 // Round up 667 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 668 div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 669 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 670 pipe_data->pipe_config.subvp_data.processing_delay_lines = 671 div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 672 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 673 674 if (subvp_pipe->bottom_pipe) { 675 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; 676 } else if (subvp_pipe->next_odm_pipe) { 677 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; 678 } else { 679 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0; 680 } 681 682 // Find phantom pipe index based on phantom stream 683 for (j = 0; j < dc->res_pool->pipe_count; j++) { 684 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; 685 686 if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) { 687 pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst; 688 if (phantom_pipe->bottom_pipe) { 689 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; 690 } else if (phantom_pipe->next_odm_pipe) { 691 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; 692 } else { 693 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0; 694 } 695 break; 696 } 697 } 698 } 699 700 /** 701 * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command 702 * 703 * @dc: [in] current dc state 704 * @context: [in] new dc state 705 * @enable: [in] if true enables the pipes population 706 * 707 * This function loops through each pipe and populates the DMUB SubVP CMD info 708 * based on the pipe (e.g. SubVP, VBLANK). 709 */ 710 void dc_dmub_setup_subvp_dmub_command(struct dc *dc, 711 struct dc_state *context, 712 bool enable) 713 { 714 uint8_t cmd_pipe_index = 0; 715 uint32_t i, pipe_idx; 716 uint8_t subvp_count = 0; 717 union dmub_rb_cmd cmd; 718 struct pipe_ctx *subvp_pipes[2]; 719 uint32_t wm_val_refclk = 0; 720 721 memset(&cmd, 0, sizeof(cmd)); 722 // FW command for SUBVP 723 cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 724 cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD; 725 cmd.fw_assisted_mclk_switch_v2.header.payload_bytes = 726 sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header); 727 728 for (i = 0; i < dc->res_pool->pipe_count; i++) { 729 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 730 731 if (!pipe->stream) 732 continue; 733 734 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe 735 */ 736 if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && 737 pipe->stream->mall_stream_config.type == SUBVP_MAIN) 738 subvp_pipes[subvp_count++] = pipe; 739 } 740 741 if (enable) { 742 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd 743 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 744 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 745 746 if (!pipe->stream) 747 continue; 748 749 /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe. 750 * Any ODM or MPC splits being used in SubVP will be handled internally in 751 * populate_subvp_cmd_pipe_info 752 */ 753 if (pipe->plane_state && pipe->stream->mall_stream_config.paired_stream && 754 !pipe->top_pipe && !pipe->prev_odm_pipe && 755 pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 756 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 757 } else if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_NONE && 758 !pipe->top_pipe && !pipe->prev_odm_pipe) { 759 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where 760 // we run through DML without calculating "natural" P-state support 761 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 762 763 } 764 pipe_idx++; 765 } 766 if (subvp_count == 2) { 767 update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); 768 } 769 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 770 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; 771 772 // Store the original watermark value for this SubVP config so we can lower it when the 773 // MCLK switch starts 774 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * 775 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; 776 777 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; 778 } 779 780 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 781 } 782 783 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) 784 { 785 if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) 786 return false; 787 return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data); 788 } 789 790 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 791 { 792 struct dmub_diagnostic_data diag_data = {0}; 793 794 if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 795 DC_LOG_ERROR("%s: invalid parameters.", __func__); 796 return; 797 } 798 799 if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) { 800 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); 801 return; 802 } 803 804 DC_LOG_DEBUG("DMCUB STATE:"); 805 DC_LOG_DEBUG(" dmcub_version : %08x", diag_data.dmcub_version); 806 DC_LOG_DEBUG(" scratch [0] : %08x", diag_data.scratch[0]); 807 DC_LOG_DEBUG(" scratch [1] : %08x", diag_data.scratch[1]); 808 DC_LOG_DEBUG(" scratch [2] : %08x", diag_data.scratch[2]); 809 DC_LOG_DEBUG(" scratch [3] : %08x", diag_data.scratch[3]); 810 DC_LOG_DEBUG(" scratch [4] : %08x", diag_data.scratch[4]); 811 DC_LOG_DEBUG(" scratch [5] : %08x", diag_data.scratch[5]); 812 DC_LOG_DEBUG(" scratch [6] : %08x", diag_data.scratch[6]); 813 DC_LOG_DEBUG(" scratch [7] : %08x", diag_data.scratch[7]); 814 DC_LOG_DEBUG(" scratch [8] : %08x", diag_data.scratch[8]); 815 DC_LOG_DEBUG(" scratch [9] : %08x", diag_data.scratch[9]); 816 DC_LOG_DEBUG(" scratch [10] : %08x", diag_data.scratch[10]); 817 DC_LOG_DEBUG(" scratch [11] : %08x", diag_data.scratch[11]); 818 DC_LOG_DEBUG(" scratch [12] : %08x", diag_data.scratch[12]); 819 DC_LOG_DEBUG(" scratch [13] : %08x", diag_data.scratch[13]); 820 DC_LOG_DEBUG(" scratch [14] : %08x", diag_data.scratch[14]); 821 DC_LOG_DEBUG(" scratch [15] : %08x", diag_data.scratch[15]); 822 DC_LOG_DEBUG(" pc : %08x", diag_data.pc); 823 DC_LOG_DEBUG(" unk_fault_addr : %08x", diag_data.undefined_address_fault_addr); 824 DC_LOG_DEBUG(" inst_fault_addr : %08x", diag_data.inst_fetch_fault_addr); 825 DC_LOG_DEBUG(" data_fault_addr : %08x", diag_data.data_write_fault_addr); 826 DC_LOG_DEBUG(" inbox1_rptr : %08x", diag_data.inbox1_rptr); 827 DC_LOG_DEBUG(" inbox1_wptr : %08x", diag_data.inbox1_wptr); 828 DC_LOG_DEBUG(" inbox1_size : %08x", diag_data.inbox1_size); 829 DC_LOG_DEBUG(" inbox0_rptr : %08x", diag_data.inbox0_rptr); 830 DC_LOG_DEBUG(" inbox0_wptr : %08x", diag_data.inbox0_wptr); 831 DC_LOG_DEBUG(" inbox0_size : %08x", diag_data.inbox0_size); 832 DC_LOG_DEBUG(" is_enabled : %d", diag_data.is_dmcub_enabled); 833 DC_LOG_DEBUG(" is_soft_reset : %d", diag_data.is_dmcub_soft_reset); 834 DC_LOG_DEBUG(" is_secure_reset : %d", diag_data.is_dmcub_secure_reset); 835 DC_LOG_DEBUG(" is_traceport_en : %d", diag_data.is_traceport_en); 836 DC_LOG_DEBUG(" is_cw0_en : %d", diag_data.is_cw0_enabled); 837 DC_LOG_DEBUG(" is_cw6_en : %d", diag_data.is_cw6_enabled); 838 } 839 840 static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) 841 { 842 struct pipe_ctx *test_pipe, *split_pipe; 843 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; 844 struct rect r1 = scl_data->recout, r2, r2_half; 845 int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b; 846 int cur_layer = pipe_ctx->plane_state->layer_index; 847 848 /** 849 * Disable the cursor if there's another pipe above this with a 850 * plane that contains this pipe's viewport to prevent double cursor 851 * and incorrect scaling artifacts. 852 */ 853 for (test_pipe = pipe_ctx->top_pipe; test_pipe; 854 test_pipe = test_pipe->top_pipe) { 855 // Skip invisible layer and pipe-split plane on same layer 856 if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer) 857 continue; 858 859 r2 = test_pipe->plane_res.scl_data.recout; 860 r2_r = r2.x + r2.width; 861 r2_b = r2.y + r2.height; 862 split_pipe = test_pipe; 863 864 /** 865 * There is another half plane on same layer because of 866 * pipe-split, merge together per same height. 867 */ 868 for (split_pipe = pipe_ctx->top_pipe; split_pipe; 869 split_pipe = split_pipe->top_pipe) 870 if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) { 871 r2_half = split_pipe->plane_res.scl_data.recout; 872 r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x; 873 r2.width = r2.width + r2_half.width; 874 r2_r = r2.x + r2.width; 875 break; 876 } 877 878 if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b) 879 return true; 880 } 881 882 return false; 883 } 884 885 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx) 886 { 887 if (pipe_ctx->plane_state != NULL) { 888 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 889 return false; 890 891 if (dc_can_pipe_disable_cursor(pipe_ctx)) 892 return false; 893 } 894 895 if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || 896 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) && 897 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1) 898 return true; 899 900 if (pipe_ctx->stream->link->replay_settings.config.replay_supported) 901 return true; 902 903 return false; 904 } 905 906 static void dc_build_cursor_update_payload0( 907 struct pipe_ctx *pipe_ctx, uint8_t p_idx, 908 struct dmub_cmd_update_cursor_payload0 *payload) 909 { 910 struct hubp *hubp = pipe_ctx->plane_res.hubp; 911 unsigned int panel_inst = 0; 912 913 if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, 914 pipe_ctx->stream->link, &panel_inst)) 915 return; 916 917 /* Payload: Cursor Rect is built from position & attribute 918 * x & y are obtained from postion 919 */ 920 payload->cursor_rect.x = hubp->cur_rect.x; 921 payload->cursor_rect.y = hubp->cur_rect.y; 922 /* w & h are obtained from attribute */ 923 payload->cursor_rect.width = hubp->cur_rect.w; 924 payload->cursor_rect.height = hubp->cur_rect.h; 925 926 payload->enable = hubp->pos.cur_ctl.bits.cur_enable; 927 payload->pipe_idx = p_idx; 928 payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 929 payload->panel_inst = panel_inst; 930 } 931 932 static void dc_build_cursor_position_update_payload0( 933 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx, 934 const struct hubp *hubp, const struct dpp *dpp) 935 { 936 /* Hubp */ 937 pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw; 938 pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw; 939 pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw; 940 pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw; 941 942 /* dpp */ 943 pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw; 944 pl->position_cfg.pipe_idx = p_idx; 945 } 946 947 static void dc_build_cursor_attribute_update_payload1( 948 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx, 949 const struct hubp *hubp, const struct dpp *dpp) 950 { 951 /* Hubp */ 952 pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH; 953 pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR; 954 pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw; 955 pl_A->aHubp.size.raw = hubp->att.size.raw; 956 pl_A->aHubp.settings.raw = hubp->att.settings.raw; 957 958 /* dpp */ 959 pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw; 960 } 961 962 /** 963 * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command 964 * 965 * @pCtx: [in] pipe context 966 * @pipe_idx: [in] pipe index 967 * 968 * This function would store the cursor related information and pass it into 969 * dmub 970 */ 971 void dc_send_update_cursor_info_to_dmu( 972 struct pipe_ctx *pCtx, uint8_t pipe_idx) 973 { 974 union dmub_rb_cmd cmd[2]; 975 union dmub_cmd_update_cursor_info_data *update_cursor_info_0 = 976 &cmd[0].update_cursor_info.update_cursor_info_data; 977 978 memset(cmd, 0, sizeof(cmd)); 979 980 if (!dc_dmub_should_update_cursor_data(pCtx)) 981 return; 982 /* 983 * Since we use multi_cmd_pending for dmub command, the 2nd command is 984 * only assigned to store cursor attributes info. 985 * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other 986 * is to store cursor position info. 987 * 988 * Command heaer type must be the same type if using multi_cmd_pending. 989 * Besides, while process 2nd command in DMU, the sub type is useless. 990 * So it's meanless to pass the sub type header with different type. 991 */ 992 993 { 994 /* Build Payload#0 Header */ 995 cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 996 cmd[0].update_cursor_info.header.payload_bytes = 997 sizeof(cmd[0].update_cursor_info.update_cursor_info_data); 998 cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd 999 1000 /* Prepare Payload */ 1001 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info_0->payload0); 1002 1003 dc_build_cursor_position_update_payload0(&update_cursor_info_0->payload0, pipe_idx, 1004 pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1005 } 1006 { 1007 /* Build Payload#1 Header */ 1008 cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 1009 cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg); 1010 cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command. 1011 1012 dc_build_cursor_attribute_update_payload1( 1013 &cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg, 1014 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1015 1016 /* Combine 2nd cmds update_curosr_info to DMU */ 1017 dm_execute_dmub_cmd_list(pCtx->stream->ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT); 1018 } 1019 } 1020 1021 bool dc_dmub_check_min_version(struct dmub_srv *srv) 1022 { 1023 if (!srv->hw_funcs.is_psrsu_supported) 1024 return true; 1025 return srv->hw_funcs.is_psrsu_supported(srv); 1026 } 1027 1028 void dc_dmub_srv_enable_dpia_trace(const struct dc *dc) 1029 { 1030 struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; 1031 struct dmub_srv *dmub; 1032 enum dmub_status status; 1033 static const uint32_t timeout_us = 30; 1034 1035 if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 1036 DC_LOG_ERROR("%s: invalid parameters.", __func__); 1037 return; 1038 } 1039 1040 dmub = dc_dmub_srv->dmub; 1041 1042 status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1, 0x0010, timeout_us); 1043 if (status != DMUB_STATUS_OK) { 1044 DC_LOG_ERROR("timeout updating trace buffer mask word\n"); 1045 return; 1046 } 1047 1048 status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK, 0x0000, timeout_us); 1049 if (status != DMUB_STATUS_OK) { 1050 DC_LOG_ERROR("timeout updating trace buffer mask word\n"); 1051 return; 1052 } 1053 1054 DC_LOG_DEBUG("Enabled DPIA trace\n"); 1055 }