1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc.h" 27 #include "dc_dmub_srv.h" 28 #include "../dmub/dmub_srv.h" 29 #include "dm_helpers.h" 30 #include "dc_hw_types.h" 31 #include "core_types.h" 32 #include "../basics/conversion.h" 33 #include "cursor_reg_cache.h" 34 35 #define CTX dc_dmub_srv->ctx 36 #define DC_LOGGER CTX->logger 37 38 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, 39 struct dmub_srv *dmub) 40 { 41 dc_srv->dmub = dmub; 42 dc_srv->ctx = dc->ctx; 43 } 44 45 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) 46 { 47 struct dc_dmub_srv *dc_srv = 48 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL); 49 50 if (dc_srv == NULL) { 51 BREAK_TO_DEBUGGER(); 52 return NULL; 53 } 54 55 dc_dmub_srv_construct(dc_srv, dc, dmub); 56 57 return dc_srv; 58 } 59 60 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv) 61 { 62 if (*dmub_srv) { 63 kfree(*dmub_srv); 64 *dmub_srv = NULL; 65 } 66 } 67 68 void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv, 69 union dmub_rb_cmd *cmd) 70 { 71 struct dmub_srv *dmub = dc_dmub_srv->dmub; 72 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 73 enum dmub_status status; 74 75 status = dmub_srv_cmd_queue(dmub, cmd); 76 if (status == DMUB_STATUS_OK) 77 return; 78 79 if (status != DMUB_STATUS_QUEUE_FULL) 80 goto error; 81 82 /* Execute and wait for queue to become empty again. */ 83 dc_dmub_srv_cmd_execute(dc_dmub_srv); 84 dc_dmub_srv_wait_idle(dc_dmub_srv); 85 86 /* Requeue the command. */ 87 status = dmub_srv_cmd_queue(dmub, cmd); 88 if (status == DMUB_STATUS_OK) 89 return; 90 91 error: 92 DC_ERROR("Error queuing DMUB command: status=%d\n", status); 93 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 94 } 95 96 void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv) 97 { 98 struct dmub_srv *dmub = dc_dmub_srv->dmub; 99 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 100 enum dmub_status status; 101 102 status = dmub_srv_cmd_execute(dmub); 103 if (status != DMUB_STATUS_OK) { 104 DC_ERROR("Error starting DMUB execution: status=%d\n", status); 105 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 106 } 107 } 108 109 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) 110 { 111 struct dmub_srv *dmub = dc_dmub_srv->dmub; 112 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 113 enum dmub_status status; 114 115 status = dmub_srv_wait_for_idle(dmub, 100000); 116 if (status != DMUB_STATUS_OK) { 117 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); 118 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 119 } 120 } 121 122 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv) 123 { 124 struct dmub_srv *dmub = dmub_srv->dmub; 125 struct dc_context *dc_ctx = dmub_srv->ctx; 126 enum dmub_status status = DMUB_STATUS_OK; 127 128 status = dmub_srv_clear_inbox0_ack(dmub); 129 if (status != DMUB_STATUS_OK) { 130 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status); 131 dc_dmub_srv_log_diagnostic_data(dmub_srv); 132 } 133 } 134 135 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv) 136 { 137 struct dmub_srv *dmub = dmub_srv->dmub; 138 struct dc_context *dc_ctx = dmub_srv->ctx; 139 enum dmub_status status = DMUB_STATUS_OK; 140 141 status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); 142 if (status != DMUB_STATUS_OK) { 143 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n"); 144 dc_dmub_srv_log_diagnostic_data(dmub_srv); 145 } 146 } 147 148 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, 149 union dmub_inbox0_data_register data) 150 { 151 struct dmub_srv *dmub = dmub_srv->dmub; 152 struct dc_context *dc_ctx = dmub_srv->ctx; 153 enum dmub_status status = DMUB_STATUS_OK; 154 155 status = dmub_srv_send_inbox0_cmd(dmub, data); 156 if (status != DMUB_STATUS_OK) { 157 DC_ERROR("Error sending INBOX0 cmd\n"); 158 dc_dmub_srv_log_diagnostic_data(dmub_srv); 159 } 160 } 161 162 bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd) 163 { 164 struct dmub_srv *dmub; 165 enum dmub_status status; 166 167 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 168 return false; 169 170 dmub = dc_dmub_srv->dmub; 171 172 status = dmub_srv_cmd_with_reply_data(dmub, cmd); 173 if (status != DMUB_STATUS_OK) { 174 DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 175 return false; 176 } 177 178 return true; 179 } 180 181 void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv) 182 { 183 struct dmub_srv *dmub = dc_dmub_srv->dmub; 184 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 185 enum dmub_status status; 186 187 for (;;) { 188 /* Wait up to a second for PHY init. */ 189 status = dmub_srv_wait_for_phy_init(dmub, 1000000); 190 if (status == DMUB_STATUS_OK) 191 /* Initialization OK */ 192 break; 193 194 DC_ERROR("DMCUB PHY init failed: status=%d\n", status); 195 ASSERT(0); 196 197 if (status != DMUB_STATUS_TIMEOUT) 198 /* 199 * Server likely initialized or we don't have 200 * DMCUB HW support - this won't end. 201 */ 202 break; 203 204 /* Continue spinning so we don't hang the ASIC. */ 205 } 206 } 207 208 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 209 unsigned int stream_mask) 210 { 211 struct dmub_srv *dmub; 212 const uint32_t timeout = 30; 213 214 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 215 return false; 216 217 dmub = dc_dmub_srv->dmub; 218 219 return dmub_srv_send_gpint_command( 220 dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, 221 stream_mask, timeout) == DMUB_STATUS_OK; 222 } 223 224 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) 225 { 226 struct dmub_srv *dmub; 227 struct dc_context *dc_ctx; 228 union dmub_fw_boot_status boot_status; 229 enum dmub_status status; 230 231 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 232 return false; 233 234 dmub = dc_dmub_srv->dmub; 235 dc_ctx = dc_dmub_srv->ctx; 236 237 status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 238 if (status != DMUB_STATUS_OK) { 239 DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 240 return false; 241 } 242 243 return boot_status.bits.restore_required; 244 } 245 246 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) 247 { 248 struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; 249 return dmub_srv_get_outbox0_msg(dmub, entry); 250 } 251 252 void dc_dmub_trace_event_control(struct dc *dc, bool enable) 253 { 254 dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); 255 } 256 257 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) 258 { 259 union dmub_rb_cmd cmd = { 0 }; 260 261 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 262 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE; 263 cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 264 cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 265 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 266 267 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 268 269 // Send the command to the DMCUB. 270 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 271 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 272 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 273 } 274 275 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) 276 { 277 union dmub_rb_cmd cmd = { 0 }; 278 279 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 280 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER; 281 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 282 283 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 284 285 // Send the command to the DMCUB. 286 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 287 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 288 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 289 } 290 291 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) 292 { 293 uint8_t pipes = 0; 294 int i = 0; 295 296 for (i = 0; i < MAX_PIPES; i++) { 297 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 298 299 if (pipe->stream == stream && pipe->stream_res.tg) 300 pipes = i; 301 } 302 return pipes; 303 } 304 305 static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context, 306 struct pipe_ctx *head_pipe, 307 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data) 308 { 309 int j; 310 int pipe_idx = 0; 311 312 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; 313 for (j = 0; j < dc->res_pool->pipe_count; j++) { 314 struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j]; 315 316 if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) { 317 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; 318 } 319 } 320 fams_pipe_data->pipe_count = pipe_idx; 321 } 322 323 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) 324 { 325 union dmub_rb_cmd cmd = { 0 }; 326 struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; 327 int i = 0, k = 0; 328 int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. 329 uint8_t visual_confirm_enabled; 330 331 if (dc == NULL) 332 return false; 333 334 visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; 335 336 // Format command. 337 cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 338 cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL; 339 cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate; 340 cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; 341 342 for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { 343 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 344 345 if (!pipe->top_pipe && !pipe->prev_odm_pipe && pipe->stream && pipe->stream->fpo_in_use) { 346 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 347 uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000; 348 349 config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz; 350 config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz; 351 config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps; 352 config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream); 353 dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]); 354 k++; 355 } 356 } 357 cmd.fw_assisted_mclk_switch.header.payload_bytes = 358 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header); 359 360 // Send the command to the DMCUB. 361 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 362 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 363 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 364 365 return true; 366 } 367 368 void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub) 369 { 370 union dmub_rb_cmd cmd = { 0 }; 371 enum dmub_status status; 372 373 if (!dmub) { 374 return; 375 } 376 377 memset(&cmd, 0, sizeof(cmd)); 378 379 /* Prepare fw command */ 380 cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; 381 cmd.query_feature_caps.header.sub_type = 0; 382 cmd.query_feature_caps.header.ret_status = 1; 383 cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); 384 385 /* Send command to fw */ 386 status = dmub_srv_cmd_with_reply_data(dmub, &cmd); 387 388 ASSERT(status == DMUB_STATUS_OK); 389 390 /* If command was processed, copy feature caps to dmub srv */ 391 if (status == DMUB_STATUS_OK && 392 cmd.query_feature_caps.header.ret_status == 0) { 393 memcpy(&dmub->feature_caps, 394 &cmd.query_feature_caps.query_feature_caps_data, 395 sizeof(struct dmub_feature_caps)); 396 } 397 } 398 399 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx) 400 { 401 union dmub_rb_cmd cmd = { 0 }; 402 enum dmub_status status; 403 unsigned int panel_inst = 0; 404 405 dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst); 406 407 memset(&cmd, 0, sizeof(cmd)); 408 409 // Prepare fw command 410 cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR; 411 cmd.visual_confirm_color.header.sub_type = 0; 412 cmd.visual_confirm_color.header.ret_status = 1; 413 cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data); 414 cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst; 415 416 // Send command to fw 417 status = dmub_srv_cmd_with_reply_data(dc->ctx->dmub_srv->dmub, &cmd); 418 419 ASSERT(status == DMUB_STATUS_OK); 420 421 // If command was processed, copy feature caps to dmub srv 422 if (status == DMUB_STATUS_OK && 423 cmd.visual_confirm_color.header.ret_status == 0) { 424 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color, 425 &cmd.visual_confirm_color.visual_confirm_color_data, 426 sizeof(struct dmub_visual_confirm_color)); 427 } 428 } 429 430 /** 431 * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command 432 * 433 * @dc: [in] current dc state 434 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 435 * @vblank_pipe: [in] pipe_ctx for the DRR pipe 436 * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info 437 * 438 * Populate the DMCUB SubVP command with DRR pipe info. All the information 439 * required for calculating the SubVP + DRR microschedule is populated here. 440 * 441 * High level algorithm: 442 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 443 * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule 444 * 3. Populate the drr_info with the min and max supported vtotal values 445 */ 446 static void populate_subvp_cmd_drr_info(struct dc *dc, 447 struct pipe_ctx *subvp_pipe, 448 struct pipe_ctx *vblank_pipe, 449 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data) 450 { 451 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 452 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 453 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 454 uint16_t drr_frame_us = 0; 455 uint16_t min_drr_supported_us = 0; 456 uint16_t max_drr_supported_us = 0; 457 uint16_t max_drr_vblank_us = 0; 458 uint16_t max_drr_mallregion_us = 0; 459 uint16_t mall_region_us = 0; 460 uint16_t prefetch_us = 0; 461 uint16_t subvp_active_us = 0; 462 uint16_t drr_active_us = 0; 463 uint16_t min_vtotal_supported = 0; 464 uint16_t max_vtotal_supported = 0; 465 466 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; 467 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping 468 pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now 469 470 drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000), 471 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 472 // P-State allow width and FW delays already included phantom_timing->v_addressable 473 mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000), 474 (((uint64_t)phantom_timing->pix_clk_100hz * 100))); 475 min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 476 min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us), 477 (((uint64_t)drr_timing->h_total * 1000000))); 478 479 prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000), 480 (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 481 subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000), 482 (((uint64_t)main_timing->pix_clk_100hz * 100))); 483 drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000), 484 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 485 max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - 486 dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us; 487 max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us; 488 max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; 489 max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us), 490 (((uint64_t)drr_timing->h_total * 1000000))); 491 492 /* When calculating the max vtotal supported for SubVP + DRR cases, add 493 * margin due to possible rounding errors (being off by 1 line in the 494 * FW calculation can incorrectly push the P-State switch to wait 1 frame 495 * longer). 496 */ 497 max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us; 498 499 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; 500 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; 501 pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us; 502 } 503 504 /** 505 * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command 506 * 507 * @dc: [in] current dc state 508 * @context: [in] new dc state 509 * @cmd: [in] DMUB cmd to be populated with SubVP info 510 * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe 511 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 512 * 513 * Populate the DMCUB SubVP command with VBLANK pipe info. All the information 514 * required to calculate the microschedule for SubVP + VBLANK case is stored in 515 * the pipe_data (subvp_data and vblank_data). Also check if the VBLANK pipe 516 * is a DRR display -- if it is make a call to populate drr_info. 517 */ 518 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, 519 struct dc_state *context, 520 union dmub_rb_cmd *cmd, 521 struct pipe_ctx *vblank_pipe, 522 uint8_t cmd_pipe_index) 523 { 524 uint32_t i; 525 struct pipe_ctx *pipe = NULL; 526 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 527 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 528 529 // Find the SubVP pipe 530 for (i = 0; i < dc->res_pool->pipe_count; i++) { 531 pipe = &context->res_ctx.pipe_ctx[i]; 532 533 // We check for master pipe, but it shouldn't matter since we only need 534 // the pipe for timing info (stream should be same for any pipe splits) 535 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 536 continue; 537 538 // Find the SubVP pipe 539 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 540 break; 541 } 542 543 pipe_data->mode = VBLANK; 544 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; 545 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - 546 vblank_pipe->stream->timing.v_front_porch; 547 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; 548 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; 549 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; 550 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; 551 pipe_data->pipe_config.vblank_data.vblank_end = 552 vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; 553 554 if (vblank_pipe->stream->ignore_msa_timing_param) 555 populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data); 556 } 557 558 /** 559 * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case 560 * 561 * @dc: [in] current dc state 562 * @context: [in] new dc state 563 * @cmd: [in] DMUB cmd to be populated with SubVP info 564 * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2) 565 * 566 * For SubVP + SubVP, we use a single vertical interrupt to start the 567 * microschedule for both SubVP pipes. In order for this to work correctly, the 568 * MALL REGION of both SubVP pipes must start at the same time. This function 569 * lengthens the prefetch end to mall start delay of the SubVP pipe that has 570 * the shorter prefetch so that both MALL REGION's will start at the same time. 571 */ 572 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, 573 struct dc_state *context, 574 union dmub_rb_cmd *cmd, 575 struct pipe_ctx *subvp_pipes[]) 576 { 577 uint32_t subvp0_prefetch_us = 0; 578 uint32_t subvp1_prefetch_us = 0; 579 uint32_t prefetch_delta_us = 0; 580 struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing; 581 struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing; 582 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL; 583 584 subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * 585 (uint64_t)phantom_timing0->h_total * 1000000), 586 (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 587 subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * 588 (uint64_t)phantom_timing1->h_total * 1000000), 589 (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 590 591 // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) 592 // should increase it's prefetch time to match the other 593 if (subvp0_prefetch_us > subvp1_prefetch_us) { 594 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; 595 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; 596 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 597 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 598 ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), 599 ((uint64_t)phantom_timing1->h_total * 1000000)); 600 601 } else if (subvp1_prefetch_us > subvp0_prefetch_us) { 602 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; 603 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; 604 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 605 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 606 ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), 607 ((uint64_t)phantom_timing0->h_total * 1000000)); 608 } 609 } 610 611 /** 612 * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command 613 * 614 * @dc: [in] current dc state 615 * @context: [in] new dc state 616 * @cmd: [in] DMUB cmd to be populated with SubVP info 617 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 618 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 619 * 620 * Populate the DMCUB SubVP command with SubVP pipe info. All the information 621 * required to calculate the microschedule for the SubVP pipe is stored in the 622 * pipe_data of the DMCUB SubVP command. 623 */ 624 static void populate_subvp_cmd_pipe_info(struct dc *dc, 625 struct dc_state *context, 626 union dmub_rb_cmd *cmd, 627 struct pipe_ctx *subvp_pipe, 628 uint8_t cmd_pipe_index) 629 { 630 uint32_t j; 631 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 632 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 633 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 634 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 635 uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den; 636 637 pipe_data->mode = SUBVP; 638 pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; 639 pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; 640 pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; 641 pipe_data->pipe_config.subvp_data.main_vblank_start = 642 main_timing->v_total - main_timing->v_front_porch; 643 pipe_data->pipe_config.subvp_data.main_vblank_end = 644 main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; 645 pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; 646 pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst; 647 pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param; 648 649 /* Calculate the scaling factor from the src and dst height. 650 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2. 651 * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor" 652 * 653 * Make sure to combine stream and plane scaling together. 654 */ 655 reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height, 656 &out_num_stream, &out_den_stream); 657 reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height, 658 &out_num_plane, &out_den_plane); 659 reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den); 660 pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num; 661 pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den; 662 663 // Prefetch lines is equal to VACTIVE + BP + VSYNC 664 pipe_data->pipe_config.subvp_data.prefetch_lines = 665 phantom_timing->v_total - phantom_timing->v_front_porch; 666 667 // Round up 668 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 669 div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 670 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 671 pipe_data->pipe_config.subvp_data.processing_delay_lines = 672 div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 673 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 674 675 if (subvp_pipe->bottom_pipe) { 676 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; 677 } else if (subvp_pipe->next_odm_pipe) { 678 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; 679 } else { 680 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0; 681 } 682 683 // Find phantom pipe index based on phantom stream 684 for (j = 0; j < dc->res_pool->pipe_count; j++) { 685 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; 686 687 if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) { 688 pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst; 689 if (phantom_pipe->bottom_pipe) { 690 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; 691 } else if (phantom_pipe->next_odm_pipe) { 692 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; 693 } else { 694 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0; 695 } 696 break; 697 } 698 } 699 } 700 701 /** 702 * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command 703 * 704 * @dc: [in] current dc state 705 * @context: [in] new dc state 706 * @enable: [in] if true enables the pipes population 707 * 708 * This function loops through each pipe and populates the DMUB SubVP CMD info 709 * based on the pipe (e.g. SubVP, VBLANK). 710 */ 711 void dc_dmub_setup_subvp_dmub_command(struct dc *dc, 712 struct dc_state *context, 713 bool enable) 714 { 715 uint8_t cmd_pipe_index = 0; 716 uint32_t i, pipe_idx; 717 uint8_t subvp_count = 0; 718 union dmub_rb_cmd cmd; 719 struct pipe_ctx *subvp_pipes[2]; 720 uint32_t wm_val_refclk = 0; 721 722 memset(&cmd, 0, sizeof(cmd)); 723 // FW command for SUBVP 724 cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 725 cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD; 726 cmd.fw_assisted_mclk_switch_v2.header.payload_bytes = 727 sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header); 728 729 for (i = 0; i < dc->res_pool->pipe_count; i++) { 730 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 731 732 if (!pipe->stream) 733 continue; 734 735 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe 736 */ 737 if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && 738 pipe->stream->mall_stream_config.type == SUBVP_MAIN) 739 subvp_pipes[subvp_count++] = pipe; 740 } 741 742 if (enable) { 743 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd 744 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 745 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 746 747 if (!pipe->stream) 748 continue; 749 750 /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe. 751 * Any ODM or MPC splits being used in SubVP will be handled internally in 752 * populate_subvp_cmd_pipe_info 753 */ 754 if (pipe->plane_state && pipe->stream->mall_stream_config.paired_stream && 755 !pipe->top_pipe && !pipe->prev_odm_pipe && 756 pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 757 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 758 } else if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_NONE && 759 !pipe->top_pipe && !pipe->prev_odm_pipe) { 760 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where 761 // we run through DML without calculating "natural" P-state support 762 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 763 764 } 765 pipe_idx++; 766 } 767 if (subvp_count == 2) { 768 update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); 769 } 770 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 771 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; 772 773 // Store the original watermark value for this SubVP config so we can lower it when the 774 // MCLK switch starts 775 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * 776 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; 777 778 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; 779 } 780 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 781 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 782 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 783 } 784 785 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) 786 { 787 if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) 788 return false; 789 return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data); 790 } 791 792 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 793 { 794 struct dmub_diagnostic_data diag_data = {0}; 795 796 if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 797 DC_LOG_ERROR("%s: invalid parameters.", __func__); 798 return; 799 } 800 801 if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) { 802 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); 803 return; 804 } 805 806 DC_LOG_DEBUG( 807 "DMCUB STATE\n" 808 " dmcub_version : %08x\n" 809 " scratch [0] : %08x\n" 810 " scratch [1] : %08x\n" 811 " scratch [2] : %08x\n" 812 " scratch [3] : %08x\n" 813 " scratch [4] : %08x\n" 814 " scratch [5] : %08x\n" 815 " scratch [6] : %08x\n" 816 " scratch [7] : %08x\n" 817 " scratch [8] : %08x\n" 818 " scratch [9] : %08x\n" 819 " scratch [10] : %08x\n" 820 " scratch [11] : %08x\n" 821 " scratch [12] : %08x\n" 822 " scratch [13] : %08x\n" 823 " scratch [14] : %08x\n" 824 " scratch [15] : %08x\n" 825 " pc : %08x\n" 826 " unk_fault_addr : %08x\n" 827 " inst_fault_addr : %08x\n" 828 " data_fault_addr : %08x\n" 829 " inbox1_rptr : %08x\n" 830 " inbox1_wptr : %08x\n" 831 " inbox1_size : %08x\n" 832 " inbox0_rptr : %08x\n" 833 " inbox0_wptr : %08x\n" 834 " inbox0_size : %08x\n" 835 " is_enabled : %d\n" 836 " is_soft_reset : %d\n" 837 " is_secure_reset : %d\n" 838 " is_traceport_en : %d\n" 839 " is_cw0_en : %d\n" 840 " is_cw6_en : %d\n", 841 diag_data.dmcub_version, 842 diag_data.scratch[0], 843 diag_data.scratch[1], 844 diag_data.scratch[2], 845 diag_data.scratch[3], 846 diag_data.scratch[4], 847 diag_data.scratch[5], 848 diag_data.scratch[6], 849 diag_data.scratch[7], 850 diag_data.scratch[8], 851 diag_data.scratch[9], 852 diag_data.scratch[10], 853 diag_data.scratch[11], 854 diag_data.scratch[12], 855 diag_data.scratch[13], 856 diag_data.scratch[14], 857 diag_data.scratch[15], 858 diag_data.pc, 859 diag_data.undefined_address_fault_addr, 860 diag_data.inst_fetch_fault_addr, 861 diag_data.data_write_fault_addr, 862 diag_data.inbox1_rptr, 863 diag_data.inbox1_wptr, 864 diag_data.inbox1_size, 865 diag_data.inbox0_rptr, 866 diag_data.inbox0_wptr, 867 diag_data.inbox0_size, 868 diag_data.is_dmcub_enabled, 869 diag_data.is_dmcub_soft_reset, 870 diag_data.is_dmcub_secure_reset, 871 diag_data.is_traceport_en, 872 diag_data.is_cw0_enabled, 873 diag_data.is_cw6_enabled); 874 } 875 876 static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) 877 { 878 struct pipe_ctx *test_pipe, *split_pipe; 879 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; 880 struct rect r1 = scl_data->recout, r2, r2_half; 881 int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b; 882 int cur_layer = pipe_ctx->plane_state->layer_index; 883 884 /** 885 * Disable the cursor if there's another pipe above this with a 886 * plane that contains this pipe's viewport to prevent double cursor 887 * and incorrect scaling artifacts. 888 */ 889 for (test_pipe = pipe_ctx->top_pipe; test_pipe; 890 test_pipe = test_pipe->top_pipe) { 891 // Skip invisible layer and pipe-split plane on same layer 892 if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer) 893 continue; 894 895 r2 = test_pipe->plane_res.scl_data.recout; 896 r2_r = r2.x + r2.width; 897 r2_b = r2.y + r2.height; 898 split_pipe = test_pipe; 899 900 /** 901 * There is another half plane on same layer because of 902 * pipe-split, merge together per same height. 903 */ 904 for (split_pipe = pipe_ctx->top_pipe; split_pipe; 905 split_pipe = split_pipe->top_pipe) 906 if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) { 907 r2_half = split_pipe->plane_res.scl_data.recout; 908 r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x; 909 r2.width = r2.width + r2_half.width; 910 r2_r = r2.x + r2.width; 911 break; 912 } 913 914 if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b) 915 return true; 916 } 917 918 return false; 919 } 920 921 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx) 922 { 923 if (pipe_ctx->plane_state != NULL) { 924 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 925 return false; 926 927 if (dc_can_pipe_disable_cursor(pipe_ctx)) 928 return false; 929 } 930 931 if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || 932 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) && 933 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1) 934 return true; 935 936 return false; 937 } 938 939 static void dc_build_cursor_update_payload0( 940 struct pipe_ctx *pipe_ctx, uint8_t p_idx, 941 struct dmub_cmd_update_cursor_payload0 *payload) 942 { 943 struct hubp *hubp = pipe_ctx->plane_res.hubp; 944 unsigned int panel_inst = 0; 945 946 if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, 947 pipe_ctx->stream->link, &panel_inst)) 948 return; 949 950 /* Payload: Cursor Rect is built from position & attribute 951 * x & y are obtained from postion 952 */ 953 payload->cursor_rect.x = hubp->cur_rect.x; 954 payload->cursor_rect.y = hubp->cur_rect.y; 955 /* w & h are obtained from attribute */ 956 payload->cursor_rect.width = hubp->cur_rect.w; 957 payload->cursor_rect.height = hubp->cur_rect.h; 958 959 payload->enable = hubp->pos.cur_ctl.bits.cur_enable; 960 payload->pipe_idx = p_idx; 961 payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 962 payload->panel_inst = panel_inst; 963 } 964 965 static void dc_send_cmd_to_dmu(struct dc_dmub_srv *dmub_srv, 966 union dmub_rb_cmd *cmd) 967 { 968 dc_dmub_srv_cmd_queue(dmub_srv, cmd); 969 dc_dmub_srv_cmd_execute(dmub_srv); 970 dc_dmub_srv_wait_idle(dmub_srv); 971 } 972 973 static void dc_build_cursor_position_update_payload0( 974 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx, 975 const struct hubp *hubp, const struct dpp *dpp) 976 { 977 /* Hubp */ 978 pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw; 979 pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw; 980 pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw; 981 pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw; 982 983 /* dpp */ 984 pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw; 985 pl->position_cfg.pipe_idx = p_idx; 986 } 987 988 static void dc_build_cursor_attribute_update_payload1( 989 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx, 990 const struct hubp *hubp, const struct dpp *dpp) 991 { 992 /* Hubp */ 993 pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH; 994 pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR; 995 pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw; 996 pl_A->aHubp.size.raw = hubp->att.size.raw; 997 pl_A->aHubp.settings.raw = hubp->att.settings.raw; 998 999 /* dpp */ 1000 pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw; 1001 } 1002 1003 /** 1004 * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command 1005 * 1006 * @pCtx: [in] pipe context 1007 * @pipe_idx: [in] pipe index 1008 * 1009 * This function would store the cursor related information and pass it into 1010 * dmub 1011 */ 1012 void dc_send_update_cursor_info_to_dmu( 1013 struct pipe_ctx *pCtx, uint8_t pipe_idx) 1014 { 1015 union dmub_rb_cmd cmd = { 0 }; 1016 union dmub_cmd_update_cursor_info_data *update_cursor_info = 1017 &cmd.update_cursor_info.update_cursor_info_data; 1018 1019 if (!dc_dmub_should_update_cursor_data(pCtx)) 1020 return; 1021 /* 1022 * Since we use multi_cmd_pending for dmub command, the 2nd command is 1023 * only assigned to store cursor attributes info. 1024 * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other 1025 * is to store cursor position info. 1026 * 1027 * Command heaer type must be the same type if using multi_cmd_pending. 1028 * Besides, while process 2nd command in DMU, the sub type is useless. 1029 * So it's meanless to pass the sub type header with different type. 1030 */ 1031 1032 { 1033 /* Build Payload#0 Header */ 1034 cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 1035 cmd.update_cursor_info.header.payload_bytes = 1036 sizeof(cmd.update_cursor_info.update_cursor_info_data); 1037 cmd.update_cursor_info.header.multi_cmd_pending = 1; /* To combine multi dmu cmd, 1st cmd */ 1038 1039 /* Prepare Payload */ 1040 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info->payload0); 1041 1042 dc_build_cursor_position_update_payload0(&update_cursor_info->payload0, pipe_idx, 1043 pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1044 /* Send update_curosr_info to queue */ 1045 dc_dmub_srv_cmd_queue(pCtx->stream->ctx->dmub_srv, &cmd); 1046 } 1047 { 1048 /* Build Payload#1 Header */ 1049 memset(update_cursor_info, 0, sizeof(union dmub_cmd_update_cursor_info_data)); 1050 cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 1051 cmd.update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg); 1052 cmd.update_cursor_info.header.multi_cmd_pending = 0; /* Indicate it's the last command. */ 1053 1054 dc_build_cursor_attribute_update_payload1( 1055 &cmd.update_cursor_info.update_cursor_info_data.payload1.attribute_cfg, 1056 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1057 1058 /* Combine 2nd cmds update_curosr_info to DMU */ 1059 dc_send_cmd_to_dmu(pCtx->stream->ctx->dmub_srv, &cmd); 1060 } 1061 } 1062