1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dc.h"
27 #include "dc_dmub_srv.h"
28 #include "../dmub/dmub_srv.h"
29 #include "dm_helpers.h"
30 #include "dc_hw_types.h"
31 #include "core_types.h"
32 #include "../basics/conversion.h"
33 #include "cursor_reg_cache.h"
34 #include "resource.h"
35 
36 #define CTX dc_dmub_srv->ctx
37 #define DC_LOGGER CTX->logger
38 
39 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,
40 				  struct dmub_srv *dmub)
41 {
42 	dc_srv->dmub = dmub;
43 	dc_srv->ctx = dc->ctx;
44 }
45 
46 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)
47 {
48 	struct dc_dmub_srv *dc_srv =
49 		kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL);
50 
51 	if (dc_srv == NULL) {
52 		BREAK_TO_DEBUGGER();
53 		return NULL;
54 	}
55 
56 	dc_dmub_srv_construct(dc_srv, dc, dmub);
57 
58 	return dc_srv;
59 }
60 
61 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)
62 {
63 	if (*dmub_srv) {
64 		kfree(*dmub_srv);
65 		*dmub_srv = NULL;
66 	}
67 }
68 
69 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
70 {
71 	struct dmub_srv *dmub = dc_dmub_srv->dmub;
72 	struct dc_context *dc_ctx = dc_dmub_srv->ctx;
73 	enum dmub_status status;
74 
75 	status = dmub_srv_wait_for_idle(dmub, 100000);
76 	if (status != DMUB_STATUS_OK) {
77 		DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
78 		dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
79 	}
80 }
81 
82 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv)
83 {
84 	struct dmub_srv *dmub = dmub_srv->dmub;
85 	struct dc_context *dc_ctx = dmub_srv->ctx;
86 	enum dmub_status status = DMUB_STATUS_OK;
87 
88 	status = dmub_srv_clear_inbox0_ack(dmub);
89 	if (status != DMUB_STATUS_OK) {
90 		DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status);
91 		dc_dmub_srv_log_diagnostic_data(dmub_srv);
92 	}
93 }
94 
95 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv)
96 {
97 	struct dmub_srv *dmub = dmub_srv->dmub;
98 	struct dc_context *dc_ctx = dmub_srv->ctx;
99 	enum dmub_status status = DMUB_STATUS_OK;
100 
101 	status = dmub_srv_wait_for_inbox0_ack(dmub, 100000);
102 	if (status != DMUB_STATUS_OK) {
103 		DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n");
104 		dc_dmub_srv_log_diagnostic_data(dmub_srv);
105 	}
106 }
107 
108 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
109 		union dmub_inbox0_data_register data)
110 {
111 	struct dmub_srv *dmub = dmub_srv->dmub;
112 	struct dc_context *dc_ctx = dmub_srv->ctx;
113 	enum dmub_status status = DMUB_STATUS_OK;
114 
115 	status = dmub_srv_send_inbox0_cmd(dmub, data);
116 	if (status != DMUB_STATUS_OK) {
117 		DC_ERROR("Error sending INBOX0 cmd\n");
118 		dc_dmub_srv_log_diagnostic_data(dmub_srv);
119 	}
120 }
121 
122 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
123 {
124 	return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type);
125 }
126 
127 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type)
128 {
129 	struct dc_context *dc_ctx;
130 	struct dmub_srv *dmub;
131 	enum dmub_status status;
132 	int i;
133 
134 	if (!dc_dmub_srv || !dc_dmub_srv->dmub)
135 		return false;
136 
137 	dc_ctx = dc_dmub_srv->ctx;
138 	dmub = dc_dmub_srv->dmub;
139 
140 	for (i = 0 ; i < count; i++) {
141 		// Queue command
142 		status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
143 
144 		if (status == DMUB_STATUS_QUEUE_FULL) {
145 			/* Execute and wait for queue to become empty again. */
146 			dmub_srv_cmd_execute(dmub);
147 			dmub_srv_wait_for_idle(dmub, 100000);
148 
149 			/* Requeue the command. */
150 			status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
151 		}
152 
153 		if (status != DMUB_STATUS_OK) {
154 			DC_ERROR("Error queueing DMUB command: status=%d\n", status);
155 			dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
156 			return false;
157 		}
158 	}
159 
160 	status = dmub_srv_cmd_execute(dmub);
161 	if (status != DMUB_STATUS_OK) {
162 		DC_ERROR("Error starting DMUB execution: status=%d\n", status);
163 		dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
164 		return false;
165 	}
166 
167 	// Wait for DMUB to process command
168 	if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {
169 		status = dmub_srv_wait_for_idle(dmub, 100000);
170 
171 		if (status != DMUB_STATUS_OK) {
172 			DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
173 			dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
174 			return false;
175 		}
176 
177 		// Copy data back from ring buffer into command
178 		if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
179 			dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list);
180 	}
181 
182 	return true;
183 }
184 
185 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
186 {
187 	struct dmub_srv *dmub;
188 	struct dc_context *dc_ctx;
189 	union dmub_fw_boot_status boot_status;
190 	enum dmub_status status;
191 
192 	if (!dc_dmub_srv || !dc_dmub_srv->dmub)
193 		return false;
194 
195 	dmub = dc_dmub_srv->dmub;
196 	dc_ctx = dc_dmub_srv->ctx;
197 
198 	status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
199 	if (status != DMUB_STATUS_OK) {
200 		DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
201 		return false;
202 	}
203 
204 	return boot_status.bits.optimized_init_done;
205 }
206 
207 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
208 				    unsigned int stream_mask)
209 {
210 	struct dmub_srv *dmub;
211 	const uint32_t timeout = 30;
212 
213 	if (!dc_dmub_srv || !dc_dmub_srv->dmub)
214 		return false;
215 
216 	dmub = dc_dmub_srv->dmub;
217 
218 	return dmub_srv_send_gpint_command(
219 		       dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
220 		       stream_mask, timeout) == DMUB_STATUS_OK;
221 }
222 
223 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
224 {
225 	struct dmub_srv *dmub;
226 	struct dc_context *dc_ctx;
227 	union dmub_fw_boot_status boot_status;
228 	enum dmub_status status;
229 
230 	if (!dc_dmub_srv || !dc_dmub_srv->dmub)
231 		return false;
232 
233 	dmub = dc_dmub_srv->dmub;
234 	dc_ctx = dc_dmub_srv->ctx;
235 
236 	status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
237 	if (status != DMUB_STATUS_OK) {
238 		DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
239 		return false;
240 	}
241 
242 	return boot_status.bits.restore_required;
243 }
244 
245 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
246 {
247 	struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;
248 	return dmub_srv_get_outbox0_msg(dmub, entry);
249 }
250 
251 void dc_dmub_trace_event_control(struct dc *dc, bool enable)
252 {
253 	dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
254 }
255 
256 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)
257 {
258 	union dmub_rb_cmd cmd = { 0 };
259 
260 	cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
261 	cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE;
262 	cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max;
263 	cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min;
264 	cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
265 
266 	cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
267 
268 	// Send the command to the DMCUB.
269 	dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
270 }
271 
272 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
273 {
274 	union dmub_rb_cmd cmd = { 0 };
275 
276 	cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
277 	cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
278 	cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
279 
280 	cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
281 
282 	// Send the command to the DMCUB.
283 	dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
284 }
285 
286 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)
287 {
288 	uint8_t pipes = 0;
289 	int i = 0;
290 
291 	for (i = 0; i < MAX_PIPES; i++) {
292 		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
293 
294 		if (pipe->stream == stream && pipe->stream_res.tg)
295 			pipes = i;
296 	}
297 	return pipes;
298 }
299 
300 static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,
301 		struct pipe_ctx *head_pipe,
302 		struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data)
303 {
304 	int j;
305 	int pipe_idx = 0;
306 
307 	fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;
308 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
309 		struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
310 
311 		if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
312 			fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;
313 		}
314 	}
315 	fams_pipe_data->pipe_count = pipe_idx;
316 }
317 
318 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
319 {
320 	union dmub_rb_cmd cmd = { 0 };
321 	struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data;
322 	int i = 0, k = 0;
323 	int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it.
324 	uint8_t visual_confirm_enabled;
325 	int pipe_idx = 0;
326 
327 	if (dc == NULL)
328 		return false;
329 
330 	visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;
331 
332 	// Format command.
333 	cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
334 	cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL;
335 	cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate;
336 	cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled;
337 
338 	if (should_manage_pstate) {
339 		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
340 			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
341 
342 			if (!pipe->stream)
343 				continue;
344 
345 			/* If FAMS is being used to support P-State and there is a stream
346 			 * that does not use FAMS, we are in an FPO + VActive scenario.
347 			 * Assign vactive stretch margin in this case.
348 			 */
349 			if (!pipe->stream->fpo_in_use) {
350 				cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us;
351 				break;
352 			}
353 			pipe_idx++;
354 		}
355 	}
356 
357 	for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
358 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
359 
360 		if (resource_is_pipe_type(pipe, OTG_MASTER) && pipe->stream->fpo_in_use) {
361 			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
362 			uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;
363 
364 			config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
365 			config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
366 			config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
367 			config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
368 			dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);
369 			k++;
370 		}
371 	}
372 	cmd.fw_assisted_mclk_switch.header.payload_bytes =
373 		sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header);
374 
375 	// Send the command to the DMCUB.
376 	dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
377 
378 	return true;
379 }
380 
381 void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv)
382 {
383 	union dmub_rb_cmd cmd = { 0 };
384 
385 	if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
386 		return;
387 
388 	memset(&cmd, 0, sizeof(cmd));
389 
390 	/* Prepare fw command */
391 	cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS;
392 	cmd.query_feature_caps.header.sub_type = 0;
393 	cmd.query_feature_caps.header.ret_status = 1;
394 	cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);
395 
396 	/* If command was processed, copy feature caps to dmub srv */
397 	if (dm_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
398 	    cmd.query_feature_caps.header.ret_status == 0) {
399 		memcpy(&dc_dmub_srv->dmub->feature_caps,
400 		       &cmd.query_feature_caps.query_feature_caps_data,
401 		       sizeof(struct dmub_feature_caps));
402 	}
403 }
404 
405 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)
406 {
407 	union dmub_rb_cmd cmd = { 0 };
408 	unsigned int panel_inst = 0;
409 
410 	dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst);
411 
412 	memset(&cmd, 0, sizeof(cmd));
413 
414 	// Prepare fw command
415 	cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
416 	cmd.visual_confirm_color.header.sub_type = 0;
417 	cmd.visual_confirm_color.header.ret_status = 1;
418 	cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
419 	cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
420 
421 	// If command was processed, copy feature caps to dmub srv
422 	if (dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
423 		cmd.visual_confirm_color.header.ret_status == 0) {
424 		memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
425 			&cmd.visual_confirm_color.visual_confirm_color_data,
426 			sizeof(struct dmub_visual_confirm_color));
427 	}
428 }
429 
430 /**
431  * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command
432  *
433  * @dc: [in] current dc state
434  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
435  * @vblank_pipe: [in] pipe_ctx for the DRR pipe
436  * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info
437  *
438  * Populate the DMCUB SubVP command with DRR pipe info. All the information
439  * required for calculating the SubVP + DRR microschedule is populated here.
440  *
441  * High level algorithm:
442  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
443  * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule
444  * 3. Populate the drr_info with the min and max supported vtotal values
445  */
446 static void populate_subvp_cmd_drr_info(struct dc *dc,
447 		struct pipe_ctx *subvp_pipe,
448 		struct pipe_ctx *vblank_pipe,
449 		struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data)
450 {
451 	struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
452 	struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
453 	struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
454 	uint16_t drr_frame_us = 0;
455 	uint16_t min_drr_supported_us = 0;
456 	uint16_t max_drr_supported_us = 0;
457 	uint16_t max_drr_vblank_us = 0;
458 	uint16_t max_drr_mallregion_us = 0;
459 	uint16_t mall_region_us = 0;
460 	uint16_t prefetch_us = 0;
461 	uint16_t subvp_active_us = 0;
462 	uint16_t drr_active_us = 0;
463 	uint16_t min_vtotal_supported = 0;
464 	uint16_t max_vtotal_supported = 0;
465 
466 	pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;
467 	pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
468 	pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
469 
470 	drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000),
471 			(((uint64_t)drr_timing->pix_clk_100hz * 100)));
472 	// P-State allow width and FW delays already included phantom_timing->v_addressable
473 	mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000),
474 			(((uint64_t)phantom_timing->pix_clk_100hz * 100)));
475 	min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
476 	min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us),
477 			(((uint64_t)drr_timing->h_total * 1000000)));
478 
479 	prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000),
480 			(((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
481 	subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000),
482 			(((uint64_t)main_timing->pix_clk_100hz * 100)));
483 	drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000),
484 			(((uint64_t)drr_timing->pix_clk_100hz * 100)));
485 	max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us -
486 			dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us;
487 	max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;
488 	max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
489 	max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us),
490 			(((uint64_t)drr_timing->h_total * 1000000)));
491 
492 	/* When calculating the max vtotal supported for SubVP + DRR cases, add
493 	 * margin due to possible rounding errors (being off by 1 line in the
494 	 * FW calculation can incorrectly push the P-State switch to wait 1 frame
495 	 * longer).
496 	 */
497 	max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
498 
499 	pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
500 	pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
501 	pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
502 }
503 
504 /**
505  * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command
506  *
507  * @dc: [in] current dc state
508  * @context: [in] new dc state
509  * @cmd: [in] DMUB cmd to be populated with SubVP info
510  * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe
511  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
512  *
513  * Populate the DMCUB SubVP command with VBLANK pipe info. All the information
514  * required to calculate the microschedule for SubVP + VBLANK case is stored in
515  * the pipe_data (subvp_data and vblank_data).  Also check if the VBLANK pipe
516  * is a DRR display -- if it is make a call to populate drr_info.
517  */
518 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,
519 		struct dc_state *context,
520 		union dmub_rb_cmd *cmd,
521 		struct pipe_ctx *vblank_pipe,
522 		uint8_t cmd_pipe_index)
523 {
524 	uint32_t i;
525 	struct pipe_ctx *pipe = NULL;
526 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
527 			&cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
528 
529 	// Find the SubVP pipe
530 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
531 		pipe = &context->res_ctx.pipe_ctx[i];
532 
533 		// We check for master pipe, but it shouldn't matter since we only need
534 		// the pipe for timing info (stream should be same for any pipe splits)
535 		if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
536 				!resource_is_pipe_type(pipe, DPP_PIPE))
537 			continue;
538 
539 		// Find the SubVP pipe
540 		if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
541 			break;
542 	}
543 
544 	pipe_data->mode = VBLANK;
545 	pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
546 	pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
547 							vblank_pipe->stream->timing.v_front_porch;
548 	pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
549 	pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;
550 	pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;
551 	pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;
552 	pipe_data->pipe_config.vblank_data.vblank_end =
553 			vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
554 
555 	if (vblank_pipe->stream->ignore_msa_timing_param)
556 		populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data);
557 }
558 
559 /**
560  * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case
561  *
562  * @dc: [in] current dc state
563  * @context: [in] new dc state
564  * @cmd: [in] DMUB cmd to be populated with SubVP info
565  * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2)
566  *
567  * For SubVP + SubVP, we use a single vertical interrupt to start the
568  * microschedule for both SubVP pipes. In order for this to work correctly, the
569  * MALL REGION of both SubVP pipes must start at the same time. This function
570  * lengthens the prefetch end to mall start delay of the SubVP pipe that has
571  * the shorter prefetch so that both MALL REGION's will start at the same time.
572  */
573 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
574 		struct dc_state *context,
575 		union dmub_rb_cmd *cmd,
576 		struct pipe_ctx *subvp_pipes[])
577 {
578 	uint32_t subvp0_prefetch_us = 0;
579 	uint32_t subvp1_prefetch_us = 0;
580 	uint32_t prefetch_delta_us = 0;
581 	struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing;
582 	struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing;
583 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
584 
585 	subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
586 			(uint64_t)phantom_timing0->h_total * 1000000),
587 			(((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
588 	subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
589 			(uint64_t)phantom_timing1->h_total * 1000000),
590 			(((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
591 
592 	// Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
593 	// should increase it's prefetch time to match the other
594 	if (subvp0_prefetch_us > subvp1_prefetch_us) {
595 		pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
596 		prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
597 		pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
598 				div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
599 					((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
600 					((uint64_t)phantom_timing1->h_total * 1000000));
601 
602 	} else if (subvp1_prefetch_us >  subvp0_prefetch_us) {
603 		pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
604 		prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
605 		pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
606 				div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
607 					((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
608 					((uint64_t)phantom_timing0->h_total * 1000000));
609 	}
610 }
611 
612 /**
613  * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command
614  *
615  * @dc: [in] current dc state
616  * @context: [in] new dc state
617  * @cmd: [in] DMUB cmd to be populated with SubVP info
618  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
619  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
620  *
621  * Populate the DMCUB SubVP command with SubVP pipe info. All the information
622  * required to calculate the microschedule for the SubVP pipe is stored in the
623  * pipe_data of the DMCUB SubVP command.
624  */
625 static void populate_subvp_cmd_pipe_info(struct dc *dc,
626 		struct dc_state *context,
627 		union dmub_rb_cmd *cmd,
628 		struct pipe_ctx *subvp_pipe,
629 		uint8_t cmd_pipe_index)
630 {
631 	uint32_t j;
632 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
633 			&cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
634 	struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
635 	struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
636 	uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;
637 
638 	pipe_data->mode = SUBVP;
639 	pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
640 	pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;
641 	pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;
642 	pipe_data->pipe_config.subvp_data.main_vblank_start =
643 			main_timing->v_total - main_timing->v_front_porch;
644 	pipe_data->pipe_config.subvp_data.main_vblank_end =
645 			main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
646 	pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
647 	pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;
648 	pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param;
649 
650 	/* Calculate the scaling factor from the src and dst height.
651 	 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.
652 	 * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor"
653 	 *
654 	 * Make sure to combine stream and plane scaling together.
655 	 */
656 	reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height,
657 			&out_num_stream, &out_den_stream);
658 	reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,
659 			&out_num_plane, &out_den_plane);
660 	reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den);
661 	pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
662 	pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
663 
664 	// Prefetch lines is equal to VACTIVE + BP + VSYNC
665 	pipe_data->pipe_config.subvp_data.prefetch_lines =
666 			phantom_timing->v_total - phantom_timing->v_front_porch;
667 
668 	// Round up
669 	pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
670 			div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
671 					((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
672 	pipe_data->pipe_config.subvp_data.processing_delay_lines =
673 			div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
674 					((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
675 
676 	if (subvp_pipe->bottom_pipe) {
677 		pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;
678 	} else if (subvp_pipe->next_odm_pipe) {
679 		pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
680 	} else {
681 		pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0;
682 	}
683 
684 	// Find phantom pipe index based on phantom stream
685 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
686 		struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
687 
688 		if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) {
689 			pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;
690 			if (phantom_pipe->bottom_pipe) {
691 				pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;
692 			} else if (phantom_pipe->next_odm_pipe) {
693 				pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
694 			} else {
695 				pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0;
696 			}
697 			break;
698 		}
699 	}
700 }
701 
702 /**
703  * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command
704  *
705  * @dc: [in] current dc state
706  * @context: [in] new dc state
707  * @enable: [in] if true enables the pipes population
708  *
709  * This function loops through each pipe and populates the DMUB SubVP CMD info
710  * based on the pipe (e.g. SubVP, VBLANK).
711  */
712 void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
713 		struct dc_state *context,
714 		bool enable)
715 {
716 	uint8_t cmd_pipe_index = 0;
717 	uint32_t i, pipe_idx;
718 	uint8_t subvp_count = 0;
719 	union dmub_rb_cmd cmd;
720 	struct pipe_ctx *subvp_pipes[2];
721 	uint32_t wm_val_refclk = 0;
722 
723 	memset(&cmd, 0, sizeof(cmd));
724 	// FW command for SUBVP
725 	cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
726 	cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD;
727 	cmd.fw_assisted_mclk_switch_v2.header.payload_bytes =
728 			sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header);
729 
730 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
731 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
732 
733 		/* For SubVP pipe count, only count the top most (ODM / MPC) pipe
734 		 */
735 		if (resource_is_pipe_type(pipe, OTG_MASTER) &&
736 				resource_is_pipe_type(pipe, DPP_PIPE) &&
737 				pipe->stream->mall_stream_config.type == SUBVP_MAIN)
738 			subvp_pipes[subvp_count++] = pipe;
739 	}
740 
741 	if (enable) {
742 		// For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd
743 		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
744 			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
745 
746 			if (!pipe->stream)
747 				continue;
748 
749 			/* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe.
750 			 * Any ODM or MPC splits being used in SubVP will be handled internally in
751 			 * populate_subvp_cmd_pipe_info
752 			 */
753 			if (resource_is_pipe_type(pipe, OTG_MASTER) &&
754 					resource_is_pipe_type(pipe, DPP_PIPE) &&
755 					pipe->stream->mall_stream_config.paired_stream &&
756 					pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
757 				populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
758 			} else if (resource_is_pipe_type(pipe, OTG_MASTER) &&
759 					resource_is_pipe_type(pipe, DPP_PIPE) &&
760 					pipe->stream->mall_stream_config.type == SUBVP_NONE) {
761 				// Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where
762 				// we run through DML without calculating "natural" P-state support
763 				populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
764 
765 			}
766 			pipe_idx++;
767 		}
768 		if (subvp_count == 2) {
769 			update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);
770 		}
771 		cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
772 		cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;
773 
774 		// Store the original watermark value for this SubVP config so we can lower it when the
775 		// MCLK switch starts
776 		wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
777 				(dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
778 
779 		cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
780 	}
781 
782 	dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
783 }
784 
785 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
786 {
787 	if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
788 		return false;
789 	return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data);
790 }
791 
792 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
793 {
794 	struct dmub_diagnostic_data diag_data = {0};
795 
796 	if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
797 		DC_LOG_ERROR("%s: invalid parameters.", __func__);
798 		return;
799 	}
800 
801 	if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) {
802 		DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);
803 		return;
804 	}
805 
806 	DC_LOG_DEBUG("DMCUB STATE:");
807 	DC_LOG_DEBUG("    dmcub_version      : %08x", diag_data.dmcub_version);
808 	DC_LOG_DEBUG("    scratch  [0]       : %08x", diag_data.scratch[0]);
809 	DC_LOG_DEBUG("    scratch  [1]       : %08x", diag_data.scratch[1]);
810 	DC_LOG_DEBUG("    scratch  [2]       : %08x", diag_data.scratch[2]);
811 	DC_LOG_DEBUG("    scratch  [3]       : %08x", diag_data.scratch[3]);
812 	DC_LOG_DEBUG("    scratch  [4]       : %08x", diag_data.scratch[4]);
813 	DC_LOG_DEBUG("    scratch  [5]       : %08x", diag_data.scratch[5]);
814 	DC_LOG_DEBUG("    scratch  [6]       : %08x", diag_data.scratch[6]);
815 	DC_LOG_DEBUG("    scratch  [7]       : %08x", diag_data.scratch[7]);
816 	DC_LOG_DEBUG("    scratch  [8]       : %08x", diag_data.scratch[8]);
817 	DC_LOG_DEBUG("    scratch  [9]       : %08x", diag_data.scratch[9]);
818 	DC_LOG_DEBUG("    scratch [10]       : %08x", diag_data.scratch[10]);
819 	DC_LOG_DEBUG("    scratch [11]       : %08x", diag_data.scratch[11]);
820 	DC_LOG_DEBUG("    scratch [12]       : %08x", diag_data.scratch[12]);
821 	DC_LOG_DEBUG("    scratch [13]       : %08x", diag_data.scratch[13]);
822 	DC_LOG_DEBUG("    scratch [14]       : %08x", diag_data.scratch[14]);
823 	DC_LOG_DEBUG("    scratch [15]       : %08x", diag_data.scratch[15]);
824 	DC_LOG_DEBUG("    pc                 : %08x", diag_data.pc);
825 	DC_LOG_DEBUG("    unk_fault_addr     : %08x", diag_data.undefined_address_fault_addr);
826 	DC_LOG_DEBUG("    inst_fault_addr    : %08x", diag_data.inst_fetch_fault_addr);
827 	DC_LOG_DEBUG("    data_fault_addr    : %08x", diag_data.data_write_fault_addr);
828 	DC_LOG_DEBUG("    inbox1_rptr        : %08x", diag_data.inbox1_rptr);
829 	DC_LOG_DEBUG("    inbox1_wptr        : %08x", diag_data.inbox1_wptr);
830 	DC_LOG_DEBUG("    inbox1_size        : %08x", diag_data.inbox1_size);
831 	DC_LOG_DEBUG("    inbox0_rptr        : %08x", diag_data.inbox0_rptr);
832 	DC_LOG_DEBUG("    inbox0_wptr        : %08x", diag_data.inbox0_wptr);
833 	DC_LOG_DEBUG("    inbox0_size        : %08x", diag_data.inbox0_size);
834 	DC_LOG_DEBUG("    is_enabled         : %d", diag_data.is_dmcub_enabled);
835 	DC_LOG_DEBUG("    is_soft_reset      : %d", diag_data.is_dmcub_soft_reset);
836 	DC_LOG_DEBUG("    is_secure_reset    : %d", diag_data.is_dmcub_secure_reset);
837 	DC_LOG_DEBUG("    is_traceport_en    : %d", diag_data.is_traceport_en);
838 	DC_LOG_DEBUG("    is_cw0_en          : %d", diag_data.is_cw0_enabled);
839 	DC_LOG_DEBUG("    is_cw6_en          : %d", diag_data.is_cw6_enabled);
840 }
841 
842 static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
843 {
844 	struct pipe_ctx *test_pipe, *split_pipe;
845 	const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data;
846 	struct rect r1 = scl_data->recout, r2, r2_half;
847 	int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b;
848 	int cur_layer = pipe_ctx->plane_state->layer_index;
849 
850 	/**
851 	 * Disable the cursor if there's another pipe above this with a
852 	 * plane that contains this pipe's viewport to prevent double cursor
853 	 * and incorrect scaling artifacts.
854 	 */
855 	for (test_pipe = pipe_ctx->top_pipe; test_pipe;
856 	     test_pipe = test_pipe->top_pipe) {
857 		// Skip invisible layer and pipe-split plane on same layer
858 		if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer)
859 			continue;
860 
861 		r2 = test_pipe->plane_res.scl_data.recout;
862 		r2_r = r2.x + r2.width;
863 		r2_b = r2.y + r2.height;
864 		split_pipe = test_pipe;
865 
866 		/**
867 		 * There is another half plane on same layer because of
868 		 * pipe-split, merge together per same height.
869 		 */
870 		for (split_pipe = pipe_ctx->top_pipe; split_pipe;
871 		     split_pipe = split_pipe->top_pipe)
872 			if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {
873 				r2_half = split_pipe->plane_res.scl_data.recout;
874 				r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x;
875 				r2.width = r2.width + r2_half.width;
876 				r2_r = r2.x + r2.width;
877 				break;
878 			}
879 
880 		if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b)
881 			return true;
882 	}
883 
884 	return false;
885 }
886 
887 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)
888 {
889 	if (pipe_ctx->plane_state != NULL) {
890 		if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
891 			return false;
892 
893 		if (dc_can_pipe_disable_cursor(pipe_ctx))
894 			return false;
895 	}
896 
897 	if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
898 		pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&
899 		pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)
900 		return true;
901 
902 	if (pipe_ctx->stream->link->replay_settings.config.replay_supported)
903 		return true;
904 
905 	return false;
906 }
907 
908 static void dc_build_cursor_update_payload0(
909 		struct pipe_ctx *pipe_ctx, uint8_t p_idx,
910 		struct dmub_cmd_update_cursor_payload0 *payload)
911 {
912 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
913 	unsigned int panel_inst = 0;
914 
915 	if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
916 		pipe_ctx->stream->link, &panel_inst))
917 		return;
918 
919 	/* Payload: Cursor Rect is built from position & attribute
920 	 * x & y are obtained from postion
921 	 */
922 	payload->cursor_rect.x = hubp->cur_rect.x;
923 	payload->cursor_rect.y = hubp->cur_rect.y;
924 	/* w & h are obtained from attribute */
925 	payload->cursor_rect.width  = hubp->cur_rect.w;
926 	payload->cursor_rect.height = hubp->cur_rect.h;
927 
928 	payload->enable      = hubp->pos.cur_ctl.bits.cur_enable;
929 	payload->pipe_idx    = p_idx;
930 	payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
931 	payload->panel_inst  = panel_inst;
932 }
933 
934 static void dc_build_cursor_position_update_payload0(
935 		struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx,
936 		const struct hubp *hubp, const struct dpp *dpp)
937 {
938 	/* Hubp */
939 	pl->position_cfg.pHubp.cur_ctl.raw  = hubp->pos.cur_ctl.raw;
940 	pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;
941 	pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;
942 	pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;
943 
944 	/* dpp */
945 	pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;
946 	pl->position_cfg.pipe_idx = p_idx;
947 }
948 
949 static void dc_build_cursor_attribute_update_payload1(
950 		struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx,
951 		const struct hubp *hubp, const struct dpp *dpp)
952 {
953 	/* Hubp */
954 	pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;
955 	pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;
956 	pl_A->aHubp.cur_ctl.raw  = hubp->att.cur_ctl.raw;
957 	pl_A->aHubp.size.raw     = hubp->att.size.raw;
958 	pl_A->aHubp.settings.raw = hubp->att.settings.raw;
959 
960 	/* dpp */
961 	pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;
962 }
963 
964 /**
965  * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command
966  *
967  * @pCtx: [in] pipe context
968  * @pipe_idx: [in] pipe index
969  *
970  * This function would store the cursor related information and pass it into
971  * dmub
972  */
973 void dc_send_update_cursor_info_to_dmu(
974 		struct pipe_ctx *pCtx, uint8_t pipe_idx)
975 {
976 	union dmub_rb_cmd cmd[2];
977 	union dmub_cmd_update_cursor_info_data *update_cursor_info_0 =
978 					&cmd[0].update_cursor_info.update_cursor_info_data;
979 
980 	memset(cmd, 0, sizeof(cmd));
981 
982 	if (!dc_dmub_should_update_cursor_data(pCtx))
983 		return;
984 	/*
985 	 * Since we use multi_cmd_pending for dmub command, the 2nd command is
986 	 * only assigned to store cursor attributes info.
987 	 * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other
988 	 * is to store cursor position info.
989 	 *
990 	 * Command heaer type must be the same type if using  multi_cmd_pending.
991 	 * Besides, while process 2nd command in DMU, the sub type is useless.
992 	 * So it's meanless to pass the sub type header with different type.
993 	 */
994 
995 	{
996 		/* Build Payload#0 Header */
997 		cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
998 		cmd[0].update_cursor_info.header.payload_bytes =
999 				sizeof(cmd[0].update_cursor_info.update_cursor_info_data);
1000 		cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd
1001 
1002 		/* Prepare Payload */
1003 		dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info_0->payload0);
1004 
1005 		dc_build_cursor_position_update_payload0(&update_cursor_info_0->payload0, pipe_idx,
1006 				pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1007 		}
1008 	{
1009 		/* Build Payload#1 Header */
1010 		cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1011 		cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg);
1012 		cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command.
1013 
1014 		dc_build_cursor_attribute_update_payload1(
1015 				&cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg,
1016 				pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1017 
1018 		/* Combine 2nd cmds update_curosr_info to DMU */
1019 		dm_execute_dmub_cmd_list(pCtx->stream->ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT);
1020 	}
1021 }
1022 
1023 bool dc_dmub_check_min_version(struct dmub_srv *srv)
1024 {
1025 	if (!srv->hw_funcs.is_psrsu_supported)
1026 		return true;
1027 	return srv->hw_funcs.is_psrsu_supported(srv);
1028 }
1029 
1030 void dc_dmub_srv_enable_dpia_trace(const struct dc *dc)
1031 {
1032 	struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;
1033 	struct dmub_srv *dmub;
1034 	enum dmub_status status;
1035 	static const uint32_t timeout_us = 30;
1036 
1037 	if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
1038 		DC_LOG_ERROR("%s: invalid parameters.", __func__);
1039 		return;
1040 	}
1041 
1042 	dmub = dc_dmub_srv->dmub;
1043 
1044 	status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1, 0x0010, timeout_us);
1045 	if (status != DMUB_STATUS_OK) {
1046 		DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1047 		return;
1048 	}
1049 
1050 	status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK, 0x0000, timeout_us);
1051 	if (status != DMUB_STATUS_OK) {
1052 		DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1053 		return;
1054 	}
1055 
1056 	DC_LOG_DEBUG("Enabled DPIA trace\n");
1057 }