1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc.h" 27 #include "dc_dmub_srv.h" 28 #include "../dmub/dmub_srv.h" 29 #include "dm_helpers.h" 30 #include "dc_hw_types.h" 31 #include "core_types.h" 32 #include "../basics/conversion.h" 33 #include "cursor_reg_cache.h" 34 35 #define CTX dc_dmub_srv->ctx 36 #define DC_LOGGER CTX->logger 37 38 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, 39 struct dmub_srv *dmub) 40 { 41 dc_srv->dmub = dmub; 42 dc_srv->ctx = dc->ctx; 43 } 44 45 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) 46 { 47 struct dc_dmub_srv *dc_srv = 48 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL); 49 50 if (dc_srv == NULL) { 51 BREAK_TO_DEBUGGER(); 52 return NULL; 53 } 54 55 dc_dmub_srv_construct(dc_srv, dc, dmub); 56 57 return dc_srv; 58 } 59 60 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv) 61 { 62 if (*dmub_srv) { 63 kfree(*dmub_srv); 64 *dmub_srv = NULL; 65 } 66 } 67 68 void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv, 69 union dmub_rb_cmd *cmd) 70 { 71 struct dmub_srv *dmub = dc_dmub_srv->dmub; 72 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 73 enum dmub_status status; 74 75 status = dmub_srv_cmd_queue(dmub, cmd); 76 if (status == DMUB_STATUS_OK) 77 return; 78 79 if (status != DMUB_STATUS_QUEUE_FULL) 80 goto error; 81 82 /* Execute and wait for queue to become empty again. */ 83 dc_dmub_srv_cmd_execute(dc_dmub_srv); 84 dc_dmub_srv_wait_idle(dc_dmub_srv); 85 86 /* Requeue the command. */ 87 status = dmub_srv_cmd_queue(dmub, cmd); 88 if (status == DMUB_STATUS_OK) 89 return; 90 91 error: 92 DC_ERROR("Error queuing DMUB command: status=%d\n", status); 93 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 94 } 95 96 void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv) 97 { 98 struct dmub_srv *dmub = dc_dmub_srv->dmub; 99 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 100 enum dmub_status status; 101 102 status = dmub_srv_cmd_execute(dmub); 103 if (status != DMUB_STATUS_OK) { 104 DC_ERROR("Error starting DMUB execution: status=%d\n", status); 105 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 106 } 107 } 108 109 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) 110 { 111 struct dmub_srv *dmub = dc_dmub_srv->dmub; 112 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 113 enum dmub_status status; 114 115 status = dmub_srv_wait_for_idle(dmub, 100000); 116 if (status != DMUB_STATUS_OK) { 117 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); 118 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 119 } 120 } 121 122 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv) 123 { 124 struct dmub_srv *dmub = dmub_srv->dmub; 125 struct dc_context *dc_ctx = dmub_srv->ctx; 126 enum dmub_status status = DMUB_STATUS_OK; 127 128 status = dmub_srv_clear_inbox0_ack(dmub); 129 if (status != DMUB_STATUS_OK) { 130 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status); 131 dc_dmub_srv_log_diagnostic_data(dmub_srv); 132 } 133 } 134 135 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv) 136 { 137 struct dmub_srv *dmub = dmub_srv->dmub; 138 struct dc_context *dc_ctx = dmub_srv->ctx; 139 enum dmub_status status = DMUB_STATUS_OK; 140 141 status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); 142 if (status != DMUB_STATUS_OK) { 143 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n"); 144 dc_dmub_srv_log_diagnostic_data(dmub_srv); 145 } 146 } 147 148 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, 149 union dmub_inbox0_data_register data) 150 { 151 struct dmub_srv *dmub = dmub_srv->dmub; 152 struct dc_context *dc_ctx = dmub_srv->ctx; 153 enum dmub_status status = DMUB_STATUS_OK; 154 155 status = dmub_srv_send_inbox0_cmd(dmub, data); 156 if (status != DMUB_STATUS_OK) { 157 DC_ERROR("Error sending INBOX0 cmd\n"); 158 dc_dmub_srv_log_diagnostic_data(dmub_srv); 159 } 160 } 161 162 bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd) 163 { 164 struct dmub_srv *dmub; 165 enum dmub_status status; 166 167 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 168 return false; 169 170 dmub = dc_dmub_srv->dmub; 171 172 status = dmub_srv_cmd_with_reply_data(dmub, cmd); 173 if (status != DMUB_STATUS_OK) { 174 DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 175 return false; 176 } 177 178 return true; 179 } 180 181 void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv) 182 { 183 struct dmub_srv *dmub = dc_dmub_srv->dmub; 184 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 185 enum dmub_status status; 186 187 for (;;) { 188 /* Wait up to a second for PHY init. */ 189 status = dmub_srv_wait_for_phy_init(dmub, 1000000); 190 if (status == DMUB_STATUS_OK) 191 /* Initialization OK */ 192 break; 193 194 DC_ERROR("DMCUB PHY init failed: status=%d\n", status); 195 ASSERT(0); 196 197 if (status != DMUB_STATUS_TIMEOUT) 198 /* 199 * Server likely initialized or we don't have 200 * DMCUB HW support - this won't end. 201 */ 202 break; 203 204 /* Continue spinning so we don't hang the ASIC. */ 205 } 206 } 207 208 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 209 unsigned int stream_mask) 210 { 211 struct dmub_srv *dmub; 212 const uint32_t timeout = 30; 213 214 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 215 return false; 216 217 dmub = dc_dmub_srv->dmub; 218 219 return dmub_srv_send_gpint_command( 220 dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, 221 stream_mask, timeout) == DMUB_STATUS_OK; 222 } 223 224 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) 225 { 226 struct dmub_srv *dmub; 227 struct dc_context *dc_ctx; 228 union dmub_fw_boot_status boot_status; 229 enum dmub_status status; 230 231 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 232 return false; 233 234 dmub = dc_dmub_srv->dmub; 235 dc_ctx = dc_dmub_srv->ctx; 236 237 status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 238 if (status != DMUB_STATUS_OK) { 239 DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 240 return false; 241 } 242 243 return boot_status.bits.restore_required; 244 } 245 246 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) 247 { 248 struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; 249 return dmub_srv_get_outbox0_msg(dmub, entry); 250 } 251 252 void dc_dmub_trace_event_control(struct dc *dc, bool enable) 253 { 254 dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); 255 } 256 257 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) 258 { 259 union dmub_rb_cmd cmd = { 0 }; 260 261 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 262 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE; 263 cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 264 cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 265 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 266 267 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 268 269 // Send the command to the DMCUB. 270 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 271 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 272 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 273 } 274 275 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) 276 { 277 union dmub_rb_cmd cmd = { 0 }; 278 279 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 280 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER; 281 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 282 283 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 284 285 // Send the command to the DMCUB. 286 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 287 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 288 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 289 } 290 291 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) 292 { 293 uint8_t pipes = 0; 294 int i = 0; 295 296 for (i = 0; i < MAX_PIPES; i++) { 297 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 298 299 if (pipe->stream == stream && pipe->stream_res.tg) 300 pipes = i; 301 } 302 return pipes; 303 } 304 305 static int dc_dmub_srv_get_timing_generator_offset(struct dc *dc, struct dc_stream_state *stream) 306 { 307 int tg_inst = 0; 308 int i = 0; 309 310 for (i = 0; i < MAX_PIPES; i++) { 311 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 312 313 if (pipe->stream == stream && pipe->stream_res.tg) { 314 tg_inst = pipe->stream_res.tg->inst; 315 break; 316 } 317 } 318 return tg_inst; 319 } 320 321 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) 322 { 323 union dmub_rb_cmd cmd = { 0 }; 324 struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; 325 int i = 0; 326 int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. 327 uint8_t visual_confirm_enabled; 328 329 if (dc == NULL) 330 return false; 331 332 visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; 333 334 // Format command. 335 cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 336 cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL; 337 cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate; 338 cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; 339 340 for (i = 0; context && i < context->stream_count; i++) { 341 struct dc_stream_state *stream = context->streams[i]; 342 uint8_t min_refresh_in_hz = (stream->timing.min_refresh_in_uhz + 999999) / 1000000; 343 int tg_inst = dc_dmub_srv_get_timing_generator_offset(dc, stream); 344 345 config_data->pipe_data[tg_inst].pix_clk_100hz = stream->timing.pix_clk_100hz; 346 config_data->pipe_data[tg_inst].min_refresh_in_hz = min_refresh_in_hz; 347 config_data->pipe_data[tg_inst].max_ramp_step = ramp_up_num_steps; 348 config_data->pipe_data[tg_inst].pipes = dc_dmub_srv_get_pipes_for_stream(dc, stream); 349 } 350 351 cmd.fw_assisted_mclk_switch.header.payload_bytes = 352 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header); 353 354 // Send the command to the DMCUB. 355 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 356 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 357 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 358 359 return true; 360 } 361 362 void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub) 363 { 364 union dmub_rb_cmd cmd = { 0 }; 365 enum dmub_status status; 366 367 if (!dmub) { 368 return; 369 } 370 371 memset(&cmd, 0, sizeof(cmd)); 372 373 /* Prepare fw command */ 374 cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; 375 cmd.query_feature_caps.header.sub_type = 0; 376 cmd.query_feature_caps.header.ret_status = 1; 377 cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); 378 379 /* Send command to fw */ 380 status = dmub_srv_cmd_with_reply_data(dmub, &cmd); 381 382 ASSERT(status == DMUB_STATUS_OK); 383 384 /* If command was processed, copy feature caps to dmub srv */ 385 if (status == DMUB_STATUS_OK && 386 cmd.query_feature_caps.header.ret_status == 0) { 387 memcpy(&dmub->feature_caps, 388 &cmd.query_feature_caps.query_feature_caps_data, 389 sizeof(struct dmub_feature_caps)); 390 } 391 } 392 393 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx) 394 { 395 union dmub_rb_cmd cmd = { 0 }; 396 enum dmub_status status; 397 unsigned int panel_inst = 0; 398 399 dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst); 400 401 memset(&cmd, 0, sizeof(cmd)); 402 403 // Prepare fw command 404 cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR; 405 cmd.visual_confirm_color.header.sub_type = 0; 406 cmd.visual_confirm_color.header.ret_status = 1; 407 cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data); 408 cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst; 409 410 // Send command to fw 411 status = dmub_srv_cmd_with_reply_data(dc->ctx->dmub_srv->dmub, &cmd); 412 413 ASSERT(status == DMUB_STATUS_OK); 414 415 // If command was processed, copy feature caps to dmub srv 416 if (status == DMUB_STATUS_OK && 417 cmd.visual_confirm_color.header.ret_status == 0) { 418 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color, 419 &cmd.visual_confirm_color.visual_confirm_color_data, 420 sizeof(struct dmub_visual_confirm_color)); 421 } 422 } 423 424 #ifdef CONFIG_DRM_AMD_DC_DCN 425 /** 426 * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command 427 * 428 * @dc: [in] current dc state 429 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 430 * @vblank_pipe: [in] pipe_ctx for the DRR pipe 431 * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info 432 * 433 * Populate the DMCUB SubVP command with DRR pipe info. All the information 434 * required for calculating the SubVP + DRR microschedule is populated here. 435 * 436 * High level algorithm: 437 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 438 * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule 439 * 3. Populate the drr_info with the min and max supported vtotal values 440 */ 441 static void populate_subvp_cmd_drr_info(struct dc *dc, 442 struct pipe_ctx *subvp_pipe, 443 struct pipe_ctx *vblank_pipe, 444 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data) 445 { 446 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 447 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 448 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 449 uint16_t drr_frame_us = 0; 450 uint16_t min_drr_supported_us = 0; 451 uint16_t max_drr_supported_us = 0; 452 uint16_t max_drr_vblank_us = 0; 453 uint16_t max_drr_mallregion_us = 0; 454 uint16_t mall_region_us = 0; 455 uint16_t prefetch_us = 0; 456 uint16_t subvp_active_us = 0; 457 uint16_t drr_active_us = 0; 458 uint16_t min_vtotal_supported = 0; 459 uint16_t max_vtotal_supported = 0; 460 461 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; 462 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping 463 pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now 464 465 drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000), 466 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 467 // P-State allow width and FW delays already included phantom_timing->v_addressable 468 mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000), 469 (((uint64_t)phantom_timing->pix_clk_100hz * 100))); 470 min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 471 min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us), 472 (((uint64_t)drr_timing->h_total * 1000000))); 473 474 prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000), 475 (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 476 subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000), 477 (((uint64_t)main_timing->pix_clk_100hz * 100))); 478 drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000), 479 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 480 max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - drr_active_us), 2) + drr_active_us; 481 max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us; 482 max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; 483 max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us), 484 (((uint64_t)drr_timing->h_total * 1000000))); 485 486 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; 487 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; 488 } 489 490 /** 491 * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command 492 * 493 * @dc: [in] current dc state 494 * @context: [in] new dc state 495 * @cmd: [in] DMUB cmd to be populated with SubVP info 496 * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe 497 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 498 * 499 * Populate the DMCUB SubVP command with VBLANK pipe info. All the information 500 * required to calculate the microschedule for SubVP + VBLANK case is stored in 501 * the pipe_data (subvp_data and vblank_data). Also check if the VBLANK pipe 502 * is a DRR display -- if it is make a call to populate drr_info. 503 */ 504 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, 505 struct dc_state *context, 506 union dmub_rb_cmd *cmd, 507 struct pipe_ctx *vblank_pipe, 508 uint8_t cmd_pipe_index) 509 { 510 uint32_t i; 511 struct pipe_ctx *pipe = NULL; 512 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 513 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 514 515 // Find the SubVP pipe 516 for (i = 0; i < dc->res_pool->pipe_count; i++) { 517 pipe = &context->res_ctx.pipe_ctx[i]; 518 519 // We check for master pipe, but it shouldn't matter since we only need 520 // the pipe for timing info (stream should be same for any pipe splits) 521 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 522 continue; 523 524 // Find the SubVP pipe 525 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 526 break; 527 } 528 529 pipe_data->mode = VBLANK; 530 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; 531 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - 532 vblank_pipe->stream->timing.v_front_porch; 533 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; 534 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; 535 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; 536 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; 537 pipe_data->pipe_config.vblank_data.vblank_end = 538 vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; 539 540 if (vblank_pipe->stream->ignore_msa_timing_param) 541 populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data); 542 } 543 544 /** 545 * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case 546 * 547 * @dc: [in] current dc state 548 * @context: [in] new dc state 549 * @cmd: [in] DMUB cmd to be populated with SubVP info 550 * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2) 551 * 552 * For SubVP + SubVP, we use a single vertical interrupt to start the 553 * microschedule for both SubVP pipes. In order for this to work correctly, the 554 * MALL REGION of both SubVP pipes must start at the same time. This function 555 * lengthens the prefetch end to mall start delay of the SubVP pipe that has 556 * the shorter prefetch so that both MALL REGION's will start at the same time. 557 */ 558 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, 559 struct dc_state *context, 560 union dmub_rb_cmd *cmd, 561 struct pipe_ctx *subvp_pipes[]) 562 { 563 uint32_t subvp0_prefetch_us = 0; 564 uint32_t subvp1_prefetch_us = 0; 565 uint32_t prefetch_delta_us = 0; 566 struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing; 567 struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing; 568 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL; 569 570 subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * 571 (uint64_t)phantom_timing0->h_total * 1000000), 572 (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 573 subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * 574 (uint64_t)phantom_timing1->h_total * 1000000), 575 (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 576 577 // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) 578 // should increase it's prefetch time to match the other 579 if (subvp0_prefetch_us > subvp1_prefetch_us) { 580 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; 581 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; 582 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 583 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 584 ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), 585 ((uint64_t)phantom_timing1->h_total * 1000000)); 586 587 } else if (subvp1_prefetch_us > subvp0_prefetch_us) { 588 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; 589 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; 590 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 591 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 592 ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), 593 ((uint64_t)phantom_timing0->h_total * 1000000)); 594 } 595 } 596 597 /** 598 * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command 599 * 600 * @dc: [in] current dc state 601 * @context: [in] new dc state 602 * @cmd: [in] DMUB cmd to be populated with SubVP info 603 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 604 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 605 * 606 * Populate the DMCUB SubVP command with SubVP pipe info. All the information 607 * required to calculate the microschedule for the SubVP pipe is stored in the 608 * pipe_data of the DMCUB SubVP command. 609 */ 610 static void populate_subvp_cmd_pipe_info(struct dc *dc, 611 struct dc_state *context, 612 union dmub_rb_cmd *cmd, 613 struct pipe_ctx *subvp_pipe, 614 uint8_t cmd_pipe_index) 615 { 616 uint32_t j; 617 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 618 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 619 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 620 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 621 uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den; 622 623 pipe_data->mode = SUBVP; 624 pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; 625 pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; 626 pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; 627 pipe_data->pipe_config.subvp_data.main_vblank_start = 628 main_timing->v_total - main_timing->v_front_porch; 629 pipe_data->pipe_config.subvp_data.main_vblank_end = 630 main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; 631 pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; 632 pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->pipe_idx; 633 pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param; 634 635 /* Calculate the scaling factor from the src and dst height. 636 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2. 637 * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor" 638 * 639 * Make sure to combine stream and plane scaling together. 640 */ 641 reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height, 642 &out_num_stream, &out_den_stream); 643 reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height, 644 &out_num_plane, &out_den_plane); 645 reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den); 646 pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num; 647 pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den; 648 649 // Prefetch lines is equal to VACTIVE + BP + VSYNC 650 pipe_data->pipe_config.subvp_data.prefetch_lines = 651 phantom_timing->v_total - phantom_timing->v_front_porch; 652 653 // Round up 654 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 655 div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 656 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 657 pipe_data->pipe_config.subvp_data.processing_delay_lines = 658 div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 659 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 660 661 if (subvp_pipe->bottom_pipe) { 662 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; 663 } else if (subvp_pipe->next_odm_pipe) { 664 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; 665 } else { 666 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0; 667 } 668 669 // Find phantom pipe index based on phantom stream 670 for (j = 0; j < dc->res_pool->pipe_count; j++) { 671 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; 672 673 if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) { 674 pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->pipe_idx; 675 if (phantom_pipe->bottom_pipe) { 676 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->pipe_idx; 677 } else if (phantom_pipe->next_odm_pipe) { 678 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->pipe_idx; 679 } else { 680 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0; 681 } 682 break; 683 } 684 } 685 } 686 687 /** 688 * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command 689 * 690 * @dc: [in] current dc state 691 * @context: [in] new dc state 692 * @cmd: [in] DMUB cmd to be populated with SubVP info 693 * 694 * This function loops through each pipe and populates the DMUB SubVP CMD info 695 * based on the pipe (e.g. SubVP, VBLANK). 696 */ 697 void dc_dmub_setup_subvp_dmub_command(struct dc *dc, 698 struct dc_state *context, 699 bool enable) 700 { 701 uint8_t cmd_pipe_index = 0; 702 uint32_t i, pipe_idx; 703 uint8_t subvp_count = 0; 704 union dmub_rb_cmd cmd; 705 struct pipe_ctx *subvp_pipes[2]; 706 uint32_t wm_val_refclk = 0; 707 708 memset(&cmd, 0, sizeof(cmd)); 709 // FW command for SUBVP 710 cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 711 cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD; 712 cmd.fw_assisted_mclk_switch_v2.header.payload_bytes = 713 sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header); 714 715 for (i = 0; i < dc->res_pool->pipe_count; i++) { 716 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 717 718 if (!pipe->stream) 719 continue; 720 721 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe 722 */ 723 if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && 724 pipe->stream->mall_stream_config.type == SUBVP_MAIN) 725 subvp_pipes[subvp_count++] = pipe; 726 } 727 728 if (enable) { 729 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd 730 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 731 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 732 733 if (!pipe->stream) 734 continue; 735 736 /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe. 737 * Any ODM or MPC splits being used in SubVP will be handled internally in 738 * populate_subvp_cmd_pipe_info 739 */ 740 if (pipe->plane_state && pipe->stream->mall_stream_config.paired_stream && 741 !pipe->top_pipe && !pipe->prev_odm_pipe && 742 pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 743 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 744 } else if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_NONE) { 745 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where 746 // we run through DML without calculating "natural" P-state support 747 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 748 749 } 750 pipe_idx++; 751 } 752 if (subvp_count == 2) { 753 update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); 754 } 755 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 756 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; 757 758 // Store the original watermark value for this SubVP config so we can lower it when the 759 // MCLK switch starts 760 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * 761 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; 762 763 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; 764 } 765 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 766 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 767 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 768 } 769 #endif 770 771 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) 772 { 773 if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) 774 return false; 775 return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data); 776 } 777 778 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 779 { 780 struct dmub_diagnostic_data diag_data = {0}; 781 782 if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 783 DC_LOG_ERROR("%s: invalid parameters.", __func__); 784 return; 785 } 786 787 if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) { 788 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); 789 return; 790 } 791 792 DC_LOG_DEBUG( 793 "DMCUB STATE\n" 794 " dmcub_version : %08x\n" 795 " scratch [0] : %08x\n" 796 " scratch [1] : %08x\n" 797 " scratch [2] : %08x\n" 798 " scratch [3] : %08x\n" 799 " scratch [4] : %08x\n" 800 " scratch [5] : %08x\n" 801 " scratch [6] : %08x\n" 802 " scratch [7] : %08x\n" 803 " scratch [8] : %08x\n" 804 " scratch [9] : %08x\n" 805 " scratch [10] : %08x\n" 806 " scratch [11] : %08x\n" 807 " scratch [12] : %08x\n" 808 " scratch [13] : %08x\n" 809 " scratch [14] : %08x\n" 810 " scratch [15] : %08x\n" 811 " pc : %08x\n" 812 " unk_fault_addr : %08x\n" 813 " inst_fault_addr : %08x\n" 814 " data_fault_addr : %08x\n" 815 " inbox1_rptr : %08x\n" 816 " inbox1_wptr : %08x\n" 817 " inbox1_size : %08x\n" 818 " inbox0_rptr : %08x\n" 819 " inbox0_wptr : %08x\n" 820 " inbox0_size : %08x\n" 821 " is_enabled : %d\n" 822 " is_soft_reset : %d\n" 823 " is_secure_reset : %d\n" 824 " is_traceport_en : %d\n" 825 " is_cw0_en : %d\n" 826 " is_cw6_en : %d\n", 827 diag_data.dmcub_version, 828 diag_data.scratch[0], 829 diag_data.scratch[1], 830 diag_data.scratch[2], 831 diag_data.scratch[3], 832 diag_data.scratch[4], 833 diag_data.scratch[5], 834 diag_data.scratch[6], 835 diag_data.scratch[7], 836 diag_data.scratch[8], 837 diag_data.scratch[9], 838 diag_data.scratch[10], 839 diag_data.scratch[11], 840 diag_data.scratch[12], 841 diag_data.scratch[13], 842 diag_data.scratch[14], 843 diag_data.scratch[15], 844 diag_data.pc, 845 diag_data.undefined_address_fault_addr, 846 diag_data.inst_fetch_fault_addr, 847 diag_data.data_write_fault_addr, 848 diag_data.inbox1_rptr, 849 diag_data.inbox1_wptr, 850 diag_data.inbox1_size, 851 diag_data.inbox0_rptr, 852 diag_data.inbox0_wptr, 853 diag_data.inbox0_size, 854 diag_data.is_dmcub_enabled, 855 diag_data.is_dmcub_soft_reset, 856 diag_data.is_dmcub_secure_reset, 857 diag_data.is_traceport_en, 858 diag_data.is_cw0_enabled, 859 diag_data.is_cw6_enabled); 860 } 861 862 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx) 863 { 864 if (pipe_ctx->plane_state != NULL) { 865 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 866 return false; 867 } 868 869 if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || 870 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) && 871 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1) 872 return true; 873 874 return false; 875 } 876 877 static void dc_build_cursor_update_payload0( 878 struct pipe_ctx *pipe_ctx, uint8_t p_idx, 879 struct dmub_cmd_update_cursor_payload0 *payload) 880 { 881 struct hubp *hubp = pipe_ctx->plane_res.hubp; 882 unsigned int panel_inst = 0; 883 884 if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, 885 pipe_ctx->stream->link, &panel_inst)) 886 return; 887 888 /* Payload: Cursor Rect is built from position & attribute 889 * x & y are obtained from postion 890 */ 891 payload->cursor_rect.x = hubp->cur_rect.x; 892 payload->cursor_rect.y = hubp->cur_rect.y; 893 /* w & h are obtained from attribute */ 894 payload->cursor_rect.width = hubp->cur_rect.w; 895 payload->cursor_rect.height = hubp->cur_rect.h; 896 897 payload->enable = hubp->pos.cur_ctl.bits.cur_enable; 898 payload->pipe_idx = p_idx; 899 payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 900 payload->panel_inst = panel_inst; 901 } 902 903 static void dc_send_cmd_to_dmu(struct dc_dmub_srv *dmub_srv, 904 union dmub_rb_cmd *cmd) 905 { 906 dc_dmub_srv_cmd_queue(dmub_srv, cmd); 907 dc_dmub_srv_cmd_execute(dmub_srv); 908 dc_dmub_srv_wait_idle(dmub_srv); 909 } 910 911 static void dc_build_cursor_position_update_payload0( 912 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx, 913 const struct hubp *hubp, const struct dpp *dpp) 914 { 915 /* Hubp */ 916 pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw; 917 pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw; 918 pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw; 919 pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw; 920 921 /* dpp */ 922 pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw; 923 pl->position_cfg.pipe_idx = p_idx; 924 } 925 926 static void dc_build_cursor_attribute_update_payload1( 927 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx, 928 const struct hubp *hubp, const struct dpp *dpp) 929 { 930 /* Hubp */ 931 pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH; 932 pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR; 933 pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw; 934 pl_A->aHubp.size.raw = hubp->att.size.raw; 935 pl_A->aHubp.settings.raw = hubp->att.settings.raw; 936 937 /* dpp */ 938 pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw; 939 } 940 941 /** 942 * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command 943 * 944 * @pCtx: [in] pipe context 945 * @pipe_idx: [in] pipe index 946 * 947 * This function would store the cursor related information and pass it into 948 * dmub 949 */ 950 void dc_send_update_cursor_info_to_dmu( 951 struct pipe_ctx *pCtx, uint8_t pipe_idx) 952 { 953 union dmub_rb_cmd cmd = { 0 }; 954 union dmub_cmd_update_cursor_info_data *update_cursor_info = 955 &cmd.update_cursor_info.update_cursor_info_data; 956 957 if (!dc_dmub_should_update_cursor_data(pCtx)) 958 return; 959 /* 960 * Since we use multi_cmd_pending for dmub command, the 2nd command is 961 * only assigned to store cursor attributes info. 962 * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other 963 * is to store cursor position info. 964 * 965 * Command heaer type must be the same type if using multi_cmd_pending. 966 * Besides, while process 2nd command in DMU, the sub type is useless. 967 * So it's meanless to pass the sub type header with different type. 968 */ 969 970 { 971 /* Build Payload#0 Header */ 972 cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 973 cmd.update_cursor_info.header.payload_bytes = 974 sizeof(cmd.update_cursor_info.update_cursor_info_data); 975 cmd.update_cursor_info.header.multi_cmd_pending = 1; /* To combine multi dmu cmd, 1st cmd */ 976 977 /* Prepare Payload */ 978 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info->payload0); 979 980 dc_build_cursor_position_update_payload0(&update_cursor_info->payload0, pipe_idx, 981 pCtx->plane_res.hubp, pCtx->plane_res.dpp); 982 /* Send update_curosr_info to queue */ 983 dc_dmub_srv_cmd_queue(pCtx->stream->ctx->dmub_srv, &cmd); 984 } 985 { 986 /* Build Payload#1 Header */ 987 memset(update_cursor_info, 0, sizeof(union dmub_cmd_update_cursor_info_data)); 988 cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 989 cmd.update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg); 990 cmd.update_cursor_info.header.multi_cmd_pending = 0; /* Indicate it's the last command. */ 991 992 dc_build_cursor_attribute_update_payload1( 993 &cmd.update_cursor_info.update_cursor_info_data.payload1.attribute_cfg, 994 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); 995 996 /* Combine 2nd cmds update_curosr_info to DMU */ 997 dc_send_cmd_to_dmu(pCtx->stream->ctx->dmub_srv, &cmd); 998 } 999 } 1000