1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc.h" 27 #include "dc_dmub_srv.h" 28 #include "../dmub/dmub_srv.h" 29 #include "dm_helpers.h" 30 #include "dc_hw_types.h" 31 #include "core_types.h" 32 33 #define CTX dc_dmub_srv->ctx 34 #define DC_LOGGER CTX->logger 35 36 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, 37 struct dmub_srv *dmub) 38 { 39 dc_srv->dmub = dmub; 40 dc_srv->ctx = dc->ctx; 41 } 42 43 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) 44 { 45 struct dc_dmub_srv *dc_srv = 46 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL); 47 48 if (dc_srv == NULL) { 49 BREAK_TO_DEBUGGER(); 50 return NULL; 51 } 52 53 dc_dmub_srv_construct(dc_srv, dc, dmub); 54 55 return dc_srv; 56 } 57 58 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv) 59 { 60 if (*dmub_srv) { 61 kfree(*dmub_srv); 62 *dmub_srv = NULL; 63 } 64 } 65 66 void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv, 67 union dmub_rb_cmd *cmd) 68 { 69 struct dmub_srv *dmub = dc_dmub_srv->dmub; 70 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 71 enum dmub_status status; 72 73 status = dmub_srv_cmd_queue(dmub, cmd); 74 if (status == DMUB_STATUS_OK) 75 return; 76 77 if (status != DMUB_STATUS_QUEUE_FULL) 78 goto error; 79 80 /* Execute and wait for queue to become empty again. */ 81 dc_dmub_srv_cmd_execute(dc_dmub_srv); 82 dc_dmub_srv_wait_idle(dc_dmub_srv); 83 84 /* Requeue the command. */ 85 status = dmub_srv_cmd_queue(dmub, cmd); 86 if (status == DMUB_STATUS_OK) 87 return; 88 89 error: 90 DC_ERROR("Error queuing DMUB command: status=%d\n", status); 91 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 92 } 93 94 void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv) 95 { 96 struct dmub_srv *dmub = dc_dmub_srv->dmub; 97 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 98 enum dmub_status status; 99 100 status = dmub_srv_cmd_execute(dmub); 101 if (status != DMUB_STATUS_OK) { 102 DC_ERROR("Error starting DMUB execution: status=%d\n", status); 103 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 104 } 105 } 106 107 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) 108 { 109 struct dmub_srv *dmub = dc_dmub_srv->dmub; 110 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 111 enum dmub_status status; 112 113 status = dmub_srv_wait_for_idle(dmub, 100000); 114 if (status != DMUB_STATUS_OK) { 115 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); 116 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 117 } 118 } 119 120 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv) 121 { 122 struct dmub_srv *dmub = dmub_srv->dmub; 123 struct dc_context *dc_ctx = dmub_srv->ctx; 124 enum dmub_status status = DMUB_STATUS_OK; 125 126 status = dmub_srv_clear_inbox0_ack(dmub); 127 if (status != DMUB_STATUS_OK) { 128 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status); 129 dc_dmub_srv_log_diagnostic_data(dmub_srv); 130 } 131 } 132 133 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv) 134 { 135 struct dmub_srv *dmub = dmub_srv->dmub; 136 struct dc_context *dc_ctx = dmub_srv->ctx; 137 enum dmub_status status = DMUB_STATUS_OK; 138 139 status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); 140 if (status != DMUB_STATUS_OK) { 141 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n"); 142 dc_dmub_srv_log_diagnostic_data(dmub_srv); 143 } 144 } 145 146 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, 147 union dmub_inbox0_data_register data) 148 { 149 struct dmub_srv *dmub = dmub_srv->dmub; 150 struct dc_context *dc_ctx = dmub_srv->ctx; 151 enum dmub_status status = DMUB_STATUS_OK; 152 153 status = dmub_srv_send_inbox0_cmd(dmub, data); 154 if (status != DMUB_STATUS_OK) { 155 DC_ERROR("Error sending INBOX0 cmd\n"); 156 dc_dmub_srv_log_diagnostic_data(dmub_srv); 157 } 158 } 159 160 bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd) 161 { 162 struct dmub_srv *dmub; 163 enum dmub_status status; 164 165 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 166 return false; 167 168 dmub = dc_dmub_srv->dmub; 169 170 status = dmub_srv_cmd_with_reply_data(dmub, cmd); 171 if (status != DMUB_STATUS_OK) { 172 DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 173 return false; 174 } 175 176 return true; 177 } 178 179 void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv) 180 { 181 struct dmub_srv *dmub = dc_dmub_srv->dmub; 182 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 183 enum dmub_status status; 184 185 for (;;) { 186 /* Wait up to a second for PHY init. */ 187 status = dmub_srv_wait_for_phy_init(dmub, 1000000); 188 if (status == DMUB_STATUS_OK) 189 /* Initialization OK */ 190 break; 191 192 DC_ERROR("DMCUB PHY init failed: status=%d\n", status); 193 ASSERT(0); 194 195 if (status != DMUB_STATUS_TIMEOUT) 196 /* 197 * Server likely initialized or we don't have 198 * DMCUB HW support - this won't end. 199 */ 200 break; 201 202 /* Continue spinning so we don't hang the ASIC. */ 203 } 204 } 205 206 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 207 unsigned int stream_mask) 208 { 209 struct dmub_srv *dmub; 210 const uint32_t timeout = 30; 211 212 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 213 return false; 214 215 dmub = dc_dmub_srv->dmub; 216 217 return dmub_srv_send_gpint_command( 218 dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, 219 stream_mask, timeout) == DMUB_STATUS_OK; 220 } 221 222 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) 223 { 224 struct dmub_srv *dmub; 225 struct dc_context *dc_ctx; 226 union dmub_fw_boot_status boot_status; 227 enum dmub_status status; 228 229 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 230 return false; 231 232 dmub = dc_dmub_srv->dmub; 233 dc_ctx = dc_dmub_srv->ctx; 234 235 status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 236 if (status != DMUB_STATUS_OK) { 237 DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 238 return false; 239 } 240 241 return boot_status.bits.restore_required; 242 } 243 244 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) 245 { 246 struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; 247 return dmub_srv_get_outbox0_msg(dmub, entry); 248 } 249 250 void dc_dmub_trace_event_control(struct dc *dc, bool enable) 251 { 252 dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); 253 } 254 255 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) 256 { 257 union dmub_rb_cmd cmd = { 0 }; 258 259 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 260 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE; 261 cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 262 cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 263 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 264 265 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 266 267 // Send the command to the DMCUB. 268 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 269 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 270 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 271 } 272 273 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) 274 { 275 uint8_t pipes = 0; 276 int i = 0; 277 278 for (i = 0; i < MAX_PIPES; i++) { 279 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 280 281 if (pipe->stream == stream && pipe->stream_res.tg) 282 pipes = i; 283 } 284 return pipes; 285 } 286 287 static int dc_dmub_srv_get_timing_generator_offset(struct dc *dc, struct dc_stream_state *stream) 288 { 289 int tg_inst = 0; 290 int i = 0; 291 292 for (i = 0; i < MAX_PIPES; i++) { 293 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 294 295 if (pipe->stream == stream && pipe->stream_res.tg) { 296 tg_inst = pipe->stream_res.tg->inst; 297 break; 298 } 299 } 300 return tg_inst; 301 } 302 303 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) 304 { 305 union dmub_rb_cmd cmd = { 0 }; 306 struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; 307 int i = 0; 308 int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. 309 uint8_t visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; 310 311 if (dc == NULL) 312 return false; 313 314 // Format command. 315 cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 316 cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL; 317 cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate; 318 cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; 319 320 for (i = 0; context && i < context->stream_count; i++) { 321 struct dc_stream_state *stream = context->streams[i]; 322 uint8_t min_refresh_in_hz = (stream->timing.min_refresh_in_uhz + 999999) / 1000000; 323 int tg_inst = dc_dmub_srv_get_timing_generator_offset(dc, stream); 324 325 config_data->pipe_data[tg_inst].pix_clk_100hz = stream->timing.pix_clk_100hz; 326 config_data->pipe_data[tg_inst].min_refresh_in_hz = min_refresh_in_hz; 327 config_data->pipe_data[tg_inst].max_ramp_step = ramp_up_num_steps; 328 config_data->pipe_data[tg_inst].pipes = dc_dmub_srv_get_pipes_for_stream(dc, stream); 329 } 330 331 cmd.fw_assisted_mclk_switch.header.payload_bytes = 332 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header); 333 334 // Send the command to the DMCUB. 335 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 336 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 337 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 338 339 return true; 340 } 341 342 void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub) 343 { 344 union dmub_rb_cmd cmd = { 0 }; 345 enum dmub_status status; 346 347 if (!dmub) { 348 return; 349 } 350 351 memset(&cmd, 0, sizeof(cmd)); 352 353 /* Prepare fw command */ 354 cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; 355 cmd.query_feature_caps.header.sub_type = 0; 356 cmd.query_feature_caps.header.ret_status = 1; 357 cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); 358 359 /* Send command to fw */ 360 status = dmub_srv_cmd_with_reply_data(dmub, &cmd); 361 362 ASSERT(status == DMUB_STATUS_OK); 363 364 /* If command was processed, copy feature caps to dmub srv */ 365 if (status == DMUB_STATUS_OK && 366 cmd.query_feature_caps.header.ret_status == 0) { 367 memcpy(&dmub->feature_caps, 368 &cmd.query_feature_caps.query_feature_caps_data, 369 sizeof(struct dmub_feature_caps)); 370 } 371 } 372 373 #ifdef CONFIG_DRM_AMD_DC_DCN 374 /** 375 * *********************************************************************************************** 376 * populate_subvp_cmd_drr_info: Helper to populate DRR pipe info for the DMCUB subvp command 377 * 378 * Populate the DMCUB SubVP command with DRR pipe info. All the information required for calculating 379 * the SubVP + DRR microschedule is populated here. 380 * 381 * High level algorithm: 382 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 383 * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule 384 * 3. Populate the drr_info with the min and max supported vtotal values 385 * 386 * @param [in] dc: current dc state 387 * @param [in] subvp_pipe: pipe_ctx for the SubVP pipe 388 * @param [in] vblank_pipe: pipe_ctx for the DRR pipe 389 * @param [in] pipe_data: Pipe data which stores the VBLANK/DRR info 390 * 391 * @return: void 392 * 393 * *********************************************************************************************** 394 */ 395 static void populate_subvp_cmd_drr_info(struct dc *dc, 396 struct pipe_ctx *subvp_pipe, 397 struct pipe_ctx *vblank_pipe, 398 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data) 399 { 400 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 401 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 402 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 403 int16_t drr_frame_us = 0; 404 int16_t min_drr_supported_us = 0; 405 int16_t max_drr_supported_us = 0; 406 int16_t max_drr_vblank_us = 0; 407 int16_t max_drr_mallregion_us = 0; 408 int16_t mall_region_us = 0; 409 int16_t prefetch_us = 0; 410 int16_t subvp_active_us = 0; 411 int16_t drr_active_us = 0; 412 int16_t min_vtotal_supported = 0; 413 int16_t max_vtotal_supported = 0; 414 415 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; 416 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping 417 pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now 418 419 drr_frame_us = div64_s64(drr_timing->v_total * drr_timing->h_total, 420 (int64_t)(drr_timing->pix_clk_100hz * 100) * 1000000); 421 // P-State allow width and FW delays already included phantom_timing->v_addressable 422 mall_region_us = div64_s64(phantom_timing->v_addressable * phantom_timing->h_total, 423 (int64_t)(phantom_timing->pix_clk_100hz * 100) * 1000000); 424 min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 425 min_vtotal_supported = div64_s64(drr_timing->pix_clk_100hz * 100 * 426 (div64_s64((int64_t)min_drr_supported_us, 1000000)), 427 (int64_t)drr_timing->h_total); 428 429 prefetch_us = div64_s64((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total, 430 (int64_t)(phantom_timing->pix_clk_100hz * 100) * 1000000 + 431 dc->caps.subvp_prefetch_end_to_mall_start_us); 432 subvp_active_us = div64_s64(main_timing->v_addressable * main_timing->h_total, 433 (int64_t)(main_timing->pix_clk_100hz * 100) * 1000000); 434 drr_active_us = div64_s64(drr_timing->v_addressable * drr_timing->h_total, 435 (int64_t)(drr_timing->pix_clk_100hz * 100) * 1000000); 436 max_drr_vblank_us = div64_s64((int64_t)(subvp_active_us - prefetch_us - drr_active_us), 2) + drr_active_us; 437 max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us; 438 max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; 439 max_vtotal_supported = div64_s64(drr_timing->pix_clk_100hz * 100 * (div64_s64((int64_t)max_drr_supported_us, 1000000)), 440 (int64_t)drr_timing->h_total); 441 442 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; 443 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; 444 } 445 446 /** 447 * *********************************************************************************************** 448 * populate_subvp_cmd_vblank_pipe_info: Helper to populate VBLANK pipe info for the DMUB subvp command 449 * 450 * Populate the DMCUB SubVP command with VBLANK pipe info. All the information required to calculate 451 * the microschedule for SubVP + VBLANK case is stored in the pipe_data (subvp_data and vblank_data). 452 * Also check if the VBLANK pipe is a DRR display -- if it is make a call to populate drr_info. 453 * 454 * @param [in] dc: current dc state 455 * @param [in] context: new dc state 456 * @param [in] cmd: DMUB cmd to be populated with SubVP info 457 * @param [in] vblank_pipe: pipe_ctx for the VBLANK pipe 458 * @param [in] cmd_pipe_index: index for the pipe array in DMCUB SubVP cmd 459 * 460 * @return: void 461 * 462 * *********************************************************************************************** 463 */ 464 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, 465 struct dc_state *context, 466 union dmub_rb_cmd *cmd, 467 struct pipe_ctx *vblank_pipe, 468 uint8_t cmd_pipe_index) 469 { 470 uint32_t i; 471 struct pipe_ctx *pipe = NULL; 472 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 473 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 474 475 // Find the SubVP pipe 476 for (i = 0; i < dc->res_pool->pipe_count; i++) { 477 pipe = &context->res_ctx.pipe_ctx[i]; 478 479 // We check for master pipe, but it shouldn't matter since we only need 480 // the pipe for timing info (stream should be same for any pipe splits) 481 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 482 continue; 483 484 // Find the SubVP pipe 485 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 486 break; 487 } 488 489 pipe_data->mode = VBLANK; 490 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; 491 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - 492 vblank_pipe->stream->timing.v_front_porch; 493 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; 494 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; 495 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; 496 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; 497 pipe_data->pipe_config.vblank_data.vblank_end = 498 vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; 499 500 if (vblank_pipe->stream->ignore_msa_timing_param) 501 populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data); 502 } 503 504 /** 505 * *********************************************************************************************** 506 * update_subvp_prefetch_end_to_mall_start: Helper for SubVP + SubVP case 507 * 508 * For SubVP + SubVP, we use a single vertical interrupt to start the microschedule for both 509 * SubVP pipes. In order for this to work correctly, the MALL REGION of both SubVP pipes must 510 * start at the same time. This function lengthens the prefetch end to mall start delay of the 511 * SubVP pipe that has the shorter prefetch so that both MALL REGION's will start at the same time. 512 * 513 * @param [in] dc: current dc state 514 * @param [in] context: new dc state 515 * @param [in] cmd: DMUB cmd to be populated with SubVP info 516 * @param [in] subvp_pipes: Array of SubVP pipes (should always be length 2) 517 * 518 * @return: void 519 * 520 * *********************************************************************************************** 521 */ 522 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, 523 struct dc_state *context, 524 union dmub_rb_cmd *cmd, 525 struct pipe_ctx *subvp_pipes[]) 526 { 527 uint32_t subvp0_prefetch_us = 0; 528 uint32_t subvp1_prefetch_us = 0; 529 uint32_t prefetch_delta_us = 0; 530 struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing; 531 struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing; 532 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL; 533 534 subvp0_prefetch_us = div64_s64((phantom_timing0->v_total - phantom_timing0->v_front_porch) * phantom_timing0->h_total, 535 (int64_t)(phantom_timing0->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us); 536 subvp1_prefetch_us = div64_s64((phantom_timing1->v_total - phantom_timing1->v_front_porch) * phantom_timing1->h_total, 537 (int64_t)(phantom_timing1->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us); 538 539 // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) 540 // should increase it's prefetch time to match the other 541 if (subvp0_prefetch_us > subvp1_prefetch_us) { 542 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; 543 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; 544 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 545 div64_s64(((div64_s64((int64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us), 1000000)) * 546 (phantom_timing1->pix_clk_100hz * 100) + phantom_timing1->h_total - 1), 547 (int64_t)phantom_timing1->h_total); 548 } else if (subvp1_prefetch_us > subvp0_prefetch_us) { 549 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; 550 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; 551 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 552 div64_s64(((div64_s64((int64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us), 1000000)) * 553 (phantom_timing0->pix_clk_100hz * 100) + phantom_timing0->h_total - 1), 554 (int64_t)phantom_timing0->h_total); 555 } 556 } 557 558 /** 559 * *************************************************************************************** 560 * setup_subvp_dmub_command: Helper to populate the SubVP pipe info for the DMUB subvp command 561 * 562 * Populate the DMCUB SubVP command with SubVP pipe info. All the information required to 563 * calculate the microschedule for the SubVP pipe is stored in the pipe_data of the DMCUB 564 * SubVP command. 565 * 566 * @param [in] dc: current dc state 567 * @param [in] context: new dc state 568 * @param [in] cmd: DMUB cmd to be populated with SubVP info 569 * @param [in] subvp_pipe: pipe_ctx for the SubVP pipe 570 * @param [in] cmd_pipe_index: index for the pipe array in DMCUB SubVP cmd 571 * 572 * @return: void 573 * 574 * *************************************************************************************** 575 */ 576 static void populate_subvp_cmd_pipe_info(struct dc *dc, 577 struct dc_state *context, 578 union dmub_rb_cmd *cmd, 579 struct pipe_ctx *subvp_pipe, 580 uint8_t cmd_pipe_index) 581 { 582 uint32_t j; 583 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 584 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 585 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 586 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 587 588 pipe_data->mode = SUBVP; 589 pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; 590 pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; 591 pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; 592 pipe_data->pipe_config.subvp_data.main_vblank_start = 593 main_timing->v_total - main_timing->v_front_porch; 594 pipe_data->pipe_config.subvp_data.main_vblank_end = 595 main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; 596 pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; 597 pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->pipe_idx; 598 599 // Prefetch lines is equal to VACTIVE + BP + VSYNC 600 pipe_data->pipe_config.subvp_data.prefetch_lines = 601 phantom_timing->v_total - phantom_timing->v_front_porch; 602 603 // Round up 604 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 605 div64_s64(((div64_s64((int64_t)dc->caps.subvp_prefetch_end_to_mall_start_us, 1000000)) * 606 (phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1), 607 (int64_t)phantom_timing->h_total); 608 pipe_data->pipe_config.subvp_data.processing_delay_lines = 609 div64_s64(((div64_s64((int64_t)dc->caps.subvp_fw_processing_delay_us, 1000000)) * 610 (phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1), 611 (int64_t)phantom_timing->h_total); 612 // Find phantom pipe index based on phantom stream 613 for (j = 0; j < dc->res_pool->pipe_count; j++) { 614 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; 615 616 if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) { 617 pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->pipe_idx; 618 break; 619 } 620 } 621 } 622 623 /** 624 * *************************************************************************************** 625 * dc_dmub_setup_subvp_dmub_command: Populate the DMCUB SubVP command 626 * 627 * This function loops through each pipe and populates the DMUB 628 * SubVP CMD info based on the pipe (e.g. SubVP, VBLANK). 629 * 630 * @param [in] dc: current dc state 631 * @param [in] context: new dc state 632 * @param [in] cmd: DMUB cmd to be populated with SubVP info 633 * 634 * @return: void 635 * 636 * *************************************************************************************** 637 */ 638 void dc_dmub_setup_subvp_dmub_command(struct dc *dc, 639 struct dc_state *context, 640 bool enable) 641 { 642 uint8_t cmd_pipe_index = 0; 643 uint32_t i, pipe_idx; 644 uint8_t subvp_count = 0; 645 union dmub_rb_cmd cmd; 646 struct pipe_ctx *subvp_pipes[2]; 647 uint32_t wm_val_refclk = 0; 648 649 memset(&cmd, 0, sizeof(cmd)); 650 // FW command for SUBVP 651 cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 652 cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD; 653 cmd.fw_assisted_mclk_switch_v2.header.payload_bytes = 654 sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header); 655 656 for (i = 0; i < dc->res_pool->pipe_count; i++) { 657 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 658 659 if (!pipe->stream) 660 continue; 661 662 if (pipe->plane_state && !pipe->top_pipe && 663 pipe->stream->mall_stream_config.type == SUBVP_MAIN) 664 subvp_pipes[subvp_count++] = pipe; 665 } 666 667 if (enable) { 668 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd 669 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 670 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 671 672 if (!pipe->stream) 673 continue; 674 675 if (pipe->plane_state && pipe->stream->mall_stream_config.paired_stream && 676 pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 677 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 678 } else if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_NONE) { 679 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where 680 // we run through DML without calculating "natural" P-state support 681 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 682 683 } 684 pipe_idx++; 685 } 686 if (subvp_count == 2) { 687 update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); 688 } 689 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 690 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; 691 692 // Store the original watermark value for this SubVP config so we can lower it when the 693 // MCLK switch starts 694 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * 695 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 / 1000; 696 697 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; 698 } 699 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 700 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 701 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 702 } 703 #endif 704 705 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) 706 { 707 if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) 708 return false; 709 return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data); 710 } 711 712 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 713 { 714 struct dmub_diagnostic_data diag_data = {0}; 715 716 if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 717 DC_LOG_ERROR("%s: invalid parameters.", __func__); 718 return; 719 } 720 721 if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) { 722 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); 723 return; 724 } 725 726 DC_LOG_DEBUG( 727 "DMCUB STATE\n" 728 " dmcub_version : %08x\n" 729 " scratch [0] : %08x\n" 730 " scratch [1] : %08x\n" 731 " scratch [2] : %08x\n" 732 " scratch [3] : %08x\n" 733 " scratch [4] : %08x\n" 734 " scratch [5] : %08x\n" 735 " scratch [6] : %08x\n" 736 " scratch [7] : %08x\n" 737 " scratch [8] : %08x\n" 738 " scratch [9] : %08x\n" 739 " scratch [10] : %08x\n" 740 " scratch [11] : %08x\n" 741 " scratch [12] : %08x\n" 742 " scratch [13] : %08x\n" 743 " scratch [14] : %08x\n" 744 " scratch [15] : %08x\n" 745 " pc : %08x\n" 746 " unk_fault_addr : %08x\n" 747 " inst_fault_addr : %08x\n" 748 " data_fault_addr : %08x\n" 749 " inbox1_rptr : %08x\n" 750 " inbox1_wptr : %08x\n" 751 " inbox1_size : %08x\n" 752 " inbox0_rptr : %08x\n" 753 " inbox0_wptr : %08x\n" 754 " inbox0_size : %08x\n" 755 " is_enabled : %d\n" 756 " is_soft_reset : %d\n" 757 " is_secure_reset : %d\n" 758 " is_traceport_en : %d\n" 759 " is_cw0_en : %d\n" 760 " is_cw6_en : %d\n", 761 diag_data.dmcub_version, 762 diag_data.scratch[0], 763 diag_data.scratch[1], 764 diag_data.scratch[2], 765 diag_data.scratch[3], 766 diag_data.scratch[4], 767 diag_data.scratch[5], 768 diag_data.scratch[6], 769 diag_data.scratch[7], 770 diag_data.scratch[8], 771 diag_data.scratch[9], 772 diag_data.scratch[10], 773 diag_data.scratch[11], 774 diag_data.scratch[12], 775 diag_data.scratch[13], 776 diag_data.scratch[14], 777 diag_data.scratch[15], 778 diag_data.pc, 779 diag_data.undefined_address_fault_addr, 780 diag_data.inst_fetch_fault_addr, 781 diag_data.data_write_fault_addr, 782 diag_data.inbox1_rptr, 783 diag_data.inbox1_wptr, 784 diag_data.inbox1_size, 785 diag_data.inbox0_rptr, 786 diag_data.inbox0_wptr, 787 diag_data.inbox0_size, 788 diag_data.is_dmcub_enabled, 789 diag_data.is_dmcub_soft_reset, 790 diag_data.is_dmcub_secure_reset, 791 diag_data.is_traceport_en, 792 diag_data.is_cw0_enabled, 793 diag_data.is_cw6_enabled); 794 } 795