1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc.h" 27 #include "dc_dmub_srv.h" 28 #include "../dmub/dmub_srv.h" 29 #include "dm_helpers.h" 30 #include "dc_hw_types.h" 31 #include "core_types.h" 32 #include "../basics/conversion.h" 33 #include "cursor_reg_cache.h" 34 35 #define CTX dc_dmub_srv->ctx 36 #define DC_LOGGER CTX->logger 37 38 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, 39 struct dmub_srv *dmub) 40 { 41 dc_srv->dmub = dmub; 42 dc_srv->ctx = dc->ctx; 43 } 44 45 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) 46 { 47 struct dc_dmub_srv *dc_srv = 48 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL); 49 50 if (dc_srv == NULL) { 51 BREAK_TO_DEBUGGER(); 52 return NULL; 53 } 54 55 dc_dmub_srv_construct(dc_srv, dc, dmub); 56 57 return dc_srv; 58 } 59 60 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv) 61 { 62 if (*dmub_srv) { 63 kfree(*dmub_srv); 64 *dmub_srv = NULL; 65 } 66 } 67 68 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) 69 { 70 struct dmub_srv *dmub = dc_dmub_srv->dmub; 71 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 72 enum dmub_status status; 73 74 status = dmub_srv_wait_for_idle(dmub, 100000); 75 if (status != DMUB_STATUS_OK) { 76 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); 77 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 78 } 79 } 80 81 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv) 82 { 83 struct dmub_srv *dmub = dmub_srv->dmub; 84 struct dc_context *dc_ctx = dmub_srv->ctx; 85 enum dmub_status status = DMUB_STATUS_OK; 86 87 status = dmub_srv_clear_inbox0_ack(dmub); 88 if (status != DMUB_STATUS_OK) { 89 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status); 90 dc_dmub_srv_log_diagnostic_data(dmub_srv); 91 } 92 } 93 94 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv) 95 { 96 struct dmub_srv *dmub = dmub_srv->dmub; 97 struct dc_context *dc_ctx = dmub_srv->ctx; 98 enum dmub_status status = DMUB_STATUS_OK; 99 100 status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); 101 if (status != DMUB_STATUS_OK) { 102 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n"); 103 dc_dmub_srv_log_diagnostic_data(dmub_srv); 104 } 105 } 106 107 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, 108 union dmub_inbox0_data_register data) 109 { 110 struct dmub_srv *dmub = dmub_srv->dmub; 111 struct dc_context *dc_ctx = dmub_srv->ctx; 112 enum dmub_status status = DMUB_STATUS_OK; 113 114 status = dmub_srv_send_inbox0_cmd(dmub, data); 115 if (status != DMUB_STATUS_OK) { 116 DC_ERROR("Error sending INBOX0 cmd\n"); 117 dc_dmub_srv_log_diagnostic_data(dmub_srv); 118 } 119 } 120 121 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 122 { 123 return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type); 124 } 125 126 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type) 127 { 128 struct dc_context *dc_ctx; 129 struct dmub_srv *dmub; 130 enum dmub_status status; 131 int i; 132 133 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 134 return false; 135 136 dc_ctx = dc_dmub_srv->ctx; 137 dmub = dc_dmub_srv->dmub; 138 139 for (i = 0 ; i < count; i++) { 140 // Queue command 141 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 142 143 if (status == DMUB_STATUS_QUEUE_FULL) { 144 /* Execute and wait for queue to become empty again. */ 145 dmub_srv_cmd_execute(dmub); 146 dmub_srv_wait_for_idle(dmub, 100000); 147 148 /* Requeue the command. */ 149 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 150 } 151 152 if (status != DMUB_STATUS_OK) { 153 DC_ERROR("Error queueing DMUB command: status=%d\n", status); 154 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 155 return false; 156 } 157 } 158 159 status = dmub_srv_cmd_execute(dmub); 160 if (status != DMUB_STATUS_OK) { 161 DC_ERROR("Error starting DMUB execution: status=%d\n", status); 162 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 163 return false; 164 } 165 166 // Wait for DMUB to process command 167 if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) { 168 status = dmub_srv_wait_for_idle(dmub, 100000); 169 170 if (status != DMUB_STATUS_OK) { 171 DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 172 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 173 return false; 174 } 175 176 // Copy data back from ring buffer into command 177 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) 178 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list); 179 } 180 181 return true; 182 } 183 184 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv) 185 { 186 struct dmub_srv *dmub; 187 struct dc_context *dc_ctx; 188 union dmub_fw_boot_status boot_status; 189 enum dmub_status status; 190 191 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 192 return false; 193 194 dmub = dc_dmub_srv->dmub; 195 dc_ctx = dc_dmub_srv->ctx; 196 197 status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 198 if (status != DMUB_STATUS_OK) { 199 DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 200 return false; 201 } 202 203 return boot_status.bits.optimized_init_done; 204 } 205 206 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 207 unsigned int stream_mask) 208 { 209 struct dmub_srv *dmub; 210 const uint32_t timeout = 30; 211 212 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 213 return false; 214 215 dmub = dc_dmub_srv->dmub; 216 217 return dmub_srv_send_gpint_command( 218 dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, 219 stream_mask, timeout) == DMUB_STATUS_OK; 220 } 221 222 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) 223 { 224 struct dmub_srv *dmub; 225 struct dc_context *dc_ctx; 226 union dmub_fw_boot_status boot_status; 227 enum dmub_status status; 228 229 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 230 return false; 231 232 dmub = dc_dmub_srv->dmub; 233 dc_ctx = dc_dmub_srv->ctx; 234 235 status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 236 if (status != DMUB_STATUS_OK) { 237 DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 238 return false; 239 } 240 241 return boot_status.bits.restore_required; 242 } 243 244 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) 245 { 246 struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; 247 return dmub_srv_get_outbox0_msg(dmub, entry); 248 } 249 250 void dc_dmub_trace_event_control(struct dc *dc, bool enable) 251 { 252 dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); 253 } 254 255 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) 256 { 257 union dmub_rb_cmd cmd = { 0 }; 258 259 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 260 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE; 261 cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 262 cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 263 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 264 265 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 266 267 // Send the command to the DMCUB. 268 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 269 } 270 271 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) 272 { 273 union dmub_rb_cmd cmd = { 0 }; 274 275 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 276 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER; 277 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 278 279 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 280 281 // Send the command to the DMCUB. 282 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 283 } 284 285 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) 286 { 287 uint8_t pipes = 0; 288 int i = 0; 289 290 for (i = 0; i < MAX_PIPES; i++) { 291 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 292 293 if (pipe->stream == stream && pipe->stream_res.tg) 294 pipes = i; 295 } 296 return pipes; 297 } 298 299 static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context, 300 struct pipe_ctx *head_pipe, 301 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data) 302 { 303 int j; 304 int pipe_idx = 0; 305 306 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; 307 for (j = 0; j < dc->res_pool->pipe_count; j++) { 308 struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j]; 309 310 if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) { 311 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; 312 } 313 } 314 fams_pipe_data->pipe_count = pipe_idx; 315 } 316 317 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) 318 { 319 union dmub_rb_cmd cmd = { 0 }; 320 struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; 321 int i = 0, k = 0; 322 int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. 323 uint8_t visual_confirm_enabled; 324 int pipe_idx = 0; 325 326 if (dc == NULL) 327 return false; 328 329 visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; 330 331 // Format command. 332 cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 333 cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL; 334 cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate; 335 cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; 336 337 if (should_manage_pstate) { 338 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 339 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 340 341 if (!pipe->stream) 342 continue; 343 344 /* If FAMS is being used to support P-State and there is a stream 345 * that does not use FAMS, we are in an FPO + VActive scenario. 346 * Assign vactive stretch margin in this case. 347 */ 348 if (!pipe->stream->fpo_in_use) { 349 cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us; 350 break; 351 } 352 pipe_idx++; 353 } 354 } 355 356 for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { 357 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 358 359 if (!pipe->top_pipe && !pipe->prev_odm_pipe && pipe->stream && pipe->stream->fpo_in_use) { 360 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 361 uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000; 362 363 config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz; 364 config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz; 365 config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps; 366 config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream); 367 dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]); 368 k++; 369 } 370 } 371 cmd.fw_assisted_mclk_switch.header.payload_bytes = 372 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header); 373 374 // Send the command to the DMCUB. 375 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 376 377 return true; 378 } 379 380 void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv) 381 { 382 union dmub_rb_cmd cmd = { 0 }; 383 384 memset(&cmd, 0, sizeof(cmd)); 385 386 /* Prepare fw command */ 387 cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; 388 cmd.query_feature_caps.header.sub_type = 0; 389 cmd.query_feature_caps.header.ret_status = 1; 390 cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); 391 392 /* If command was processed, copy feature caps to dmub srv */ 393 if (dm_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 394 cmd.query_feature_caps.header.ret_status == 0) { 395 memcpy(&dc_dmub_srv->dmub->feature_caps, 396 &cmd.query_feature_caps.query_feature_caps_data, 397 sizeof(struct dmub_feature_caps)); 398 } 399 } 400 401 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx) 402 { 403 union dmub_rb_cmd cmd = { 0 }; 404 unsigned int panel_inst = 0; 405 406 dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst); 407 408 memset(&cmd, 0, sizeof(cmd)); 409 410 // Prepare fw command 411 cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR; 412 cmd.visual_confirm_color.header.sub_type = 0; 413 cmd.visual_confirm_color.header.ret_status = 1; 414 cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data); 415 cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst; 416 417 // If command was processed, copy feature caps to dmub srv 418 if (dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 419 cmd.visual_confirm_color.header.ret_status == 0) { 420 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color, 421 &cmd.visual_confirm_color.visual_confirm_color_data, 422 sizeof(struct dmub_visual_confirm_color)); 423 } 424 } 425 426 /** 427 * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command 428 * 429 * @dc: [in] current dc state 430 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 431 * @vblank_pipe: [in] pipe_ctx for the DRR pipe 432 * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info 433 * 434 * Populate the DMCUB SubVP command with DRR pipe info. All the information 435 * required for calculating the SubVP + DRR microschedule is populated here. 436 * 437 * High level algorithm: 438 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 439 * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule 440 * 3. Populate the drr_info with the min and max supported vtotal values 441 */ 442 static void populate_subvp_cmd_drr_info(struct dc *dc, 443 struct pipe_ctx *subvp_pipe, 444 struct pipe_ctx *vblank_pipe, 445 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data) 446 { 447 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 448 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 449 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 450 uint16_t drr_frame_us = 0; 451 uint16_t min_drr_supported_us = 0; 452 uint16_t max_drr_supported_us = 0; 453 uint16_t max_drr_vblank_us = 0; 454 uint16_t max_drr_mallregion_us = 0; 455 uint16_t mall_region_us = 0; 456 uint16_t prefetch_us = 0; 457 uint16_t subvp_active_us = 0; 458 uint16_t drr_active_us = 0; 459 uint16_t min_vtotal_supported = 0; 460 uint16_t max_vtotal_supported = 0; 461 462 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; 463 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping 464 pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now 465 466 drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000), 467 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 468 // P-State allow width and FW delays already included phantom_timing->v_addressable 469 mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000), 470 (((uint64_t)phantom_timing->pix_clk_100hz * 100))); 471 min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 472 min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us), 473 (((uint64_t)drr_timing->h_total * 1000000))); 474 475 prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000), 476 (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 477 subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000), 478 (((uint64_t)main_timing->pix_clk_100hz * 100))); 479 drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000), 480 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 481 max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - 482 dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us; 483 max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us; 484 max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; 485 max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us), 486 (((uint64_t)drr_timing->h_total * 1000000))); 487 488 /* When calculating the max vtotal supported for SubVP + DRR cases, add 489 * margin due to possible rounding errors (being off by 1 line in the 490 * FW calculation can incorrectly push the P-State switch to wait 1 frame 491 * longer). 492 */ 493 max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us; 494 495 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; 496 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; 497 pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us; 498 } 499 500 /** 501 * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command 502 * 503 * @dc: [in] current dc state 504 * @context: [in] new dc state 505 * @cmd: [in] DMUB cmd to be populated with SubVP info 506 * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe 507 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 508 * 509 * Populate the DMCUB SubVP command with VBLANK pipe info. All the information 510 * required to calculate the microschedule for SubVP + VBLANK case is stored in 511 * the pipe_data (subvp_data and vblank_data). Also check if the VBLANK pipe 512 * is a DRR display -- if it is make a call to populate drr_info. 513 */ 514 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, 515 struct dc_state *context, 516 union dmub_rb_cmd *cmd, 517 struct pipe_ctx *vblank_pipe, 518 uint8_t cmd_pipe_index) 519 { 520 uint32_t i; 521 struct pipe_ctx *pipe = NULL; 522 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 523 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 524 525 // Find the SubVP pipe 526 for (i = 0; i < dc->res_pool->pipe_count; i++) { 527 pipe = &context->res_ctx.pipe_ctx[i]; 528 529 // We check for master pipe, but it shouldn't matter since we only need 530 // the pipe for timing info (stream should be same for any pipe splits) 531 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 532 continue; 533 534 // Find the SubVP pipe 535 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 536 break; 537 } 538 539 pipe_data->mode = VBLANK; 540 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; 541 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - 542 vblank_pipe->stream->timing.v_front_porch; 543 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; 544 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; 545 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; 546 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; 547 pipe_data->pipe_config.vblank_data.vblank_end = 548 vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; 549 550 if (vblank_pipe->stream->ignore_msa_timing_param) 551 populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data); 552 } 553 554 /** 555 * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case 556 * 557 * @dc: [in] current dc state 558 * @context: [in] new dc state 559 * @cmd: [in] DMUB cmd to be populated with SubVP info 560 * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2) 561 * 562 * For SubVP + SubVP, we use a single vertical interrupt to start the 563 * microschedule for both SubVP pipes. In order for this to work correctly, the 564 * MALL REGION of both SubVP pipes must start at the same time. This function 565 * lengthens the prefetch end to mall start delay of the SubVP pipe that has 566 * the shorter prefetch so that both MALL REGION's will start at the same time. 567 */ 568 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, 569 struct dc_state *context, 570 union dmub_rb_cmd *cmd, 571 struct pipe_ctx *subvp_pipes[]) 572 { 573 uint32_t subvp0_prefetch_us = 0; 574 uint32_t subvp1_prefetch_us = 0; 575 uint32_t prefetch_delta_us = 0; 576 struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing; 577 struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing; 578 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL; 579 580 subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * 581 (uint64_t)phantom_timing0->h_total * 1000000), 582 (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 583 subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * 584 (uint64_t)phantom_timing1->h_total * 1000000), 585 (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 586 587 // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) 588 // should increase it's prefetch time to match the other 589 if (subvp0_prefetch_us > subvp1_prefetch_us) { 590 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; 591 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; 592 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 593 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 594 ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), 595 ((uint64_t)phantom_timing1->h_total * 1000000)); 596 597 } else if (subvp1_prefetch_us > subvp0_prefetch_us) { 598 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; 599 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; 600 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 601 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 602 ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), 603 ((uint64_t)phantom_timing0->h_total * 1000000)); 604 } 605 } 606 607 /** 608 * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command 609 * 610 * @dc: [in] current dc state 611 * @context: [in] new dc state 612 * @cmd: [in] DMUB cmd to be populated with SubVP info 613 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 614 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 615 * 616 * Populate the DMCUB SubVP command with SubVP pipe info. All the information 617 * required to calculate the microschedule for the SubVP pipe is stored in the 618 * pipe_data of the DMCUB SubVP command. 619 */ 620 static void populate_subvp_cmd_pipe_info(struct dc *dc, 621 struct dc_state *context, 622 union dmub_rb_cmd *cmd, 623 struct pipe_ctx *subvp_pipe, 624 uint8_t cmd_pipe_index) 625 { 626 uint32_t j; 627 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 628 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 629 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 630 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 631 uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den; 632 633 pipe_data->mode = SUBVP; 634 pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; 635 pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; 636 pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; 637 pipe_data->pipe_config.subvp_data.main_vblank_start = 638 main_timing->v_total - main_timing->v_front_porch; 639 pipe_data->pipe_config.subvp_data.main_vblank_end = 640 main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; 641 pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; 642 pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst; 643 pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param; 644 645 /* Calculate the scaling factor from the src and dst height. 646 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2. 647 * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor" 648 * 649 * Make sure to combine stream and plane scaling together. 650 */ 651 reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height, 652 &out_num_stream, &out_den_stream); 653 reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height, 654 &out_num_plane, &out_den_plane); 655 reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den); 656 pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num; 657 pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den; 658 659 // Prefetch lines is equal to VACTIVE + BP + VSYNC 660 pipe_data->pipe_config.subvp_data.prefetch_lines = 661 phantom_timing->v_total - phantom_timing->v_front_porch; 662 663 // Round up 664 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 665 div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 666 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 667 pipe_data->pipe_config.subvp_data.processing_delay_lines = 668 div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 669 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 670 671 if (subvp_pipe->bottom_pipe) { 672 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; 673 } else if (subvp_pipe->next_odm_pipe) { 674 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; 675 } else { 676 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0; 677 } 678 679 // Find phantom pipe index based on phantom stream 680 for (j = 0; j < dc->res_pool->pipe_count; j++) { 681 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; 682 683 if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) { 684 pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst; 685 if (phantom_pipe->bottom_pipe) { 686 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; 687 } else if (phantom_pipe->next_odm_pipe) { 688 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; 689 } else { 690 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0; 691 } 692 break; 693 } 694 } 695 } 696 697 /** 698 * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command 699 * 700 * @dc: [in] current dc state 701 * @context: [in] new dc state 702 * @enable: [in] if true enables the pipes population 703 * 704 * This function loops through each pipe and populates the DMUB SubVP CMD info 705 * based on the pipe (e.g. SubVP, VBLANK). 706 */ 707 void dc_dmub_setup_subvp_dmub_command(struct dc *dc, 708 struct dc_state *context, 709 bool enable) 710 { 711 uint8_t cmd_pipe_index = 0; 712 uint32_t i, pipe_idx; 713 uint8_t subvp_count = 0; 714 union dmub_rb_cmd cmd; 715 struct pipe_ctx *subvp_pipes[2]; 716 uint32_t wm_val_refclk = 0; 717 718 memset(&cmd, 0, sizeof(cmd)); 719 // FW command for SUBVP 720 cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 721 cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD; 722 cmd.fw_assisted_mclk_switch_v2.header.payload_bytes = 723 sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header); 724 725 for (i = 0; i < dc->res_pool->pipe_count; i++) { 726 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 727 728 if (!pipe->stream) 729 continue; 730 731 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe 732 */ 733 if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && 734 pipe->stream->mall_stream_config.type == SUBVP_MAIN) 735 subvp_pipes[subvp_count++] = pipe; 736 } 737 738 if (enable) { 739 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd 740 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 741 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 742 743 if (!pipe->stream) 744 continue; 745 746 /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe. 747 * Any ODM or MPC splits being used in SubVP will be handled internally in 748 * populate_subvp_cmd_pipe_info 749 */ 750 if (pipe->plane_state && pipe->stream->mall_stream_config.paired_stream && 751 !pipe->top_pipe && !pipe->prev_odm_pipe && 752 pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 753 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 754 } else if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_NONE && 755 !pipe->top_pipe && !pipe->prev_odm_pipe) { 756 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where 757 // we run through DML without calculating "natural" P-state support 758 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 759 760 } 761 pipe_idx++; 762 } 763 if (subvp_count == 2) { 764 update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); 765 } 766 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 767 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; 768 769 // Store the original watermark value for this SubVP config so we can lower it when the 770 // MCLK switch starts 771 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * 772 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; 773 774 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; 775 } 776 777 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 778 } 779 780 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) 781 { 782 if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) 783 return false; 784 return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data); 785 } 786 787 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 788 { 789 struct dmub_diagnostic_data diag_data = {0}; 790 791 if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 792 DC_LOG_ERROR("%s: invalid parameters.", __func__); 793 return; 794 } 795 796 if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) { 797 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); 798 return; 799 } 800 801 DC_LOG_DEBUG("DMCUB STATE:"); 802 DC_LOG_DEBUG(" dmcub_version : %08x", diag_data.dmcub_version); 803 DC_LOG_DEBUG(" scratch [0] : %08x", diag_data.scratch[0]); 804 DC_LOG_DEBUG(" scratch [1] : %08x", diag_data.scratch[1]); 805 DC_LOG_DEBUG(" scratch [2] : %08x", diag_data.scratch[2]); 806 DC_LOG_DEBUG(" scratch [3] : %08x", diag_data.scratch[3]); 807 DC_LOG_DEBUG(" scratch [4] : %08x", diag_data.scratch[4]); 808 DC_LOG_DEBUG(" scratch [5] : %08x", diag_data.scratch[5]); 809 DC_LOG_DEBUG(" scratch [6] : %08x", diag_data.scratch[6]); 810 DC_LOG_DEBUG(" scratch [7] : %08x", diag_data.scratch[7]); 811 DC_LOG_DEBUG(" scratch [8] : %08x", diag_data.scratch[8]); 812 DC_LOG_DEBUG(" scratch [9] : %08x", diag_data.scratch[9]); 813 DC_LOG_DEBUG(" scratch [10] : %08x", diag_data.scratch[10]); 814 DC_LOG_DEBUG(" scratch [11] : %08x", diag_data.scratch[11]); 815 DC_LOG_DEBUG(" scratch [12] : %08x", diag_data.scratch[12]); 816 DC_LOG_DEBUG(" scratch [13] : %08x", diag_data.scratch[13]); 817 DC_LOG_DEBUG(" scratch [14] : %08x", diag_data.scratch[14]); 818 DC_LOG_DEBUG(" scratch [15] : %08x", diag_data.scratch[15]); 819 DC_LOG_DEBUG(" pc : %08x", diag_data.pc); 820 DC_LOG_DEBUG(" unk_fault_addr : %08x", diag_data.undefined_address_fault_addr); 821 DC_LOG_DEBUG(" inst_fault_addr : %08x", diag_data.inst_fetch_fault_addr); 822 DC_LOG_DEBUG(" data_fault_addr : %08x", diag_data.data_write_fault_addr); 823 DC_LOG_DEBUG(" inbox1_rptr : %08x", diag_data.inbox1_rptr); 824 DC_LOG_DEBUG(" inbox1_wptr : %08x", diag_data.inbox1_wptr); 825 DC_LOG_DEBUG(" inbox1_size : %08x", diag_data.inbox1_size); 826 DC_LOG_DEBUG(" inbox0_rptr : %08x", diag_data.inbox0_rptr); 827 DC_LOG_DEBUG(" inbox0_wptr : %08x", diag_data.inbox0_wptr); 828 DC_LOG_DEBUG(" inbox0_size : %08x", diag_data.inbox0_size); 829 DC_LOG_DEBUG(" is_enabled : %d", diag_data.is_dmcub_enabled); 830 DC_LOG_DEBUG(" is_soft_reset : %d", diag_data.is_dmcub_soft_reset); 831 DC_LOG_DEBUG(" is_secure_reset : %d", diag_data.is_dmcub_secure_reset); 832 DC_LOG_DEBUG(" is_traceport_en : %d", diag_data.is_traceport_en); 833 DC_LOG_DEBUG(" is_cw0_en : %d", diag_data.is_cw0_enabled); 834 DC_LOG_DEBUG(" is_cw6_en : %d", diag_data.is_cw6_enabled); 835 } 836 837 static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) 838 { 839 struct pipe_ctx *test_pipe, *split_pipe; 840 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; 841 struct rect r1 = scl_data->recout, r2, r2_half; 842 int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b; 843 int cur_layer = pipe_ctx->plane_state->layer_index; 844 845 /** 846 * Disable the cursor if there's another pipe above this with a 847 * plane that contains this pipe's viewport to prevent double cursor 848 * and incorrect scaling artifacts. 849 */ 850 for (test_pipe = pipe_ctx->top_pipe; test_pipe; 851 test_pipe = test_pipe->top_pipe) { 852 // Skip invisible layer and pipe-split plane on same layer 853 if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer) 854 continue; 855 856 r2 = test_pipe->plane_res.scl_data.recout; 857 r2_r = r2.x + r2.width; 858 r2_b = r2.y + r2.height; 859 split_pipe = test_pipe; 860 861 /** 862 * There is another half plane on same layer because of 863 * pipe-split, merge together per same height. 864 */ 865 for (split_pipe = pipe_ctx->top_pipe; split_pipe; 866 split_pipe = split_pipe->top_pipe) 867 if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) { 868 r2_half = split_pipe->plane_res.scl_data.recout; 869 r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x; 870 r2.width = r2.width + r2_half.width; 871 r2_r = r2.x + r2.width; 872 break; 873 } 874 875 if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b) 876 return true; 877 } 878 879 return false; 880 } 881 882 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx) 883 { 884 if (pipe_ctx->plane_state != NULL) { 885 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 886 return false; 887 888 if (dc_can_pipe_disable_cursor(pipe_ctx)) 889 return false; 890 } 891 892 if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || 893 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) && 894 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1) 895 return true; 896 897 return false; 898 } 899 900 static void dc_build_cursor_update_payload0( 901 struct pipe_ctx *pipe_ctx, uint8_t p_idx, 902 struct dmub_cmd_update_cursor_payload0 *payload) 903 { 904 struct hubp *hubp = pipe_ctx->plane_res.hubp; 905 unsigned int panel_inst = 0; 906 907 if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, 908 pipe_ctx->stream->link, &panel_inst)) 909 return; 910 911 /* Payload: Cursor Rect is built from position & attribute 912 * x & y are obtained from postion 913 */ 914 payload->cursor_rect.x = hubp->cur_rect.x; 915 payload->cursor_rect.y = hubp->cur_rect.y; 916 /* w & h are obtained from attribute */ 917 payload->cursor_rect.width = hubp->cur_rect.w; 918 payload->cursor_rect.height = hubp->cur_rect.h; 919 920 payload->enable = hubp->pos.cur_ctl.bits.cur_enable; 921 payload->pipe_idx = p_idx; 922 payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 923 payload->panel_inst = panel_inst; 924 } 925 926 static void dc_build_cursor_position_update_payload0( 927 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx, 928 const struct hubp *hubp, const struct dpp *dpp) 929 { 930 /* Hubp */ 931 pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw; 932 pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw; 933 pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw; 934 pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw; 935 936 /* dpp */ 937 pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw; 938 pl->position_cfg.pipe_idx = p_idx; 939 } 940 941 static void dc_build_cursor_attribute_update_payload1( 942 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx, 943 const struct hubp *hubp, const struct dpp *dpp) 944 { 945 /* Hubp */ 946 pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH; 947 pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR; 948 pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw; 949 pl_A->aHubp.size.raw = hubp->att.size.raw; 950 pl_A->aHubp.settings.raw = hubp->att.settings.raw; 951 952 /* dpp */ 953 pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw; 954 } 955 956 /** 957 * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command 958 * 959 * @pCtx: [in] pipe context 960 * @pipe_idx: [in] pipe index 961 * 962 * This function would store the cursor related information and pass it into 963 * dmub 964 */ 965 void dc_send_update_cursor_info_to_dmu( 966 struct pipe_ctx *pCtx, uint8_t pipe_idx) 967 { 968 union dmub_rb_cmd cmd[2]; 969 union dmub_cmd_update_cursor_info_data *update_cursor_info_0 = 970 &cmd[0].update_cursor_info.update_cursor_info_data; 971 972 memset(cmd, 0, sizeof(cmd)); 973 974 if (!dc_dmub_should_update_cursor_data(pCtx)) 975 return; 976 /* 977 * Since we use multi_cmd_pending for dmub command, the 2nd command is 978 * only assigned to store cursor attributes info. 979 * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other 980 * is to store cursor position info. 981 * 982 * Command heaer type must be the same type if using multi_cmd_pending. 983 * Besides, while process 2nd command in DMU, the sub type is useless. 984 * So it's meanless to pass the sub type header with different type. 985 */ 986 987 { 988 /* Build Payload#0 Header */ 989 cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 990 cmd[0].update_cursor_info.header.payload_bytes = 991 sizeof(cmd[0].update_cursor_info.update_cursor_info_data); 992 cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd 993 994 /* Prepare Payload */ 995 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info_0->payload0); 996 997 dc_build_cursor_position_update_payload0(&update_cursor_info_0->payload0, pipe_idx, 998 pCtx->plane_res.hubp, pCtx->plane_res.dpp); 999 } 1000 { 1001 /* Build Payload#1 Header */ 1002 cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 1003 cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg); 1004 cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command. 1005 1006 dc_build_cursor_attribute_update_payload1( 1007 &cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg, 1008 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1009 1010 /* Combine 2nd cmds update_curosr_info to DMU */ 1011 dm_execute_dmub_cmd_list(pCtx->stream->ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT); 1012 } 1013 } 1014 1015 bool dc_dmub_check_min_version(struct dmub_srv *srv) 1016 { 1017 if (!srv->hw_funcs.is_psrsu_supported) 1018 return true; 1019 return srv->hw_funcs.is_psrsu_supported(srv); 1020 } 1021