13a1627b0SNicholas Kazlauskas /* 23a1627b0SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 33a1627b0SNicholas Kazlauskas * 43a1627b0SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 53a1627b0SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 63a1627b0SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 73a1627b0SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 83a1627b0SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 93a1627b0SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 103a1627b0SNicholas Kazlauskas * 113a1627b0SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 123a1627b0SNicholas Kazlauskas * all copies or substantial portions of the Software. 133a1627b0SNicholas Kazlauskas * 143a1627b0SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 153a1627b0SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 163a1627b0SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 173a1627b0SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 183a1627b0SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 193a1627b0SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 203a1627b0SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 213a1627b0SNicholas Kazlauskas * 223a1627b0SNicholas Kazlauskas * Authors: AMD 233a1627b0SNicholas Kazlauskas * 243a1627b0SNicholas Kazlauskas */ 253a1627b0SNicholas Kazlauskas 263a1627b0SNicholas Kazlauskas #include "dc.h" 273a1627b0SNicholas Kazlauskas #include "dc_dmub_srv.h" 28cdca3f21SAnthony Koo #include "../dmub/dmub_srv.h" 2970732504SYongqiang Sun #include "dm_helpers.h" 30c2fbe663SFelipe Clark #include "dc_hw_types.h" 31c2fbe663SFelipe Clark #include "core_types.h" 32fbe43dcdSAlvin Lee #include "../basics/conversion.h" 33b73353f7SMax Tseng #include "cursor_reg_cache.h" 343a1627b0SNicholas Kazlauskas 35ecdfc5c9SNicholas Kazlauskas #define CTX dc_dmub_srv->ctx 36ecdfc5c9SNicholas Kazlauskas #define DC_LOGGER CTX->logger 37ecdfc5c9SNicholas Kazlauskas 383a1627b0SNicholas Kazlauskas static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, 393a1627b0SNicholas Kazlauskas struct dmub_srv *dmub) 403a1627b0SNicholas Kazlauskas { 413a1627b0SNicholas Kazlauskas dc_srv->dmub = dmub; 423a1627b0SNicholas Kazlauskas dc_srv->ctx = dc->ctx; 433a1627b0SNicholas Kazlauskas } 443a1627b0SNicholas Kazlauskas 453a1627b0SNicholas Kazlauskas struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) 463a1627b0SNicholas Kazlauskas { 473a1627b0SNicholas Kazlauskas struct dc_dmub_srv *dc_srv = 483a1627b0SNicholas Kazlauskas kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL); 493a1627b0SNicholas Kazlauskas 503a1627b0SNicholas Kazlauskas if (dc_srv == NULL) { 513a1627b0SNicholas Kazlauskas BREAK_TO_DEBUGGER(); 523a1627b0SNicholas Kazlauskas return NULL; 533a1627b0SNicholas Kazlauskas } 543a1627b0SNicholas Kazlauskas 553a1627b0SNicholas Kazlauskas dc_dmub_srv_construct(dc_srv, dc, dmub); 563a1627b0SNicholas Kazlauskas 573a1627b0SNicholas Kazlauskas return dc_srv; 583a1627b0SNicholas Kazlauskas } 593a1627b0SNicholas Kazlauskas 603a1627b0SNicholas Kazlauskas void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv) 613a1627b0SNicholas Kazlauskas { 623a1627b0SNicholas Kazlauskas if (*dmub_srv) { 633a1627b0SNicholas Kazlauskas kfree(*dmub_srv); 643a1627b0SNicholas Kazlauskas *dmub_srv = NULL; 653a1627b0SNicholas Kazlauskas } 663a1627b0SNicholas Kazlauskas } 673a1627b0SNicholas Kazlauskas 683a1627b0SNicholas Kazlauskas void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) 693a1627b0SNicholas Kazlauskas { 703a1627b0SNicholas Kazlauskas struct dmub_srv *dmub = dc_dmub_srv->dmub; 713a1627b0SNicholas Kazlauskas struct dc_context *dc_ctx = dc_dmub_srv->ctx; 723a1627b0SNicholas Kazlauskas enum dmub_status status; 733a1627b0SNicholas Kazlauskas 743a1627b0SNicholas Kazlauskas status = dmub_srv_wait_for_idle(dmub, 100000); 752631ac1aSAshley Thomas if (status != DMUB_STATUS_OK) { 763a1627b0SNicholas Kazlauskas DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); 772631ac1aSAshley Thomas dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 782631ac1aSAshley Thomas } 793a1627b0SNicholas Kazlauskas } 803a1627b0SNicholas Kazlauskas 81d493a024SAlvin Lee void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv) 82d493a024SAlvin Lee { 83d493a024SAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub; 84d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx; 85d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK; 86d493a024SAlvin Lee 87d493a024SAlvin Lee status = dmub_srv_clear_inbox0_ack(dmub); 88d493a024SAlvin Lee if (status != DMUB_STATUS_OK) { 89d493a024SAlvin Lee DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status); 90d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv); 91d493a024SAlvin Lee } 92d493a024SAlvin Lee } 93d493a024SAlvin Lee 94d493a024SAlvin Lee void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv) 95d493a024SAlvin Lee { 96d493a024SAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub; 97d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx; 98d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK; 99d493a024SAlvin Lee 100d493a024SAlvin Lee status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); 101d493a024SAlvin Lee if (status != DMUB_STATUS_OK) { 102d493a024SAlvin Lee DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n"); 103d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv); 104d493a024SAlvin Lee } 105d493a024SAlvin Lee } 106d493a024SAlvin Lee 107f2973d2aSAlvin Lee void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, 108f2973d2aSAlvin Lee union dmub_inbox0_data_register data) 109f2973d2aSAlvin Lee { 110f2973d2aSAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub; 111d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx; 112d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK; 113d493a024SAlvin Lee 114d493a024SAlvin Lee status = dmub_srv_send_inbox0_cmd(dmub, data); 115d493a024SAlvin Lee if (status != DMUB_STATUS_OK) { 116d493a024SAlvin Lee DC_ERROR("Error sending INBOX0 cmd\n"); 117d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv); 118d493a024SAlvin Lee } 119f2973d2aSAlvin Lee } 120f2973d2aSAlvin Lee 121e97cc04fSJosip Pavic bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 122ecdfc5c9SNicholas Kazlauskas { 123e97cc04fSJosip Pavic return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type); 124e97cc04fSJosip Pavic } 125e97cc04fSJosip Pavic 126e97cc04fSJosip Pavic bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type) 127e97cc04fSJosip Pavic { 12844407010SHarshit Mogalapalli struct dc_context *dc_ctx; 129ecdfc5c9SNicholas Kazlauskas struct dmub_srv *dmub; 130ecdfc5c9SNicholas Kazlauskas enum dmub_status status; 131e97cc04fSJosip Pavic int i; 132ecdfc5c9SNicholas Kazlauskas 133ecdfc5c9SNicholas Kazlauskas if (!dc_dmub_srv || !dc_dmub_srv->dmub) 134ecdfc5c9SNicholas Kazlauskas return false; 135ecdfc5c9SNicholas Kazlauskas 13644407010SHarshit Mogalapalli dc_ctx = dc_dmub_srv->ctx; 137ecdfc5c9SNicholas Kazlauskas dmub = dc_dmub_srv->dmub; 138ecdfc5c9SNicholas Kazlauskas 139e97cc04fSJosip Pavic for (i = 0 ; i < count; i++) { 140e97cc04fSJosip Pavic // Queue command 141e97cc04fSJosip Pavic status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 142e97cc04fSJosip Pavic 143522b9a5dSJosip Pavic if (status == DMUB_STATUS_QUEUE_FULL) { 144522b9a5dSJosip Pavic /* Execute and wait for queue to become empty again. */ 145522b9a5dSJosip Pavic dmub_srv_cmd_execute(dmub); 146522b9a5dSJosip Pavic dmub_srv_wait_for_idle(dmub, 100000); 147522b9a5dSJosip Pavic 148522b9a5dSJosip Pavic /* Requeue the command. */ 149522b9a5dSJosip Pavic status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 150522b9a5dSJosip Pavic } 151522b9a5dSJosip Pavic 152e97cc04fSJosip Pavic if (status != DMUB_STATUS_OK) { 153e97cc04fSJosip Pavic DC_ERROR("Error queueing DMUB command: status=%d\n", status); 154e97cc04fSJosip Pavic dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 155e97cc04fSJosip Pavic return false; 156e97cc04fSJosip Pavic } 157e97cc04fSJosip Pavic } 158e97cc04fSJosip Pavic 159e97cc04fSJosip Pavic status = dmub_srv_cmd_execute(dmub); 160e97cc04fSJosip Pavic if (status != DMUB_STATUS_OK) { 161e97cc04fSJosip Pavic DC_ERROR("Error starting DMUB execution: status=%d\n", status); 162e97cc04fSJosip Pavic dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 163e97cc04fSJosip Pavic return false; 164e97cc04fSJosip Pavic } 165e97cc04fSJosip Pavic 166e97cc04fSJosip Pavic // Wait for DMUB to process command 167e97cc04fSJosip Pavic if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) { 168e97cc04fSJosip Pavic status = dmub_srv_wait_for_idle(dmub, 100000); 169e97cc04fSJosip Pavic 170ecdfc5c9SNicholas Kazlauskas if (status != DMUB_STATUS_OK) { 171ecdfc5c9SNicholas Kazlauskas DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 172f36f2648SCruise Hung dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 173ecdfc5c9SNicholas Kazlauskas return false; 174ecdfc5c9SNicholas Kazlauskas } 175ecdfc5c9SNicholas Kazlauskas 176e97cc04fSJosip Pavic // Copy data back from ring buffer into command 177e97cc04fSJosip Pavic if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) 178e97cc04fSJosip Pavic dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list); 179e97cc04fSJosip Pavic } 180e97cc04fSJosip Pavic 181ecdfc5c9SNicholas Kazlauskas return true; 182ecdfc5c9SNicholas Kazlauskas } 183ecdfc5c9SNicholas Kazlauskas 184499e4b1cSEric Yang bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv) 1853a1627b0SNicholas Kazlauskas { 186499e4b1cSEric Yang struct dmub_srv *dmub; 187b94f1cc9STom Rix struct dc_context *dc_ctx; 188b94f1cc9STom Rix union dmub_fw_boot_status boot_status; 189b94f1cc9STom Rix enum dmub_status status; 1903a1627b0SNicholas Kazlauskas 191499e4b1cSEric Yang if (!dc_dmub_srv || !dc_dmub_srv->dmub) 192499e4b1cSEric Yang return false; 193a6e4da40SNicholas Kazlauskas 194499e4b1cSEric Yang dmub = dc_dmub_srv->dmub; 195b94f1cc9STom Rix dc_ctx = dc_dmub_srv->ctx; 196a6e4da40SNicholas Kazlauskas 197b94f1cc9STom Rix status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 198b94f1cc9STom Rix if (status != DMUB_STATUS_OK) { 199b94f1cc9STom Rix DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 200b94f1cc9STom Rix return false; 201b94f1cc9STom Rix } 202b94f1cc9STom Rix 203b94f1cc9STom Rix return boot_status.bits.optimized_init_done; 2043a1627b0SNicholas Kazlauskas } 2050825d965SEric Yang 2060825d965SEric Yang bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 2070825d965SEric Yang unsigned int stream_mask) 2080825d965SEric Yang { 2090825d965SEric Yang struct dmub_srv *dmub; 2100825d965SEric Yang const uint32_t timeout = 30; 2110825d965SEric Yang 2120825d965SEric Yang if (!dc_dmub_srv || !dc_dmub_srv->dmub) 2130825d965SEric Yang return false; 2140825d965SEric Yang 2150825d965SEric Yang dmub = dc_dmub_srv->dmub; 2160825d965SEric Yang 2170825d965SEric Yang return dmub_srv_send_gpint_command( 2180825d965SEric Yang dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, 2190825d965SEric Yang stream_mask, timeout) == DMUB_STATUS_OK; 2200825d965SEric Yang } 2218fe44c08SAlex Deucher 222b04cb192SNicholas Kazlauskas bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) 223b04cb192SNicholas Kazlauskas { 224b04cb192SNicholas Kazlauskas struct dmub_srv *dmub; 225b04cb192SNicholas Kazlauskas struct dc_context *dc_ctx; 226b04cb192SNicholas Kazlauskas union dmub_fw_boot_status boot_status; 227b04cb192SNicholas Kazlauskas enum dmub_status status; 228b04cb192SNicholas Kazlauskas 229b04cb192SNicholas Kazlauskas if (!dc_dmub_srv || !dc_dmub_srv->dmub) 230b04cb192SNicholas Kazlauskas return false; 231b04cb192SNicholas Kazlauskas 232b04cb192SNicholas Kazlauskas dmub = dc_dmub_srv->dmub; 233b04cb192SNicholas Kazlauskas dc_ctx = dc_dmub_srv->ctx; 234b04cb192SNicholas Kazlauskas 235b04cb192SNicholas Kazlauskas status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 236b04cb192SNicholas Kazlauskas if (status != DMUB_STATUS_OK) { 237b04cb192SNicholas Kazlauskas DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 238b04cb192SNicholas Kazlauskas return false; 239b04cb192SNicholas Kazlauskas } 240b04cb192SNicholas Kazlauskas 241b04cb192SNicholas Kazlauskas return boot_status.bits.restore_required; 242b04cb192SNicholas Kazlauskas } 24370732504SYongqiang Sun 2446804287bSYongqiang Sun bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) 24570732504SYongqiang Sun { 24670732504SYongqiang Sun struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; 2476804287bSYongqiang Sun return dmub_srv_get_outbox0_msg(dmub, entry); 24870732504SYongqiang Sun } 24970732504SYongqiang Sun 25070732504SYongqiang Sun void dc_dmub_trace_event_control(struct dc *dc, bool enable) 25170732504SYongqiang Sun { 25281927e28SJude Shih dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); 25370732504SYongqiang Sun } 2542631ac1aSAshley Thomas 25500fa7f03SRodrigo Siqueira void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) 25600fa7f03SRodrigo Siqueira { 25700fa7f03SRodrigo Siqueira union dmub_rb_cmd cmd = { 0 }; 25800fa7f03SRodrigo Siqueira 25900fa7f03SRodrigo Siqueira cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 26000fa7f03SRodrigo Siqueira cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE; 26100fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 26200fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 26300fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 26400fa7f03SRodrigo Siqueira 26500fa7f03SRodrigo Siqueira cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 26600fa7f03SRodrigo Siqueira 26700fa7f03SRodrigo Siqueira // Send the command to the DMCUB. 268e97cc04fSJosip Pavic dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 26900fa7f03SRodrigo Siqueira } 27000fa7f03SRodrigo Siqueira 271319568d7SAlvin Lee void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) 272319568d7SAlvin Lee { 273319568d7SAlvin Lee union dmub_rb_cmd cmd = { 0 }; 274319568d7SAlvin Lee 275319568d7SAlvin Lee cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 2769f5171ceSAlvin Lee cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER; 277319568d7SAlvin Lee cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 278319568d7SAlvin Lee 279319568d7SAlvin Lee cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 280319568d7SAlvin Lee 281319568d7SAlvin Lee // Send the command to the DMCUB. 282e97cc04fSJosip Pavic dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 283319568d7SAlvin Lee } 284319568d7SAlvin Lee 28584900aeeSAlex Deucher static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) 28600fa7f03SRodrigo Siqueira { 28700fa7f03SRodrigo Siqueira uint8_t pipes = 0; 28800fa7f03SRodrigo Siqueira int i = 0; 28900fa7f03SRodrigo Siqueira 29000fa7f03SRodrigo Siqueira for (i = 0; i < MAX_PIPES; i++) { 29100fa7f03SRodrigo Siqueira struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 29200fa7f03SRodrigo Siqueira 29300fa7f03SRodrigo Siqueira if (pipe->stream == stream && pipe->stream_res.tg) 29400fa7f03SRodrigo Siqueira pipes = i; 29500fa7f03SRodrigo Siqueira } 29600fa7f03SRodrigo Siqueira return pipes; 29700fa7f03SRodrigo Siqueira } 29800fa7f03SRodrigo Siqueira 2994ed79308SAlvin Lee static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context, 3004ed79308SAlvin Lee struct pipe_ctx *head_pipe, 3014ed79308SAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data) 30200fa7f03SRodrigo Siqueira { 3034ed79308SAlvin Lee int j; 304b0d58d11SAlvin Lee int pipe_idx = 0; 30500fa7f03SRodrigo Siqueira 306b0d58d11SAlvin Lee fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; 3074ed79308SAlvin Lee for (j = 0; j < dc->res_pool->pipe_count; j++) { 3084ed79308SAlvin Lee struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j]; 30900fa7f03SRodrigo Siqueira 3104ed79308SAlvin Lee if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) { 311b0d58d11SAlvin Lee fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; 31200fa7f03SRodrigo Siqueira } 31300fa7f03SRodrigo Siqueira } 314b0d58d11SAlvin Lee fams_pipe_data->pipe_count = pipe_idx; 31500fa7f03SRodrigo Siqueira } 31600fa7f03SRodrigo Siqueira 31700fa7f03SRodrigo Siqueira bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) 31800fa7f03SRodrigo Siqueira { 31900fa7f03SRodrigo Siqueira union dmub_rb_cmd cmd = { 0 }; 32000fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; 3214ed79308SAlvin Lee int i = 0, k = 0; 32200fa7f03SRodrigo Siqueira int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. 32345a92f45Ssunliming uint8_t visual_confirm_enabled; 3240289e0edSAlvin Lee int pipe_idx = 0; 32500fa7f03SRodrigo Siqueira 32600fa7f03SRodrigo Siqueira if (dc == NULL) 32700fa7f03SRodrigo Siqueira return false; 32800fa7f03SRodrigo Siqueira 32945a92f45Ssunliming visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; 33045a92f45Ssunliming 33100fa7f03SRodrigo Siqueira // Format command. 33200fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 33300fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL; 33400fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate; 33500fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; 33600fa7f03SRodrigo Siqueira 3370289e0edSAlvin Lee if (should_manage_pstate) { 3380289e0edSAlvin Lee for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3390289e0edSAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 3400289e0edSAlvin Lee 3410289e0edSAlvin Lee if (!pipe->stream) 3420289e0edSAlvin Lee continue; 3430289e0edSAlvin Lee 3440289e0edSAlvin Lee /* If FAMS is being used to support P-State and there is a stream 3450289e0edSAlvin Lee * that does not use FAMS, we are in an FPO + VActive scenario. 3460289e0edSAlvin Lee * Assign vactive stretch margin in this case. 3470289e0edSAlvin Lee */ 3480289e0edSAlvin Lee if (!pipe->stream->fpo_in_use) { 3490289e0edSAlvin Lee cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us; 3500289e0edSAlvin Lee break; 3510289e0edSAlvin Lee } 3520289e0edSAlvin Lee pipe_idx++; 3530289e0edSAlvin Lee } 3540289e0edSAlvin Lee } 3550289e0edSAlvin Lee 3564ed79308SAlvin Lee for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { 3574ed79308SAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 35800fa7f03SRodrigo Siqueira 3594ed79308SAlvin Lee if (!pipe->top_pipe && !pipe->prev_odm_pipe && pipe->stream && pipe->stream->fpo_in_use) { 3604ed79308SAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 3614ed79308SAlvin Lee uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000; 3624ed79308SAlvin Lee 3634ed79308SAlvin Lee config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz; 3644ed79308SAlvin Lee config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz; 3654ed79308SAlvin Lee config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps; 3664ed79308SAlvin Lee config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream); 3674ed79308SAlvin Lee dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]); 3684ed79308SAlvin Lee k++; 36900fa7f03SRodrigo Siqueira } 3704ed79308SAlvin Lee } 37100fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.payload_bytes = 37200fa7f03SRodrigo Siqueira sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header); 37300fa7f03SRodrigo Siqueira 37400fa7f03SRodrigo Siqueira // Send the command to the DMCUB. 375e97cc04fSJosip Pavic dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 37600fa7f03SRodrigo Siqueira 37700fa7f03SRodrigo Siqueira return true; 37800fa7f03SRodrigo Siqueira } 37900fa7f03SRodrigo Siqueira 380e97cc04fSJosip Pavic void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv) 381ac2e555eSAurabindo Pillai { 382ac2e555eSAurabindo Pillai union dmub_rb_cmd cmd = { 0 }; 383ac2e555eSAurabindo Pillai 384*a243e38eSNicholas Kazlauskas if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation) 385*a243e38eSNicholas Kazlauskas return; 386*a243e38eSNicholas Kazlauskas 387ac2e555eSAurabindo Pillai memset(&cmd, 0, sizeof(cmd)); 388ac2e555eSAurabindo Pillai 389ac2e555eSAurabindo Pillai /* Prepare fw command */ 390ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; 391ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.sub_type = 0; 392ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.ret_status = 1; 393ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); 394ac2e555eSAurabindo Pillai 395ac2e555eSAurabindo Pillai /* If command was processed, copy feature caps to dmub srv */ 396e97cc04fSJosip Pavic if (dm_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 397ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.ret_status == 0) { 398e97cc04fSJosip Pavic memcpy(&dc_dmub_srv->dmub->feature_caps, 399ac2e555eSAurabindo Pillai &cmd.query_feature_caps.query_feature_caps_data, 400ac2e555eSAurabindo Pillai sizeof(struct dmub_feature_caps)); 401ac2e555eSAurabindo Pillai } 402ac2e555eSAurabindo Pillai } 403ac2e555eSAurabindo Pillai 404b09c1fffSLeo (Hanghong) Ma void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx) 405b09c1fffSLeo (Hanghong) Ma { 406b09c1fffSLeo (Hanghong) Ma union dmub_rb_cmd cmd = { 0 }; 407b09c1fffSLeo (Hanghong) Ma unsigned int panel_inst = 0; 408b09c1fffSLeo (Hanghong) Ma 409b09c1fffSLeo (Hanghong) Ma dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst); 410b09c1fffSLeo (Hanghong) Ma 411b09c1fffSLeo (Hanghong) Ma memset(&cmd, 0, sizeof(cmd)); 412b09c1fffSLeo (Hanghong) Ma 413b09c1fffSLeo (Hanghong) Ma // Prepare fw command 414b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR; 415b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.sub_type = 0; 416b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.ret_status = 1; 417b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data); 418b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst; 419b09c1fffSLeo (Hanghong) Ma 420b09c1fffSLeo (Hanghong) Ma // If command was processed, copy feature caps to dmub srv 421e97cc04fSJosip Pavic if (dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 422b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.ret_status == 0) { 423b09c1fffSLeo (Hanghong) Ma memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color, 424b09c1fffSLeo (Hanghong) Ma &cmd.visual_confirm_color.visual_confirm_color_data, 425b09c1fffSLeo (Hanghong) Ma sizeof(struct dmub_visual_confirm_color)); 426b09c1fffSLeo (Hanghong) Ma } 427b09c1fffSLeo (Hanghong) Ma } 428b09c1fffSLeo (Hanghong) Ma 42985f4bc0cSAlvin Lee /** 4306be153dcSRodrigo Siqueira * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command 43185f4bc0cSAlvin Lee * 4326be153dcSRodrigo Siqueira * @dc: [in] current dc state 4336be153dcSRodrigo Siqueira * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 4346be153dcSRodrigo Siqueira * @vblank_pipe: [in] pipe_ctx for the DRR pipe 4356be153dcSRodrigo Siqueira * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info 4366be153dcSRodrigo Siqueira * 4376be153dcSRodrigo Siqueira * Populate the DMCUB SubVP command with DRR pipe info. All the information 4386be153dcSRodrigo Siqueira * required for calculating the SubVP + DRR microschedule is populated here. 43985f4bc0cSAlvin Lee * 44085f4bc0cSAlvin Lee * High level algorithm: 44185f4bc0cSAlvin Lee * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 44285f4bc0cSAlvin Lee * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule 44385f4bc0cSAlvin Lee * 3. Populate the drr_info with the min and max supported vtotal values 44485f4bc0cSAlvin Lee */ 44585f4bc0cSAlvin Lee static void populate_subvp_cmd_drr_info(struct dc *dc, 44685f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipe, 44785f4bc0cSAlvin Lee struct pipe_ctx *vblank_pipe, 44885f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data) 44985f4bc0cSAlvin Lee { 45085f4bc0cSAlvin Lee struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 45185f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 45285f4bc0cSAlvin Lee struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 453410e7474SAlvin Lee uint16_t drr_frame_us = 0; 454410e7474SAlvin Lee uint16_t min_drr_supported_us = 0; 455410e7474SAlvin Lee uint16_t max_drr_supported_us = 0; 456410e7474SAlvin Lee uint16_t max_drr_vblank_us = 0; 457410e7474SAlvin Lee uint16_t max_drr_mallregion_us = 0; 458410e7474SAlvin Lee uint16_t mall_region_us = 0; 459410e7474SAlvin Lee uint16_t prefetch_us = 0; 460410e7474SAlvin Lee uint16_t subvp_active_us = 0; 461410e7474SAlvin Lee uint16_t drr_active_us = 0; 462410e7474SAlvin Lee uint16_t min_vtotal_supported = 0; 463410e7474SAlvin Lee uint16_t max_vtotal_supported = 0; 46485f4bc0cSAlvin Lee 46585f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; 46685f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping 46785f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now 46885f4bc0cSAlvin Lee 469410e7474SAlvin Lee drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000), 470410e7474SAlvin Lee (((uint64_t)drr_timing->pix_clk_100hz * 100))); 47185f4bc0cSAlvin Lee // P-State allow width and FW delays already included phantom_timing->v_addressable 472410e7474SAlvin Lee mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000), 473410e7474SAlvin Lee (((uint64_t)phantom_timing->pix_clk_100hz * 100))); 47485f4bc0cSAlvin Lee min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 475410e7474SAlvin Lee min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us), 476410e7474SAlvin Lee (((uint64_t)drr_timing->h_total * 1000000))); 47785f4bc0cSAlvin Lee 478410e7474SAlvin Lee prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000), 479410e7474SAlvin Lee (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 480410e7474SAlvin Lee subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000), 481410e7474SAlvin Lee (((uint64_t)main_timing->pix_clk_100hz * 100))); 482410e7474SAlvin Lee drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000), 483410e7474SAlvin Lee (((uint64_t)drr_timing->pix_clk_100hz * 100))); 484964d6416SAlvin Lee max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - 485964d6416SAlvin Lee dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us; 486964d6416SAlvin Lee max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us; 48785f4bc0cSAlvin Lee max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; 488410e7474SAlvin Lee max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us), 489410e7474SAlvin Lee (((uint64_t)drr_timing->h_total * 1000000))); 49085f4bc0cSAlvin Lee 491964d6416SAlvin Lee /* When calculating the max vtotal supported for SubVP + DRR cases, add 492964d6416SAlvin Lee * margin due to possible rounding errors (being off by 1 line in the 493964d6416SAlvin Lee * FW calculation can incorrectly push the P-State switch to wait 1 frame 494964d6416SAlvin Lee * longer). 495964d6416SAlvin Lee */ 496964d6416SAlvin Lee max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us; 497964d6416SAlvin Lee 49885f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; 49985f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; 500ae7169a9SAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us; 50185f4bc0cSAlvin Lee } 50285f4bc0cSAlvin Lee 50385f4bc0cSAlvin Lee /** 5046be153dcSRodrigo Siqueira * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command 50585f4bc0cSAlvin Lee * 5066be153dcSRodrigo Siqueira * @dc: [in] current dc state 5076be153dcSRodrigo Siqueira * @context: [in] new dc state 5086be153dcSRodrigo Siqueira * @cmd: [in] DMUB cmd to be populated with SubVP info 5096be153dcSRodrigo Siqueira * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe 5106be153dcSRodrigo Siqueira * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 51185f4bc0cSAlvin Lee * 5126be153dcSRodrigo Siqueira * Populate the DMCUB SubVP command with VBLANK pipe info. All the information 5136be153dcSRodrigo Siqueira * required to calculate the microschedule for SubVP + VBLANK case is stored in 5146be153dcSRodrigo Siqueira * the pipe_data (subvp_data and vblank_data). Also check if the VBLANK pipe 5156be153dcSRodrigo Siqueira * is a DRR display -- if it is make a call to populate drr_info. 51685f4bc0cSAlvin Lee */ 51785f4bc0cSAlvin Lee static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, 51885f4bc0cSAlvin Lee struct dc_state *context, 51985f4bc0cSAlvin Lee union dmub_rb_cmd *cmd, 52085f4bc0cSAlvin Lee struct pipe_ctx *vblank_pipe, 52185f4bc0cSAlvin Lee uint8_t cmd_pipe_index) 52285f4bc0cSAlvin Lee { 52385f4bc0cSAlvin Lee uint32_t i; 52485f4bc0cSAlvin Lee struct pipe_ctx *pipe = NULL; 52585f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 52685f4bc0cSAlvin Lee &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 52785f4bc0cSAlvin Lee 52885f4bc0cSAlvin Lee // Find the SubVP pipe 52985f4bc0cSAlvin Lee for (i = 0; i < dc->res_pool->pipe_count; i++) { 53085f4bc0cSAlvin Lee pipe = &context->res_ctx.pipe_ctx[i]; 53185f4bc0cSAlvin Lee 53285f4bc0cSAlvin Lee // We check for master pipe, but it shouldn't matter since we only need 53385f4bc0cSAlvin Lee // the pipe for timing info (stream should be same for any pipe splits) 53485f4bc0cSAlvin Lee if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 53585f4bc0cSAlvin Lee continue; 53685f4bc0cSAlvin Lee 53785f4bc0cSAlvin Lee // Find the SubVP pipe 53885f4bc0cSAlvin Lee if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 53985f4bc0cSAlvin Lee break; 54085f4bc0cSAlvin Lee } 54185f4bc0cSAlvin Lee 54285f4bc0cSAlvin Lee pipe_data->mode = VBLANK; 54385f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; 54485f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - 54585f4bc0cSAlvin Lee vblank_pipe->stream->timing.v_front_porch; 54685f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; 54785f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; 54885f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; 54985f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; 55085f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_end = 55185f4bc0cSAlvin Lee vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; 55285f4bc0cSAlvin Lee 55385f4bc0cSAlvin Lee if (vblank_pipe->stream->ignore_msa_timing_param) 55485f4bc0cSAlvin Lee populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data); 55585f4bc0cSAlvin Lee } 55685f4bc0cSAlvin Lee 55785f4bc0cSAlvin Lee /** 5586be153dcSRodrigo Siqueira * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case 55985f4bc0cSAlvin Lee * 5606be153dcSRodrigo Siqueira * @dc: [in] current dc state 5616be153dcSRodrigo Siqueira * @context: [in] new dc state 5626be153dcSRodrigo Siqueira * @cmd: [in] DMUB cmd to be populated with SubVP info 5636be153dcSRodrigo Siqueira * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2) 56485f4bc0cSAlvin Lee * 5656be153dcSRodrigo Siqueira * For SubVP + SubVP, we use a single vertical interrupt to start the 5666be153dcSRodrigo Siqueira * microschedule for both SubVP pipes. In order for this to work correctly, the 5676be153dcSRodrigo Siqueira * MALL REGION of both SubVP pipes must start at the same time. This function 5686be153dcSRodrigo Siqueira * lengthens the prefetch end to mall start delay of the SubVP pipe that has 5696be153dcSRodrigo Siqueira * the shorter prefetch so that both MALL REGION's will start at the same time. 57085f4bc0cSAlvin Lee */ 57185f4bc0cSAlvin Lee static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, 57285f4bc0cSAlvin Lee struct dc_state *context, 57385f4bc0cSAlvin Lee union dmub_rb_cmd *cmd, 57485f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipes[]) 57585f4bc0cSAlvin Lee { 57685f4bc0cSAlvin Lee uint32_t subvp0_prefetch_us = 0; 57785f4bc0cSAlvin Lee uint32_t subvp1_prefetch_us = 0; 57885f4bc0cSAlvin Lee uint32_t prefetch_delta_us = 0; 57985f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing; 58085f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing; 58185f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL; 58285f4bc0cSAlvin Lee 583410e7474SAlvin Lee subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * 584410e7474SAlvin Lee (uint64_t)phantom_timing0->h_total * 1000000), 585410e7474SAlvin Lee (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 586410e7474SAlvin Lee subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * 587410e7474SAlvin Lee (uint64_t)phantom_timing1->h_total * 1000000), 588410e7474SAlvin Lee (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 58985f4bc0cSAlvin Lee 59085f4bc0cSAlvin Lee // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) 59185f4bc0cSAlvin Lee // should increase it's prefetch time to match the other 59285f4bc0cSAlvin Lee if (subvp0_prefetch_us > subvp1_prefetch_us) { 59385f4bc0cSAlvin Lee pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; 59485f4bc0cSAlvin Lee prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; 59585f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 596410e7474SAlvin Lee div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 597410e7474SAlvin Lee ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), 598410e7474SAlvin Lee ((uint64_t)phantom_timing1->h_total * 1000000)); 599410e7474SAlvin Lee 60085f4bc0cSAlvin Lee } else if (subvp1_prefetch_us > subvp0_prefetch_us) { 60185f4bc0cSAlvin Lee pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; 60285f4bc0cSAlvin Lee prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; 60385f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 604410e7474SAlvin Lee div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 605410e7474SAlvin Lee ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), 606410e7474SAlvin Lee ((uint64_t)phantom_timing0->h_total * 1000000)); 60785f4bc0cSAlvin Lee } 60885f4bc0cSAlvin Lee } 60985f4bc0cSAlvin Lee 61085f4bc0cSAlvin Lee /** 6110645b7a6SJiapeng Chong * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command 61285f4bc0cSAlvin Lee * 6136be153dcSRodrigo Siqueira * @dc: [in] current dc state 6146be153dcSRodrigo Siqueira * @context: [in] new dc state 6156be153dcSRodrigo Siqueira * @cmd: [in] DMUB cmd to be populated with SubVP info 6166be153dcSRodrigo Siqueira * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 6176be153dcSRodrigo Siqueira * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 61885f4bc0cSAlvin Lee * 6196be153dcSRodrigo Siqueira * Populate the DMCUB SubVP command with SubVP pipe info. All the information 6206be153dcSRodrigo Siqueira * required to calculate the microschedule for the SubVP pipe is stored in the 6216be153dcSRodrigo Siqueira * pipe_data of the DMCUB SubVP command. 62285f4bc0cSAlvin Lee */ 62385f4bc0cSAlvin Lee static void populate_subvp_cmd_pipe_info(struct dc *dc, 62485f4bc0cSAlvin Lee struct dc_state *context, 62585f4bc0cSAlvin Lee union dmub_rb_cmd *cmd, 62685f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipe, 62785f4bc0cSAlvin Lee uint8_t cmd_pipe_index) 62885f4bc0cSAlvin Lee { 62985f4bc0cSAlvin Lee uint32_t j; 63085f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 63185f4bc0cSAlvin Lee &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 63285f4bc0cSAlvin Lee struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 63385f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 6347857825bSAlvin Lee uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den; 63585f4bc0cSAlvin Lee 63685f4bc0cSAlvin Lee pipe_data->mode = SUBVP; 63785f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; 63885f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; 63985f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; 64085f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.main_vblank_start = 64185f4bc0cSAlvin Lee main_timing->v_total - main_timing->v_front_porch; 64285f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.main_vblank_end = 64385f4bc0cSAlvin Lee main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; 64485f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; 6457da2bcdaSAlvin Lee pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst; 6469f5171ceSAlvin Lee pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param; 64785f4bc0cSAlvin Lee 648fbe43dcdSAlvin Lee /* Calculate the scaling factor from the src and dst height. 649fbe43dcdSAlvin Lee * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2. 650fbe43dcdSAlvin Lee * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor" 6517857825bSAlvin Lee * 6527857825bSAlvin Lee * Make sure to combine stream and plane scaling together. 653fbe43dcdSAlvin Lee */ 6547857825bSAlvin Lee reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height, 6557857825bSAlvin Lee &out_num_stream, &out_den_stream); 6567857825bSAlvin Lee reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height, 6577857825bSAlvin Lee &out_num_plane, &out_den_plane); 6587857825bSAlvin Lee reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den); 65974f4e84dSAlvin Lee pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num; 66074f4e84dSAlvin Lee pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den; 661fbe43dcdSAlvin Lee 66285f4bc0cSAlvin Lee // Prefetch lines is equal to VACTIVE + BP + VSYNC 66385f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_lines = 66485f4bc0cSAlvin Lee phantom_timing->v_total - phantom_timing->v_front_porch; 66585f4bc0cSAlvin Lee 66685f4bc0cSAlvin Lee // Round up 66785f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 668410e7474SAlvin Lee div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 669410e7474SAlvin Lee ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 67085f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.processing_delay_lines = 671410e7474SAlvin Lee div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 672410e7474SAlvin Lee ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 673b0d6de32SAlvin Lee 674b0d6de32SAlvin Lee if (subvp_pipe->bottom_pipe) { 675b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; 676b0d6de32SAlvin Lee } else if (subvp_pipe->next_odm_pipe) { 677b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; 678b0d6de32SAlvin Lee } else { 679b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0; 680b0d6de32SAlvin Lee } 681b0d6de32SAlvin Lee 68285f4bc0cSAlvin Lee // Find phantom pipe index based on phantom stream 68385f4bc0cSAlvin Lee for (j = 0; j < dc->res_pool->pipe_count; j++) { 68485f4bc0cSAlvin Lee struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; 68585f4bc0cSAlvin Lee 68685f4bc0cSAlvin Lee if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) { 6877da2bcdaSAlvin Lee pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst; 688b0d6de32SAlvin Lee if (phantom_pipe->bottom_pipe) { 6897da2bcdaSAlvin Lee pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; 690b0d6de32SAlvin Lee } else if (phantom_pipe->next_odm_pipe) { 6917da2bcdaSAlvin Lee pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; 692b0d6de32SAlvin Lee } else { 693b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0; 694b0d6de32SAlvin Lee } 69585f4bc0cSAlvin Lee break; 69685f4bc0cSAlvin Lee } 69785f4bc0cSAlvin Lee } 69885f4bc0cSAlvin Lee } 69985f4bc0cSAlvin Lee 70085f4bc0cSAlvin Lee /** 7016be153dcSRodrigo Siqueira * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command 70285f4bc0cSAlvin Lee * 7036be153dcSRodrigo Siqueira * @dc: [in] current dc state 7046be153dcSRodrigo Siqueira * @context: [in] new dc state 70501543dcfSArthur Grillo * @enable: [in] if true enables the pipes population 70685f4bc0cSAlvin Lee * 7076be153dcSRodrigo Siqueira * This function loops through each pipe and populates the DMUB SubVP CMD info 7086be153dcSRodrigo Siqueira * based on the pipe (e.g. SubVP, VBLANK). 70985f4bc0cSAlvin Lee */ 71085f4bc0cSAlvin Lee void dc_dmub_setup_subvp_dmub_command(struct dc *dc, 71185f4bc0cSAlvin Lee struct dc_state *context, 71285f4bc0cSAlvin Lee bool enable) 71385f4bc0cSAlvin Lee { 71485f4bc0cSAlvin Lee uint8_t cmd_pipe_index = 0; 71585f4bc0cSAlvin Lee uint32_t i, pipe_idx; 71685f4bc0cSAlvin Lee uint8_t subvp_count = 0; 71785f4bc0cSAlvin Lee union dmub_rb_cmd cmd; 71885f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipes[2]; 71985f4bc0cSAlvin Lee uint32_t wm_val_refclk = 0; 72085f4bc0cSAlvin Lee 72185f4bc0cSAlvin Lee memset(&cmd, 0, sizeof(cmd)); 72285f4bc0cSAlvin Lee // FW command for SUBVP 72385f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 72485f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD; 72585f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.payload_bytes = 72685f4bc0cSAlvin Lee sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header); 72785f4bc0cSAlvin Lee 72885f4bc0cSAlvin Lee for (i = 0; i < dc->res_pool->pipe_count; i++) { 72985f4bc0cSAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 73085f4bc0cSAlvin Lee 73185f4bc0cSAlvin Lee if (!pipe->stream) 73285f4bc0cSAlvin Lee continue; 73385f4bc0cSAlvin Lee 734b0d6de32SAlvin Lee /* For SubVP pipe count, only count the top most (ODM / MPC) pipe 735b0d6de32SAlvin Lee */ 736b0d6de32SAlvin Lee if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && 73785f4bc0cSAlvin Lee pipe->stream->mall_stream_config.type == SUBVP_MAIN) 73885f4bc0cSAlvin Lee subvp_pipes[subvp_count++] = pipe; 73985f4bc0cSAlvin Lee } 74085f4bc0cSAlvin Lee 74185f4bc0cSAlvin Lee if (enable) { 74285f4bc0cSAlvin Lee // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd 74385f4bc0cSAlvin Lee for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 74485f4bc0cSAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 74585f4bc0cSAlvin Lee 74685f4bc0cSAlvin Lee if (!pipe->stream) 74785f4bc0cSAlvin Lee continue; 74885f4bc0cSAlvin Lee 749b0d6de32SAlvin Lee /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe. 750b0d6de32SAlvin Lee * Any ODM or MPC splits being used in SubVP will be handled internally in 751b0d6de32SAlvin Lee * populate_subvp_cmd_pipe_info 752b0d6de32SAlvin Lee */ 75385f4bc0cSAlvin Lee if (pipe->plane_state && pipe->stream->mall_stream_config.paired_stream && 754b0d6de32SAlvin Lee !pipe->top_pipe && !pipe->prev_odm_pipe && 75585f4bc0cSAlvin Lee pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 75685f4bc0cSAlvin Lee populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 7579bb10b7aSAyush Gupta } else if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_NONE && 7589bb10b7aSAyush Gupta !pipe->top_pipe && !pipe->prev_odm_pipe) { 75985f4bc0cSAlvin Lee // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where 76085f4bc0cSAlvin Lee // we run through DML without calculating "natural" P-state support 76185f4bc0cSAlvin Lee populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 76285f4bc0cSAlvin Lee 76385f4bc0cSAlvin Lee } 76485f4bc0cSAlvin Lee pipe_idx++; 76585f4bc0cSAlvin Lee } 76685f4bc0cSAlvin Lee if (subvp_count == 2) { 76785f4bc0cSAlvin Lee update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); 76885f4bc0cSAlvin Lee } 76985f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 77085f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; 77185f4bc0cSAlvin Lee 77285f4bc0cSAlvin Lee // Store the original watermark value for this SubVP config so we can lower it when the 77385f4bc0cSAlvin Lee // MCLK switch starts 77485f4bc0cSAlvin Lee wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * 77597997023SAlvin Lee (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; 77685f4bc0cSAlvin Lee 77785f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; 77885f4bc0cSAlvin Lee } 779e97cc04fSJosip Pavic 780e97cc04fSJosip Pavic dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 78185f4bc0cSAlvin Lee } 78285f4bc0cSAlvin Lee 7832631ac1aSAshley Thomas bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) 7842631ac1aSAshley Thomas { 7852631ac1aSAshley Thomas if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) 7862631ac1aSAshley Thomas return false; 7872631ac1aSAshley Thomas return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data); 7882631ac1aSAshley Thomas } 7892631ac1aSAshley Thomas 7902631ac1aSAshley Thomas void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 7912631ac1aSAshley Thomas { 7922631ac1aSAshley Thomas struct dmub_diagnostic_data diag_data = {0}; 7932631ac1aSAshley Thomas 7942631ac1aSAshley Thomas if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 7952631ac1aSAshley Thomas DC_LOG_ERROR("%s: invalid parameters.", __func__); 7962631ac1aSAshley Thomas return; 7972631ac1aSAshley Thomas } 7982631ac1aSAshley Thomas 7992631ac1aSAshley Thomas if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) { 8002631ac1aSAshley Thomas DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); 8012631ac1aSAshley Thomas return; 8022631ac1aSAshley Thomas } 8032631ac1aSAshley Thomas 804f36f2648SCruise Hung DC_LOG_DEBUG("DMCUB STATE:"); 805f36f2648SCruise Hung DC_LOG_DEBUG(" dmcub_version : %08x", diag_data.dmcub_version); 806f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [0] : %08x", diag_data.scratch[0]); 807f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [1] : %08x", diag_data.scratch[1]); 808f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [2] : %08x", diag_data.scratch[2]); 809f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [3] : %08x", diag_data.scratch[3]); 810f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [4] : %08x", diag_data.scratch[4]); 811f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [5] : %08x", diag_data.scratch[5]); 812f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [6] : %08x", diag_data.scratch[6]); 813f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [7] : %08x", diag_data.scratch[7]); 814f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [8] : %08x", diag_data.scratch[8]); 815f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [9] : %08x", diag_data.scratch[9]); 816f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [10] : %08x", diag_data.scratch[10]); 817f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [11] : %08x", diag_data.scratch[11]); 818f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [12] : %08x", diag_data.scratch[12]); 819f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [13] : %08x", diag_data.scratch[13]); 820f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [14] : %08x", diag_data.scratch[14]); 821f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [15] : %08x", diag_data.scratch[15]); 822f36f2648SCruise Hung DC_LOG_DEBUG(" pc : %08x", diag_data.pc); 823f36f2648SCruise Hung DC_LOG_DEBUG(" unk_fault_addr : %08x", diag_data.undefined_address_fault_addr); 824f36f2648SCruise Hung DC_LOG_DEBUG(" inst_fault_addr : %08x", diag_data.inst_fetch_fault_addr); 825f36f2648SCruise Hung DC_LOG_DEBUG(" data_fault_addr : %08x", diag_data.data_write_fault_addr); 826f36f2648SCruise Hung DC_LOG_DEBUG(" inbox1_rptr : %08x", diag_data.inbox1_rptr); 827f36f2648SCruise Hung DC_LOG_DEBUG(" inbox1_wptr : %08x", diag_data.inbox1_wptr); 828f36f2648SCruise Hung DC_LOG_DEBUG(" inbox1_size : %08x", diag_data.inbox1_size); 829f36f2648SCruise Hung DC_LOG_DEBUG(" inbox0_rptr : %08x", diag_data.inbox0_rptr); 830f36f2648SCruise Hung DC_LOG_DEBUG(" inbox0_wptr : %08x", diag_data.inbox0_wptr); 831f36f2648SCruise Hung DC_LOG_DEBUG(" inbox0_size : %08x", diag_data.inbox0_size); 832f36f2648SCruise Hung DC_LOG_DEBUG(" is_enabled : %d", diag_data.is_dmcub_enabled); 833f36f2648SCruise Hung DC_LOG_DEBUG(" is_soft_reset : %d", diag_data.is_dmcub_soft_reset); 834f36f2648SCruise Hung DC_LOG_DEBUG(" is_secure_reset : %d", diag_data.is_dmcub_secure_reset); 835f36f2648SCruise Hung DC_LOG_DEBUG(" is_traceport_en : %d", diag_data.is_traceport_en); 836f36f2648SCruise Hung DC_LOG_DEBUG(" is_cw0_en : %d", diag_data.is_cw0_enabled); 837f36f2648SCruise Hung DC_LOG_DEBUG(" is_cw6_en : %d", diag_data.is_cw6_enabled); 8382631ac1aSAshley Thomas } 839b73353f7SMax Tseng 840f7085cbfSMax Tseng static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) 841f7085cbfSMax Tseng { 842f7085cbfSMax Tseng struct pipe_ctx *test_pipe, *split_pipe; 843f7085cbfSMax Tseng const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; 844f7085cbfSMax Tseng struct rect r1 = scl_data->recout, r2, r2_half; 845f7085cbfSMax Tseng int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b; 846f7085cbfSMax Tseng int cur_layer = pipe_ctx->plane_state->layer_index; 847f7085cbfSMax Tseng 848f7085cbfSMax Tseng /** 849f7085cbfSMax Tseng * Disable the cursor if there's another pipe above this with a 850f7085cbfSMax Tseng * plane that contains this pipe's viewport to prevent double cursor 851f7085cbfSMax Tseng * and incorrect scaling artifacts. 852f7085cbfSMax Tseng */ 853f7085cbfSMax Tseng for (test_pipe = pipe_ctx->top_pipe; test_pipe; 854f7085cbfSMax Tseng test_pipe = test_pipe->top_pipe) { 855f7085cbfSMax Tseng // Skip invisible layer and pipe-split plane on same layer 856f7085cbfSMax Tseng if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer) 857f7085cbfSMax Tseng continue; 858f7085cbfSMax Tseng 859f7085cbfSMax Tseng r2 = test_pipe->plane_res.scl_data.recout; 860f7085cbfSMax Tseng r2_r = r2.x + r2.width; 861f7085cbfSMax Tseng r2_b = r2.y + r2.height; 862f7085cbfSMax Tseng split_pipe = test_pipe; 863f7085cbfSMax Tseng 864f7085cbfSMax Tseng /** 865f7085cbfSMax Tseng * There is another half plane on same layer because of 866f7085cbfSMax Tseng * pipe-split, merge together per same height. 867f7085cbfSMax Tseng */ 868f7085cbfSMax Tseng for (split_pipe = pipe_ctx->top_pipe; split_pipe; 869f7085cbfSMax Tseng split_pipe = split_pipe->top_pipe) 870f7085cbfSMax Tseng if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) { 871f7085cbfSMax Tseng r2_half = split_pipe->plane_res.scl_data.recout; 872f7085cbfSMax Tseng r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x; 873f7085cbfSMax Tseng r2.width = r2.width + r2_half.width; 874f7085cbfSMax Tseng r2_r = r2.x + r2.width; 875f7085cbfSMax Tseng break; 876f7085cbfSMax Tseng } 877f7085cbfSMax Tseng 878f7085cbfSMax Tseng if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b) 879f7085cbfSMax Tseng return true; 880f7085cbfSMax Tseng } 881f7085cbfSMax Tseng 882f7085cbfSMax Tseng return false; 883f7085cbfSMax Tseng } 884f7085cbfSMax Tseng 885b73353f7SMax Tseng static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx) 886b73353f7SMax Tseng { 887b73353f7SMax Tseng if (pipe_ctx->plane_state != NULL) { 888b73353f7SMax Tseng if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 889b73353f7SMax Tseng return false; 890f7085cbfSMax Tseng 891f7085cbfSMax Tseng if (dc_can_pipe_disable_cursor(pipe_ctx)) 892f7085cbfSMax Tseng return false; 893b73353f7SMax Tseng } 894b73353f7SMax Tseng 895b73353f7SMax Tseng if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || 896b73353f7SMax Tseng pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) && 897b73353f7SMax Tseng pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1) 898b73353f7SMax Tseng return true; 899b73353f7SMax Tseng 900b73353f7SMax Tseng return false; 901b73353f7SMax Tseng } 902b73353f7SMax Tseng 903b73353f7SMax Tseng static void dc_build_cursor_update_payload0( 904b73353f7SMax Tseng struct pipe_ctx *pipe_ctx, uint8_t p_idx, 905b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 *payload) 906b73353f7SMax Tseng { 907b73353f7SMax Tseng struct hubp *hubp = pipe_ctx->plane_res.hubp; 908b73353f7SMax Tseng unsigned int panel_inst = 0; 909b73353f7SMax Tseng 910b73353f7SMax Tseng if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, 911b73353f7SMax Tseng pipe_ctx->stream->link, &panel_inst)) 912b73353f7SMax Tseng return; 913b73353f7SMax Tseng 914b73353f7SMax Tseng /* Payload: Cursor Rect is built from position & attribute 915b73353f7SMax Tseng * x & y are obtained from postion 916b73353f7SMax Tseng */ 917b73353f7SMax Tseng payload->cursor_rect.x = hubp->cur_rect.x; 918b73353f7SMax Tseng payload->cursor_rect.y = hubp->cur_rect.y; 919b73353f7SMax Tseng /* w & h are obtained from attribute */ 920b73353f7SMax Tseng payload->cursor_rect.width = hubp->cur_rect.w; 921b73353f7SMax Tseng payload->cursor_rect.height = hubp->cur_rect.h; 922b73353f7SMax Tseng 923b73353f7SMax Tseng payload->enable = hubp->pos.cur_ctl.bits.cur_enable; 924b73353f7SMax Tseng payload->pipe_idx = p_idx; 925b73353f7SMax Tseng payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 926b73353f7SMax Tseng payload->panel_inst = panel_inst; 927b73353f7SMax Tseng } 928b73353f7SMax Tseng 929b73353f7SMax Tseng static void dc_build_cursor_position_update_payload0( 930b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx, 931b73353f7SMax Tseng const struct hubp *hubp, const struct dpp *dpp) 932b73353f7SMax Tseng { 933b73353f7SMax Tseng /* Hubp */ 934b73353f7SMax Tseng pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw; 935b73353f7SMax Tseng pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw; 936b73353f7SMax Tseng pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw; 937b73353f7SMax Tseng pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw; 938b73353f7SMax Tseng 939b73353f7SMax Tseng /* dpp */ 940b73353f7SMax Tseng pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw; 941b73353f7SMax Tseng pl->position_cfg.pipe_idx = p_idx; 942b73353f7SMax Tseng } 943b73353f7SMax Tseng 944b73353f7SMax Tseng static void dc_build_cursor_attribute_update_payload1( 945b73353f7SMax Tseng struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx, 946b73353f7SMax Tseng const struct hubp *hubp, const struct dpp *dpp) 947b73353f7SMax Tseng { 948b73353f7SMax Tseng /* Hubp */ 949b73353f7SMax Tseng pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH; 950b73353f7SMax Tseng pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR; 951b73353f7SMax Tseng pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw; 952b73353f7SMax Tseng pl_A->aHubp.size.raw = hubp->att.size.raw; 953b73353f7SMax Tseng pl_A->aHubp.settings.raw = hubp->att.settings.raw; 954b73353f7SMax Tseng 955b73353f7SMax Tseng /* dpp */ 956b73353f7SMax Tseng pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw; 957b73353f7SMax Tseng } 958b73353f7SMax Tseng 959b73353f7SMax Tseng /** 9606be153dcSRodrigo Siqueira * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command 961b73353f7SMax Tseng * 9626be153dcSRodrigo Siqueira * @pCtx: [in] pipe context 9636be153dcSRodrigo Siqueira * @pipe_idx: [in] pipe index 964b73353f7SMax Tseng * 9656be153dcSRodrigo Siqueira * This function would store the cursor related information and pass it into 9666be153dcSRodrigo Siqueira * dmub 967b73353f7SMax Tseng */ 968b73353f7SMax Tseng void dc_send_update_cursor_info_to_dmu( 969b73353f7SMax Tseng struct pipe_ctx *pCtx, uint8_t pipe_idx) 970b73353f7SMax Tseng { 971e97cc04fSJosip Pavic union dmub_rb_cmd cmd[2]; 972e97cc04fSJosip Pavic union dmub_cmd_update_cursor_info_data *update_cursor_info_0 = 973e97cc04fSJosip Pavic &cmd[0].update_cursor_info.update_cursor_info_data; 974e97cc04fSJosip Pavic 975e97cc04fSJosip Pavic memset(cmd, 0, sizeof(cmd)); 976b73353f7SMax Tseng 977b73353f7SMax Tseng if (!dc_dmub_should_update_cursor_data(pCtx)) 978b73353f7SMax Tseng return; 979b73353f7SMax Tseng /* 980b73353f7SMax Tseng * Since we use multi_cmd_pending for dmub command, the 2nd command is 981b73353f7SMax Tseng * only assigned to store cursor attributes info. 982b73353f7SMax Tseng * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other 983b73353f7SMax Tseng * is to store cursor position info. 984b73353f7SMax Tseng * 985b73353f7SMax Tseng * Command heaer type must be the same type if using multi_cmd_pending. 986b73353f7SMax Tseng * Besides, while process 2nd command in DMU, the sub type is useless. 987b73353f7SMax Tseng * So it's meanless to pass the sub type header with different type. 988b73353f7SMax Tseng */ 989b73353f7SMax Tseng 990b73353f7SMax Tseng { 991b73353f7SMax Tseng /* Build Payload#0 Header */ 992e97cc04fSJosip Pavic cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 993e97cc04fSJosip Pavic cmd[0].update_cursor_info.header.payload_bytes = 994e97cc04fSJosip Pavic sizeof(cmd[0].update_cursor_info.update_cursor_info_data); 995e97cc04fSJosip Pavic cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd 996b73353f7SMax Tseng 997b73353f7SMax Tseng /* Prepare Payload */ 998e97cc04fSJosip Pavic dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info_0->payload0); 999b73353f7SMax Tseng 1000e97cc04fSJosip Pavic dc_build_cursor_position_update_payload0(&update_cursor_info_0->payload0, pipe_idx, 1001b73353f7SMax Tseng pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1002b73353f7SMax Tseng } 1003b73353f7SMax Tseng { 1004b73353f7SMax Tseng /* Build Payload#1 Header */ 1005e97cc04fSJosip Pavic cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 1006e97cc04fSJosip Pavic cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg); 1007e97cc04fSJosip Pavic cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command. 1008b73353f7SMax Tseng 1009b73353f7SMax Tseng dc_build_cursor_attribute_update_payload1( 1010e97cc04fSJosip Pavic &cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg, 1011b73353f7SMax Tseng pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1012b73353f7SMax Tseng 1013b73353f7SMax Tseng /* Combine 2nd cmds update_curosr_info to DMU */ 1014e97cc04fSJosip Pavic dm_execute_dmub_cmd_list(pCtx->stream->ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT); 1015b73353f7SMax Tseng } 1016b73353f7SMax Tseng } 1017c35b6ea8SMario Limonciello 1018c35b6ea8SMario Limonciello bool dc_dmub_check_min_version(struct dmub_srv *srv) 1019c35b6ea8SMario Limonciello { 1020c35b6ea8SMario Limonciello if (!srv->hw_funcs.is_psrsu_supported) 1021c35b6ea8SMario Limonciello return true; 1022c35b6ea8SMario Limonciello return srv->hw_funcs.is_psrsu_supported(srv); 1023c35b6ea8SMario Limonciello } 1024