13a1627b0SNicholas Kazlauskas /* 23a1627b0SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 33a1627b0SNicholas Kazlauskas * 43a1627b0SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 53a1627b0SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 63a1627b0SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 73a1627b0SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 83a1627b0SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 93a1627b0SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 103a1627b0SNicholas Kazlauskas * 113a1627b0SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 123a1627b0SNicholas Kazlauskas * all copies or substantial portions of the Software. 133a1627b0SNicholas Kazlauskas * 143a1627b0SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 153a1627b0SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 163a1627b0SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 173a1627b0SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 183a1627b0SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 193a1627b0SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 203a1627b0SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 213a1627b0SNicholas Kazlauskas * 223a1627b0SNicholas Kazlauskas * Authors: AMD 233a1627b0SNicholas Kazlauskas * 243a1627b0SNicholas Kazlauskas */ 253a1627b0SNicholas Kazlauskas 263a1627b0SNicholas Kazlauskas #include "dc.h" 273a1627b0SNicholas Kazlauskas #include "dc_dmub_srv.h" 28cdca3f21SAnthony Koo #include "../dmub/dmub_srv.h" 2970732504SYongqiang Sun #include "dm_helpers.h" 30c2fbe663SFelipe Clark #include "dc_hw_types.h" 31c2fbe663SFelipe Clark #include "core_types.h" 32fbe43dcdSAlvin Lee #include "../basics/conversion.h" 33b73353f7SMax Tseng #include "cursor_reg_cache.h" 343a1627b0SNicholas Kazlauskas 35ecdfc5c9SNicholas Kazlauskas #define CTX dc_dmub_srv->ctx 36ecdfc5c9SNicholas Kazlauskas #define DC_LOGGER CTX->logger 37ecdfc5c9SNicholas Kazlauskas 383a1627b0SNicholas Kazlauskas static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, 393a1627b0SNicholas Kazlauskas struct dmub_srv *dmub) 403a1627b0SNicholas Kazlauskas { 413a1627b0SNicholas Kazlauskas dc_srv->dmub = dmub; 423a1627b0SNicholas Kazlauskas dc_srv->ctx = dc->ctx; 433a1627b0SNicholas Kazlauskas } 443a1627b0SNicholas Kazlauskas 453a1627b0SNicholas Kazlauskas struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) 463a1627b0SNicholas Kazlauskas { 473a1627b0SNicholas Kazlauskas struct dc_dmub_srv *dc_srv = 483a1627b0SNicholas Kazlauskas kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL); 493a1627b0SNicholas Kazlauskas 503a1627b0SNicholas Kazlauskas if (dc_srv == NULL) { 513a1627b0SNicholas Kazlauskas BREAK_TO_DEBUGGER(); 523a1627b0SNicholas Kazlauskas return NULL; 533a1627b0SNicholas Kazlauskas } 543a1627b0SNicholas Kazlauskas 553a1627b0SNicholas Kazlauskas dc_dmub_srv_construct(dc_srv, dc, dmub); 563a1627b0SNicholas Kazlauskas 573a1627b0SNicholas Kazlauskas return dc_srv; 583a1627b0SNicholas Kazlauskas } 593a1627b0SNicholas Kazlauskas 603a1627b0SNicholas Kazlauskas void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv) 613a1627b0SNicholas Kazlauskas { 623a1627b0SNicholas Kazlauskas if (*dmub_srv) { 633a1627b0SNicholas Kazlauskas kfree(*dmub_srv); 643a1627b0SNicholas Kazlauskas *dmub_srv = NULL; 653a1627b0SNicholas Kazlauskas } 663a1627b0SNicholas Kazlauskas } 673a1627b0SNicholas Kazlauskas 683a1627b0SNicholas Kazlauskas void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv, 690ed3bcc4SNicholas Kazlauskas union dmub_rb_cmd *cmd) 703a1627b0SNicholas Kazlauskas { 713a1627b0SNicholas Kazlauskas struct dmub_srv *dmub = dc_dmub_srv->dmub; 723a1627b0SNicholas Kazlauskas struct dc_context *dc_ctx = dc_dmub_srv->ctx; 733a1627b0SNicholas Kazlauskas enum dmub_status status; 743a1627b0SNicholas Kazlauskas 753a1627b0SNicholas Kazlauskas status = dmub_srv_cmd_queue(dmub, cmd); 763a1627b0SNicholas Kazlauskas if (status == DMUB_STATUS_OK) 773a1627b0SNicholas Kazlauskas return; 783a1627b0SNicholas Kazlauskas 793a1627b0SNicholas Kazlauskas if (status != DMUB_STATUS_QUEUE_FULL) 803a1627b0SNicholas Kazlauskas goto error; 813a1627b0SNicholas Kazlauskas 823a1627b0SNicholas Kazlauskas /* Execute and wait for queue to become empty again. */ 833a1627b0SNicholas Kazlauskas dc_dmub_srv_cmd_execute(dc_dmub_srv); 843a1627b0SNicholas Kazlauskas dc_dmub_srv_wait_idle(dc_dmub_srv); 853a1627b0SNicholas Kazlauskas 863a1627b0SNicholas Kazlauskas /* Requeue the command. */ 873a1627b0SNicholas Kazlauskas status = dmub_srv_cmd_queue(dmub, cmd); 883a1627b0SNicholas Kazlauskas if (status == DMUB_STATUS_OK) 893a1627b0SNicholas Kazlauskas return; 903a1627b0SNicholas Kazlauskas 913a1627b0SNicholas Kazlauskas error: 923a1627b0SNicholas Kazlauskas DC_ERROR("Error queuing DMUB command: status=%d\n", status); 932631ac1aSAshley Thomas dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 943a1627b0SNicholas Kazlauskas } 953a1627b0SNicholas Kazlauskas 963a1627b0SNicholas Kazlauskas void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv) 973a1627b0SNicholas Kazlauskas { 983a1627b0SNicholas Kazlauskas struct dmub_srv *dmub = dc_dmub_srv->dmub; 993a1627b0SNicholas Kazlauskas struct dc_context *dc_ctx = dc_dmub_srv->ctx; 1003a1627b0SNicholas Kazlauskas enum dmub_status status; 1013a1627b0SNicholas Kazlauskas 1023a1627b0SNicholas Kazlauskas status = dmub_srv_cmd_execute(dmub); 1032631ac1aSAshley Thomas if (status != DMUB_STATUS_OK) { 104243a8f41SColin Ian King DC_ERROR("Error starting DMUB execution: status=%d\n", status); 1052631ac1aSAshley Thomas dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 1062631ac1aSAshley Thomas } 1073a1627b0SNicholas Kazlauskas } 1083a1627b0SNicholas Kazlauskas 1093a1627b0SNicholas Kazlauskas void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) 1103a1627b0SNicholas Kazlauskas { 1113a1627b0SNicholas Kazlauskas struct dmub_srv *dmub = dc_dmub_srv->dmub; 1123a1627b0SNicholas Kazlauskas struct dc_context *dc_ctx = dc_dmub_srv->ctx; 1133a1627b0SNicholas Kazlauskas enum dmub_status status; 1143a1627b0SNicholas Kazlauskas 1153a1627b0SNicholas Kazlauskas status = dmub_srv_wait_for_idle(dmub, 100000); 1162631ac1aSAshley Thomas if (status != DMUB_STATUS_OK) { 1173a1627b0SNicholas Kazlauskas DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); 1182631ac1aSAshley Thomas dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 1192631ac1aSAshley Thomas } 1203a1627b0SNicholas Kazlauskas } 1213a1627b0SNicholas Kazlauskas 122d493a024SAlvin Lee void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv) 123d493a024SAlvin Lee { 124d493a024SAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub; 125d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx; 126d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK; 127d493a024SAlvin Lee 128d493a024SAlvin Lee status = dmub_srv_clear_inbox0_ack(dmub); 129d493a024SAlvin Lee if (status != DMUB_STATUS_OK) { 130d493a024SAlvin Lee DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status); 131d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv); 132d493a024SAlvin Lee } 133d493a024SAlvin Lee } 134d493a024SAlvin Lee 135d493a024SAlvin Lee void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv) 136d493a024SAlvin Lee { 137d493a024SAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub; 138d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx; 139d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK; 140d493a024SAlvin Lee 141d493a024SAlvin Lee status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); 142d493a024SAlvin Lee if (status != DMUB_STATUS_OK) { 143d493a024SAlvin Lee DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n"); 144d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv); 145d493a024SAlvin Lee } 146d493a024SAlvin Lee } 147d493a024SAlvin Lee 148f2973d2aSAlvin Lee void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, 149f2973d2aSAlvin Lee union dmub_inbox0_data_register data) 150f2973d2aSAlvin Lee { 151f2973d2aSAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub; 152d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx; 153d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK; 154d493a024SAlvin Lee 155d493a024SAlvin Lee status = dmub_srv_send_inbox0_cmd(dmub, data); 156d493a024SAlvin Lee if (status != DMUB_STATUS_OK) { 157d493a024SAlvin Lee DC_ERROR("Error sending INBOX0 cmd\n"); 158d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv); 159d493a024SAlvin Lee } 160f2973d2aSAlvin Lee } 161f2973d2aSAlvin Lee 162ecdfc5c9SNicholas Kazlauskas bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd) 163ecdfc5c9SNicholas Kazlauskas { 164ecdfc5c9SNicholas Kazlauskas struct dmub_srv *dmub; 165ecdfc5c9SNicholas Kazlauskas enum dmub_status status; 166ecdfc5c9SNicholas Kazlauskas 167ecdfc5c9SNicholas Kazlauskas if (!dc_dmub_srv || !dc_dmub_srv->dmub) 168ecdfc5c9SNicholas Kazlauskas return false; 169ecdfc5c9SNicholas Kazlauskas 170ecdfc5c9SNicholas Kazlauskas dmub = dc_dmub_srv->dmub; 171ecdfc5c9SNicholas Kazlauskas 172ecdfc5c9SNicholas Kazlauskas status = dmub_srv_cmd_with_reply_data(dmub, cmd); 173ecdfc5c9SNicholas Kazlauskas if (status != DMUB_STATUS_OK) { 174ecdfc5c9SNicholas Kazlauskas DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 175ecdfc5c9SNicholas Kazlauskas return false; 176ecdfc5c9SNicholas Kazlauskas } 177ecdfc5c9SNicholas Kazlauskas 178ecdfc5c9SNicholas Kazlauskas return true; 179ecdfc5c9SNicholas Kazlauskas } 180ecdfc5c9SNicholas Kazlauskas 1813a1627b0SNicholas Kazlauskas void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv) 1823a1627b0SNicholas Kazlauskas { 1833a1627b0SNicholas Kazlauskas struct dmub_srv *dmub = dc_dmub_srv->dmub; 1843a1627b0SNicholas Kazlauskas struct dc_context *dc_ctx = dc_dmub_srv->ctx; 1853a1627b0SNicholas Kazlauskas enum dmub_status status; 1863a1627b0SNicholas Kazlauskas 187a6e4da40SNicholas Kazlauskas for (;;) { 188a6e4da40SNicholas Kazlauskas /* Wait up to a second for PHY init. */ 189a6e4da40SNicholas Kazlauskas status = dmub_srv_wait_for_phy_init(dmub, 1000000); 190a6e4da40SNicholas Kazlauskas if (status == DMUB_STATUS_OK) 191a6e4da40SNicholas Kazlauskas /* Initialization OK */ 192a6e4da40SNicholas Kazlauskas break; 193a6e4da40SNicholas Kazlauskas 194a6e4da40SNicholas Kazlauskas DC_ERROR("DMCUB PHY init failed: status=%d\n", status); 19556fc13feSNicholas Kazlauskas ASSERT(0); 196a6e4da40SNicholas Kazlauskas 197a6e4da40SNicholas Kazlauskas if (status != DMUB_STATUS_TIMEOUT) 198a6e4da40SNicholas Kazlauskas /* 199a6e4da40SNicholas Kazlauskas * Server likely initialized or we don't have 200a6e4da40SNicholas Kazlauskas * DMCUB HW support - this won't end. 201a6e4da40SNicholas Kazlauskas */ 202a6e4da40SNicholas Kazlauskas break; 203a6e4da40SNicholas Kazlauskas 204a6e4da40SNicholas Kazlauskas /* Continue spinning so we don't hang the ASIC. */ 20556fc13feSNicholas Kazlauskas } 2063a1627b0SNicholas Kazlauskas } 2070825d965SEric Yang 2080825d965SEric Yang bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 2090825d965SEric Yang unsigned int stream_mask) 2100825d965SEric Yang { 2110825d965SEric Yang struct dmub_srv *dmub; 2120825d965SEric Yang const uint32_t timeout = 30; 2130825d965SEric Yang 2140825d965SEric Yang if (!dc_dmub_srv || !dc_dmub_srv->dmub) 2150825d965SEric Yang return false; 2160825d965SEric Yang 2170825d965SEric Yang dmub = dc_dmub_srv->dmub; 2180825d965SEric Yang 2190825d965SEric Yang return dmub_srv_send_gpint_command( 2200825d965SEric Yang dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, 2210825d965SEric Yang stream_mask, timeout) == DMUB_STATUS_OK; 2220825d965SEric Yang } 2238fe44c08SAlex Deucher 224b04cb192SNicholas Kazlauskas bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) 225b04cb192SNicholas Kazlauskas { 226b04cb192SNicholas Kazlauskas struct dmub_srv *dmub; 227b04cb192SNicholas Kazlauskas struct dc_context *dc_ctx; 228b04cb192SNicholas Kazlauskas union dmub_fw_boot_status boot_status; 229b04cb192SNicholas Kazlauskas enum dmub_status status; 230b04cb192SNicholas Kazlauskas 231b04cb192SNicholas Kazlauskas if (!dc_dmub_srv || !dc_dmub_srv->dmub) 232b04cb192SNicholas Kazlauskas return false; 233b04cb192SNicholas Kazlauskas 234b04cb192SNicholas Kazlauskas dmub = dc_dmub_srv->dmub; 235b04cb192SNicholas Kazlauskas dc_ctx = dc_dmub_srv->ctx; 236b04cb192SNicholas Kazlauskas 237b04cb192SNicholas Kazlauskas status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 238b04cb192SNicholas Kazlauskas if (status != DMUB_STATUS_OK) { 239b04cb192SNicholas Kazlauskas DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 240b04cb192SNicholas Kazlauskas return false; 241b04cb192SNicholas Kazlauskas } 242b04cb192SNicholas Kazlauskas 243b04cb192SNicholas Kazlauskas return boot_status.bits.restore_required; 244b04cb192SNicholas Kazlauskas } 24570732504SYongqiang Sun 2466804287bSYongqiang Sun bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) 24770732504SYongqiang Sun { 24870732504SYongqiang Sun struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; 2496804287bSYongqiang Sun return dmub_srv_get_outbox0_msg(dmub, entry); 25070732504SYongqiang Sun } 25170732504SYongqiang Sun 25270732504SYongqiang Sun void dc_dmub_trace_event_control(struct dc *dc, bool enable) 25370732504SYongqiang Sun { 25481927e28SJude Shih dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); 25570732504SYongqiang Sun } 2562631ac1aSAshley Thomas 25700fa7f03SRodrigo Siqueira void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) 25800fa7f03SRodrigo Siqueira { 25900fa7f03SRodrigo Siqueira union dmub_rb_cmd cmd = { 0 }; 26000fa7f03SRodrigo Siqueira 26100fa7f03SRodrigo Siqueira cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 26200fa7f03SRodrigo Siqueira cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE; 26300fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 26400fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 26500fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 26600fa7f03SRodrigo Siqueira 26700fa7f03SRodrigo Siqueira cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 26800fa7f03SRodrigo Siqueira 26900fa7f03SRodrigo Siqueira // Send the command to the DMCUB. 27000fa7f03SRodrigo Siqueira dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 27100fa7f03SRodrigo Siqueira dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 27200fa7f03SRodrigo Siqueira dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 27300fa7f03SRodrigo Siqueira } 27400fa7f03SRodrigo Siqueira 275319568d7SAlvin Lee void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) 276319568d7SAlvin Lee { 277319568d7SAlvin Lee union dmub_rb_cmd cmd = { 0 }; 278319568d7SAlvin Lee 279319568d7SAlvin Lee cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 2809f5171ceSAlvin Lee cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER; 281319568d7SAlvin Lee cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 282319568d7SAlvin Lee 283319568d7SAlvin Lee cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 284319568d7SAlvin Lee 285319568d7SAlvin Lee // Send the command to the DMCUB. 286319568d7SAlvin Lee dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 287319568d7SAlvin Lee dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 288319568d7SAlvin Lee dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 289319568d7SAlvin Lee } 290319568d7SAlvin Lee 29184900aeeSAlex Deucher static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) 29200fa7f03SRodrigo Siqueira { 29300fa7f03SRodrigo Siqueira uint8_t pipes = 0; 29400fa7f03SRodrigo Siqueira int i = 0; 29500fa7f03SRodrigo Siqueira 29600fa7f03SRodrigo Siqueira for (i = 0; i < MAX_PIPES; i++) { 29700fa7f03SRodrigo Siqueira struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 29800fa7f03SRodrigo Siqueira 29900fa7f03SRodrigo Siqueira if (pipe->stream == stream && pipe->stream_res.tg) 30000fa7f03SRodrigo Siqueira pipes = i; 30100fa7f03SRodrigo Siqueira } 30200fa7f03SRodrigo Siqueira return pipes; 30300fa7f03SRodrigo Siqueira } 30400fa7f03SRodrigo Siqueira 30584900aeeSAlex Deucher static int dc_dmub_srv_get_timing_generator_offset(struct dc *dc, struct dc_stream_state *stream) 30600fa7f03SRodrigo Siqueira { 30700fa7f03SRodrigo Siqueira int tg_inst = 0; 30800fa7f03SRodrigo Siqueira int i = 0; 30900fa7f03SRodrigo Siqueira 31000fa7f03SRodrigo Siqueira for (i = 0; i < MAX_PIPES; i++) { 31100fa7f03SRodrigo Siqueira struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 31200fa7f03SRodrigo Siqueira 31300fa7f03SRodrigo Siqueira if (pipe->stream == stream && pipe->stream_res.tg) { 31400fa7f03SRodrigo Siqueira tg_inst = pipe->stream_res.tg->inst; 31500fa7f03SRodrigo Siqueira break; 31600fa7f03SRodrigo Siqueira } 31700fa7f03SRodrigo Siqueira } 31800fa7f03SRodrigo Siqueira return tg_inst; 31900fa7f03SRodrigo Siqueira } 32000fa7f03SRodrigo Siqueira 32100fa7f03SRodrigo Siqueira bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) 32200fa7f03SRodrigo Siqueira { 32300fa7f03SRodrigo Siqueira union dmub_rb_cmd cmd = { 0 }; 32400fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; 32500fa7f03SRodrigo Siqueira int i = 0; 32600fa7f03SRodrigo Siqueira int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. 32745a92f45Ssunliming uint8_t visual_confirm_enabled; 32800fa7f03SRodrigo Siqueira 32900fa7f03SRodrigo Siqueira if (dc == NULL) 33000fa7f03SRodrigo Siqueira return false; 33100fa7f03SRodrigo Siqueira 33245a92f45Ssunliming visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; 33345a92f45Ssunliming 33400fa7f03SRodrigo Siqueira // Format command. 33500fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 33600fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL; 33700fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate; 33800fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; 33900fa7f03SRodrigo Siqueira 34000fa7f03SRodrigo Siqueira for (i = 0; context && i < context->stream_count; i++) { 34100fa7f03SRodrigo Siqueira struct dc_stream_state *stream = context->streams[i]; 34200fa7f03SRodrigo Siqueira uint8_t min_refresh_in_hz = (stream->timing.min_refresh_in_uhz + 999999) / 1000000; 34300fa7f03SRodrigo Siqueira int tg_inst = dc_dmub_srv_get_timing_generator_offset(dc, stream); 34400fa7f03SRodrigo Siqueira 34500fa7f03SRodrigo Siqueira config_data->pipe_data[tg_inst].pix_clk_100hz = stream->timing.pix_clk_100hz; 34600fa7f03SRodrigo Siqueira config_data->pipe_data[tg_inst].min_refresh_in_hz = min_refresh_in_hz; 34700fa7f03SRodrigo Siqueira config_data->pipe_data[tg_inst].max_ramp_step = ramp_up_num_steps; 34800fa7f03SRodrigo Siqueira config_data->pipe_data[tg_inst].pipes = dc_dmub_srv_get_pipes_for_stream(dc, stream); 34900fa7f03SRodrigo Siqueira } 35000fa7f03SRodrigo Siqueira 35100fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.payload_bytes = 35200fa7f03SRodrigo Siqueira sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header); 35300fa7f03SRodrigo Siqueira 35400fa7f03SRodrigo Siqueira // Send the command to the DMCUB. 35500fa7f03SRodrigo Siqueira dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 35600fa7f03SRodrigo Siqueira dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 35700fa7f03SRodrigo Siqueira dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 35800fa7f03SRodrigo Siqueira 35900fa7f03SRodrigo Siqueira return true; 36000fa7f03SRodrigo Siqueira } 36100fa7f03SRodrigo Siqueira 362ac2e555eSAurabindo Pillai void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub) 363ac2e555eSAurabindo Pillai { 364ac2e555eSAurabindo Pillai union dmub_rb_cmd cmd = { 0 }; 365ac2e555eSAurabindo Pillai enum dmub_status status; 366ac2e555eSAurabindo Pillai 367ac2e555eSAurabindo Pillai if (!dmub) { 368ac2e555eSAurabindo Pillai return; 369ac2e555eSAurabindo Pillai } 370ac2e555eSAurabindo Pillai 371ac2e555eSAurabindo Pillai memset(&cmd, 0, sizeof(cmd)); 372ac2e555eSAurabindo Pillai 373ac2e555eSAurabindo Pillai /* Prepare fw command */ 374ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; 375ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.sub_type = 0; 376ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.ret_status = 1; 377ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); 378ac2e555eSAurabindo Pillai 379ac2e555eSAurabindo Pillai /* Send command to fw */ 380ac2e555eSAurabindo Pillai status = dmub_srv_cmd_with_reply_data(dmub, &cmd); 381ac2e555eSAurabindo Pillai 382ac2e555eSAurabindo Pillai ASSERT(status == DMUB_STATUS_OK); 383ac2e555eSAurabindo Pillai 384ac2e555eSAurabindo Pillai /* If command was processed, copy feature caps to dmub srv */ 385ac2e555eSAurabindo Pillai if (status == DMUB_STATUS_OK && 386ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.ret_status == 0) { 387ac2e555eSAurabindo Pillai memcpy(&dmub->feature_caps, 388ac2e555eSAurabindo Pillai &cmd.query_feature_caps.query_feature_caps_data, 389ac2e555eSAurabindo Pillai sizeof(struct dmub_feature_caps)); 390ac2e555eSAurabindo Pillai } 391ac2e555eSAurabindo Pillai } 392ac2e555eSAurabindo Pillai 393b09c1fffSLeo (Hanghong) Ma void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx) 394b09c1fffSLeo (Hanghong) Ma { 395b09c1fffSLeo (Hanghong) Ma union dmub_rb_cmd cmd = { 0 }; 396b09c1fffSLeo (Hanghong) Ma enum dmub_status status; 397b09c1fffSLeo (Hanghong) Ma unsigned int panel_inst = 0; 398b09c1fffSLeo (Hanghong) Ma 399b09c1fffSLeo (Hanghong) Ma dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst); 400b09c1fffSLeo (Hanghong) Ma 401b09c1fffSLeo (Hanghong) Ma memset(&cmd, 0, sizeof(cmd)); 402b09c1fffSLeo (Hanghong) Ma 403b09c1fffSLeo (Hanghong) Ma // Prepare fw command 404b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR; 405b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.sub_type = 0; 406b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.ret_status = 1; 407b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data); 408b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst; 409b09c1fffSLeo (Hanghong) Ma 410b09c1fffSLeo (Hanghong) Ma // Send command to fw 411b09c1fffSLeo (Hanghong) Ma status = dmub_srv_cmd_with_reply_data(dc->ctx->dmub_srv->dmub, &cmd); 412b09c1fffSLeo (Hanghong) Ma 413b09c1fffSLeo (Hanghong) Ma ASSERT(status == DMUB_STATUS_OK); 414b09c1fffSLeo (Hanghong) Ma 415b09c1fffSLeo (Hanghong) Ma // If command was processed, copy feature caps to dmub srv 416b09c1fffSLeo (Hanghong) Ma if (status == DMUB_STATUS_OK && 417b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.ret_status == 0) { 418b09c1fffSLeo (Hanghong) Ma memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color, 419b09c1fffSLeo (Hanghong) Ma &cmd.visual_confirm_color.visual_confirm_color_data, 420b09c1fffSLeo (Hanghong) Ma sizeof(struct dmub_visual_confirm_color)); 421b09c1fffSLeo (Hanghong) Ma } 422b09c1fffSLeo (Hanghong) Ma } 423b09c1fffSLeo (Hanghong) Ma 424bdd0d7e2SAlex Deucher #ifdef CONFIG_DRM_AMD_DC_DCN 42585f4bc0cSAlvin Lee /** 4266be153dcSRodrigo Siqueira * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command 42785f4bc0cSAlvin Lee * 4286be153dcSRodrigo Siqueira * @dc: [in] current dc state 4296be153dcSRodrigo Siqueira * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 4306be153dcSRodrigo Siqueira * @vblank_pipe: [in] pipe_ctx for the DRR pipe 4316be153dcSRodrigo Siqueira * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info 4326be153dcSRodrigo Siqueira * 4336be153dcSRodrigo Siqueira * Populate the DMCUB SubVP command with DRR pipe info. All the information 4346be153dcSRodrigo Siqueira * required for calculating the SubVP + DRR microschedule is populated here. 43585f4bc0cSAlvin Lee * 43685f4bc0cSAlvin Lee * High level algorithm: 43785f4bc0cSAlvin Lee * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 43885f4bc0cSAlvin Lee * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule 43985f4bc0cSAlvin Lee * 3. Populate the drr_info with the min and max supported vtotal values 44085f4bc0cSAlvin Lee */ 44185f4bc0cSAlvin Lee static void populate_subvp_cmd_drr_info(struct dc *dc, 44285f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipe, 44385f4bc0cSAlvin Lee struct pipe_ctx *vblank_pipe, 44485f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data) 44585f4bc0cSAlvin Lee { 44685f4bc0cSAlvin Lee struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 44785f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 44885f4bc0cSAlvin Lee struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 449410e7474SAlvin Lee uint16_t drr_frame_us = 0; 450410e7474SAlvin Lee uint16_t min_drr_supported_us = 0; 451410e7474SAlvin Lee uint16_t max_drr_supported_us = 0; 452410e7474SAlvin Lee uint16_t max_drr_vblank_us = 0; 453410e7474SAlvin Lee uint16_t max_drr_mallregion_us = 0; 454410e7474SAlvin Lee uint16_t mall_region_us = 0; 455410e7474SAlvin Lee uint16_t prefetch_us = 0; 456410e7474SAlvin Lee uint16_t subvp_active_us = 0; 457410e7474SAlvin Lee uint16_t drr_active_us = 0; 458410e7474SAlvin Lee uint16_t min_vtotal_supported = 0; 459410e7474SAlvin Lee uint16_t max_vtotal_supported = 0; 46085f4bc0cSAlvin Lee 46185f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; 46285f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping 46385f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now 46485f4bc0cSAlvin Lee 465410e7474SAlvin Lee drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000), 466410e7474SAlvin Lee (((uint64_t)drr_timing->pix_clk_100hz * 100))); 46785f4bc0cSAlvin Lee // P-State allow width and FW delays already included phantom_timing->v_addressable 468410e7474SAlvin Lee mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000), 469410e7474SAlvin Lee (((uint64_t)phantom_timing->pix_clk_100hz * 100))); 47085f4bc0cSAlvin Lee min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 471410e7474SAlvin Lee min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us), 472410e7474SAlvin Lee (((uint64_t)drr_timing->h_total * 1000000))); 47385f4bc0cSAlvin Lee 474410e7474SAlvin Lee prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000), 475410e7474SAlvin Lee (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 476410e7474SAlvin Lee subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000), 477410e7474SAlvin Lee (((uint64_t)main_timing->pix_clk_100hz * 100))); 478410e7474SAlvin Lee drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000), 479410e7474SAlvin Lee (((uint64_t)drr_timing->pix_clk_100hz * 100))); 480964d6416SAlvin Lee max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - 481964d6416SAlvin Lee dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us; 482964d6416SAlvin Lee max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us; 48385f4bc0cSAlvin Lee max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; 484410e7474SAlvin Lee max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us), 485410e7474SAlvin Lee (((uint64_t)drr_timing->h_total * 1000000))); 48685f4bc0cSAlvin Lee 487964d6416SAlvin Lee /* When calculating the max vtotal supported for SubVP + DRR cases, add 488964d6416SAlvin Lee * margin due to possible rounding errors (being off by 1 line in the 489964d6416SAlvin Lee * FW calculation can incorrectly push the P-State switch to wait 1 frame 490964d6416SAlvin Lee * longer). 491964d6416SAlvin Lee */ 492964d6416SAlvin Lee max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us; 493964d6416SAlvin Lee 49485f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; 49585f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; 496ae7169a9SAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us; 49785f4bc0cSAlvin Lee } 49885f4bc0cSAlvin Lee 49985f4bc0cSAlvin Lee /** 5006be153dcSRodrigo Siqueira * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command 50185f4bc0cSAlvin Lee * 5026be153dcSRodrigo Siqueira * @dc: [in] current dc state 5036be153dcSRodrigo Siqueira * @context: [in] new dc state 5046be153dcSRodrigo Siqueira * @cmd: [in] DMUB cmd to be populated with SubVP info 5056be153dcSRodrigo Siqueira * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe 5066be153dcSRodrigo Siqueira * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 50785f4bc0cSAlvin Lee * 5086be153dcSRodrigo Siqueira * Populate the DMCUB SubVP command with VBLANK pipe info. All the information 5096be153dcSRodrigo Siqueira * required to calculate the microschedule for SubVP + VBLANK case is stored in 5106be153dcSRodrigo Siqueira * the pipe_data (subvp_data and vblank_data). Also check if the VBLANK pipe 5116be153dcSRodrigo Siqueira * is a DRR display -- if it is make a call to populate drr_info. 51285f4bc0cSAlvin Lee */ 51385f4bc0cSAlvin Lee static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, 51485f4bc0cSAlvin Lee struct dc_state *context, 51585f4bc0cSAlvin Lee union dmub_rb_cmd *cmd, 51685f4bc0cSAlvin Lee struct pipe_ctx *vblank_pipe, 51785f4bc0cSAlvin Lee uint8_t cmd_pipe_index) 51885f4bc0cSAlvin Lee { 51985f4bc0cSAlvin Lee uint32_t i; 52085f4bc0cSAlvin Lee struct pipe_ctx *pipe = NULL; 52185f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 52285f4bc0cSAlvin Lee &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 52385f4bc0cSAlvin Lee 52485f4bc0cSAlvin Lee // Find the SubVP pipe 52585f4bc0cSAlvin Lee for (i = 0; i < dc->res_pool->pipe_count; i++) { 52685f4bc0cSAlvin Lee pipe = &context->res_ctx.pipe_ctx[i]; 52785f4bc0cSAlvin Lee 52885f4bc0cSAlvin Lee // We check for master pipe, but it shouldn't matter since we only need 52985f4bc0cSAlvin Lee // the pipe for timing info (stream should be same for any pipe splits) 53085f4bc0cSAlvin Lee if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 53185f4bc0cSAlvin Lee continue; 53285f4bc0cSAlvin Lee 53385f4bc0cSAlvin Lee // Find the SubVP pipe 53485f4bc0cSAlvin Lee if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 53585f4bc0cSAlvin Lee break; 53685f4bc0cSAlvin Lee } 53785f4bc0cSAlvin Lee 53885f4bc0cSAlvin Lee pipe_data->mode = VBLANK; 53985f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; 54085f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - 54185f4bc0cSAlvin Lee vblank_pipe->stream->timing.v_front_porch; 54285f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; 54385f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; 54485f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; 54585f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; 54685f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_end = 54785f4bc0cSAlvin Lee vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; 54885f4bc0cSAlvin Lee 54985f4bc0cSAlvin Lee if (vblank_pipe->stream->ignore_msa_timing_param) 55085f4bc0cSAlvin Lee populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data); 55185f4bc0cSAlvin Lee } 55285f4bc0cSAlvin Lee 55385f4bc0cSAlvin Lee /** 5546be153dcSRodrigo Siqueira * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case 55585f4bc0cSAlvin Lee * 5566be153dcSRodrigo Siqueira * @dc: [in] current dc state 5576be153dcSRodrigo Siqueira * @context: [in] new dc state 5586be153dcSRodrigo Siqueira * @cmd: [in] DMUB cmd to be populated with SubVP info 5596be153dcSRodrigo Siqueira * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2) 56085f4bc0cSAlvin Lee * 5616be153dcSRodrigo Siqueira * For SubVP + SubVP, we use a single vertical interrupt to start the 5626be153dcSRodrigo Siqueira * microschedule for both SubVP pipes. In order for this to work correctly, the 5636be153dcSRodrigo Siqueira * MALL REGION of both SubVP pipes must start at the same time. This function 5646be153dcSRodrigo Siqueira * lengthens the prefetch end to mall start delay of the SubVP pipe that has 5656be153dcSRodrigo Siqueira * the shorter prefetch so that both MALL REGION's will start at the same time. 56685f4bc0cSAlvin Lee */ 56785f4bc0cSAlvin Lee static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, 56885f4bc0cSAlvin Lee struct dc_state *context, 56985f4bc0cSAlvin Lee union dmub_rb_cmd *cmd, 57085f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipes[]) 57185f4bc0cSAlvin Lee { 57285f4bc0cSAlvin Lee uint32_t subvp0_prefetch_us = 0; 57385f4bc0cSAlvin Lee uint32_t subvp1_prefetch_us = 0; 57485f4bc0cSAlvin Lee uint32_t prefetch_delta_us = 0; 57585f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing; 57685f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing; 57785f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL; 57885f4bc0cSAlvin Lee 579410e7474SAlvin Lee subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * 580410e7474SAlvin Lee (uint64_t)phantom_timing0->h_total * 1000000), 581410e7474SAlvin Lee (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 582410e7474SAlvin Lee subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * 583410e7474SAlvin Lee (uint64_t)phantom_timing1->h_total * 1000000), 584410e7474SAlvin Lee (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 58585f4bc0cSAlvin Lee 58685f4bc0cSAlvin Lee // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) 58785f4bc0cSAlvin Lee // should increase it's prefetch time to match the other 58885f4bc0cSAlvin Lee if (subvp0_prefetch_us > subvp1_prefetch_us) { 58985f4bc0cSAlvin Lee pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; 59085f4bc0cSAlvin Lee prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; 59185f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 592410e7474SAlvin Lee div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 593410e7474SAlvin Lee ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), 594410e7474SAlvin Lee ((uint64_t)phantom_timing1->h_total * 1000000)); 595410e7474SAlvin Lee 59685f4bc0cSAlvin Lee } else if (subvp1_prefetch_us > subvp0_prefetch_us) { 59785f4bc0cSAlvin Lee pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; 59885f4bc0cSAlvin Lee prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; 59985f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 600410e7474SAlvin Lee div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 601410e7474SAlvin Lee ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), 602410e7474SAlvin Lee ((uint64_t)phantom_timing0->h_total * 1000000)); 60385f4bc0cSAlvin Lee } 60485f4bc0cSAlvin Lee } 60585f4bc0cSAlvin Lee 60685f4bc0cSAlvin Lee /** 6070645b7a6SJiapeng Chong * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command 60885f4bc0cSAlvin Lee * 6096be153dcSRodrigo Siqueira * @dc: [in] current dc state 6106be153dcSRodrigo Siqueira * @context: [in] new dc state 6116be153dcSRodrigo Siqueira * @cmd: [in] DMUB cmd to be populated with SubVP info 6126be153dcSRodrigo Siqueira * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 6136be153dcSRodrigo Siqueira * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 61485f4bc0cSAlvin Lee * 6156be153dcSRodrigo Siqueira * Populate the DMCUB SubVP command with SubVP pipe info. All the information 6166be153dcSRodrigo Siqueira * required to calculate the microschedule for the SubVP pipe is stored in the 6176be153dcSRodrigo Siqueira * pipe_data of the DMCUB SubVP command. 61885f4bc0cSAlvin Lee */ 61985f4bc0cSAlvin Lee static void populate_subvp_cmd_pipe_info(struct dc *dc, 62085f4bc0cSAlvin Lee struct dc_state *context, 62185f4bc0cSAlvin Lee union dmub_rb_cmd *cmd, 62285f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipe, 62385f4bc0cSAlvin Lee uint8_t cmd_pipe_index) 62485f4bc0cSAlvin Lee { 62585f4bc0cSAlvin Lee uint32_t j; 62685f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 62785f4bc0cSAlvin Lee &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 62885f4bc0cSAlvin Lee struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 62985f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 6307857825bSAlvin Lee uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den; 63185f4bc0cSAlvin Lee 63285f4bc0cSAlvin Lee pipe_data->mode = SUBVP; 63385f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; 63485f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; 63585f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; 63685f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.main_vblank_start = 63785f4bc0cSAlvin Lee main_timing->v_total - main_timing->v_front_porch; 63885f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.main_vblank_end = 63985f4bc0cSAlvin Lee main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; 64085f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; 64185f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->pipe_idx; 6429f5171ceSAlvin Lee pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param; 64385f4bc0cSAlvin Lee 644fbe43dcdSAlvin Lee /* Calculate the scaling factor from the src and dst height. 645fbe43dcdSAlvin Lee * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2. 646fbe43dcdSAlvin Lee * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor" 6477857825bSAlvin Lee * 6487857825bSAlvin Lee * Make sure to combine stream and plane scaling together. 649fbe43dcdSAlvin Lee */ 6507857825bSAlvin Lee reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height, 6517857825bSAlvin Lee &out_num_stream, &out_den_stream); 6527857825bSAlvin Lee reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height, 6537857825bSAlvin Lee &out_num_plane, &out_den_plane); 6547857825bSAlvin Lee reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den); 65574f4e84dSAlvin Lee pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num; 65674f4e84dSAlvin Lee pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den; 657fbe43dcdSAlvin Lee 65885f4bc0cSAlvin Lee // Prefetch lines is equal to VACTIVE + BP + VSYNC 65985f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_lines = 66085f4bc0cSAlvin Lee phantom_timing->v_total - phantom_timing->v_front_porch; 66185f4bc0cSAlvin Lee 66285f4bc0cSAlvin Lee // Round up 66385f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 664410e7474SAlvin Lee div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 665410e7474SAlvin Lee ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 66685f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.processing_delay_lines = 667410e7474SAlvin Lee div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 668410e7474SAlvin Lee ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 669b0d6de32SAlvin Lee 670b0d6de32SAlvin Lee if (subvp_pipe->bottom_pipe) { 671b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; 672b0d6de32SAlvin Lee } else if (subvp_pipe->next_odm_pipe) { 673b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; 674b0d6de32SAlvin Lee } else { 675b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0; 676b0d6de32SAlvin Lee } 677b0d6de32SAlvin Lee 67885f4bc0cSAlvin Lee // Find phantom pipe index based on phantom stream 67985f4bc0cSAlvin Lee for (j = 0; j < dc->res_pool->pipe_count; j++) { 68085f4bc0cSAlvin Lee struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; 68185f4bc0cSAlvin Lee 68285f4bc0cSAlvin Lee if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) { 68385f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->pipe_idx; 684b0d6de32SAlvin Lee if (phantom_pipe->bottom_pipe) { 685b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->pipe_idx; 686b0d6de32SAlvin Lee } else if (phantom_pipe->next_odm_pipe) { 687b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->pipe_idx; 688b0d6de32SAlvin Lee } else { 689b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0; 690b0d6de32SAlvin Lee } 69185f4bc0cSAlvin Lee break; 69285f4bc0cSAlvin Lee } 69385f4bc0cSAlvin Lee } 69485f4bc0cSAlvin Lee } 69585f4bc0cSAlvin Lee 69685f4bc0cSAlvin Lee /** 6976be153dcSRodrigo Siqueira * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command 69885f4bc0cSAlvin Lee * 6996be153dcSRodrigo Siqueira * @dc: [in] current dc state 7006be153dcSRodrigo Siqueira * @context: [in] new dc state 70101543dcfSArthur Grillo * @enable: [in] if true enables the pipes population 70285f4bc0cSAlvin Lee * 7036be153dcSRodrigo Siqueira * This function loops through each pipe and populates the DMUB SubVP CMD info 7046be153dcSRodrigo Siqueira * based on the pipe (e.g. SubVP, VBLANK). 70585f4bc0cSAlvin Lee */ 70685f4bc0cSAlvin Lee void dc_dmub_setup_subvp_dmub_command(struct dc *dc, 70785f4bc0cSAlvin Lee struct dc_state *context, 70885f4bc0cSAlvin Lee bool enable) 70985f4bc0cSAlvin Lee { 71085f4bc0cSAlvin Lee uint8_t cmd_pipe_index = 0; 71185f4bc0cSAlvin Lee uint32_t i, pipe_idx; 71285f4bc0cSAlvin Lee uint8_t subvp_count = 0; 71385f4bc0cSAlvin Lee union dmub_rb_cmd cmd; 71485f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipes[2]; 71585f4bc0cSAlvin Lee uint32_t wm_val_refclk = 0; 71685f4bc0cSAlvin Lee 71785f4bc0cSAlvin Lee memset(&cmd, 0, sizeof(cmd)); 71885f4bc0cSAlvin Lee // FW command for SUBVP 71985f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 72085f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD; 72185f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.payload_bytes = 72285f4bc0cSAlvin Lee sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header); 72385f4bc0cSAlvin Lee 72485f4bc0cSAlvin Lee for (i = 0; i < dc->res_pool->pipe_count; i++) { 72585f4bc0cSAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 72685f4bc0cSAlvin Lee 72785f4bc0cSAlvin Lee if (!pipe->stream) 72885f4bc0cSAlvin Lee continue; 72985f4bc0cSAlvin Lee 730b0d6de32SAlvin Lee /* For SubVP pipe count, only count the top most (ODM / MPC) pipe 731b0d6de32SAlvin Lee */ 732b0d6de32SAlvin Lee if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && 73385f4bc0cSAlvin Lee pipe->stream->mall_stream_config.type == SUBVP_MAIN) 73485f4bc0cSAlvin Lee subvp_pipes[subvp_count++] = pipe; 73585f4bc0cSAlvin Lee } 73685f4bc0cSAlvin Lee 73785f4bc0cSAlvin Lee if (enable) { 73885f4bc0cSAlvin Lee // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd 73985f4bc0cSAlvin Lee for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 74085f4bc0cSAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 74185f4bc0cSAlvin Lee 74285f4bc0cSAlvin Lee if (!pipe->stream) 74385f4bc0cSAlvin Lee continue; 74485f4bc0cSAlvin Lee 745b0d6de32SAlvin Lee /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe. 746b0d6de32SAlvin Lee * Any ODM or MPC splits being used in SubVP will be handled internally in 747b0d6de32SAlvin Lee * populate_subvp_cmd_pipe_info 748b0d6de32SAlvin Lee */ 74985f4bc0cSAlvin Lee if (pipe->plane_state && pipe->stream->mall_stream_config.paired_stream && 750b0d6de32SAlvin Lee !pipe->top_pipe && !pipe->prev_odm_pipe && 75185f4bc0cSAlvin Lee pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 75285f4bc0cSAlvin Lee populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 753*9bb10b7aSAyush Gupta } else if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_NONE && 754*9bb10b7aSAyush Gupta !pipe->top_pipe && !pipe->prev_odm_pipe) { 75585f4bc0cSAlvin Lee // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where 75685f4bc0cSAlvin Lee // we run through DML without calculating "natural" P-state support 75785f4bc0cSAlvin Lee populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 75885f4bc0cSAlvin Lee 75985f4bc0cSAlvin Lee } 76085f4bc0cSAlvin Lee pipe_idx++; 76185f4bc0cSAlvin Lee } 76285f4bc0cSAlvin Lee if (subvp_count == 2) { 76385f4bc0cSAlvin Lee update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); 76485f4bc0cSAlvin Lee } 76585f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 76685f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; 76785f4bc0cSAlvin Lee 76885f4bc0cSAlvin Lee // Store the original watermark value for this SubVP config so we can lower it when the 76985f4bc0cSAlvin Lee // MCLK switch starts 77085f4bc0cSAlvin Lee wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * 77197997023SAlvin Lee (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; 77285f4bc0cSAlvin Lee 77385f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; 77485f4bc0cSAlvin Lee } 77585f4bc0cSAlvin Lee dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 77685f4bc0cSAlvin Lee dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 77785f4bc0cSAlvin Lee dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 77885f4bc0cSAlvin Lee } 779bdd0d7e2SAlex Deucher #endif 78085f4bc0cSAlvin Lee 7812631ac1aSAshley Thomas bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) 7822631ac1aSAshley Thomas { 7832631ac1aSAshley Thomas if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) 7842631ac1aSAshley Thomas return false; 7852631ac1aSAshley Thomas return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data); 7862631ac1aSAshley Thomas } 7872631ac1aSAshley Thomas 7882631ac1aSAshley Thomas void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 7892631ac1aSAshley Thomas { 7902631ac1aSAshley Thomas struct dmub_diagnostic_data diag_data = {0}; 7912631ac1aSAshley Thomas 7922631ac1aSAshley Thomas if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 7932631ac1aSAshley Thomas DC_LOG_ERROR("%s: invalid parameters.", __func__); 7942631ac1aSAshley Thomas return; 7952631ac1aSAshley Thomas } 7962631ac1aSAshley Thomas 7972631ac1aSAshley Thomas if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) { 7982631ac1aSAshley Thomas DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); 7992631ac1aSAshley Thomas return; 8002631ac1aSAshley Thomas } 8012631ac1aSAshley Thomas 8022631ac1aSAshley Thomas DC_LOG_DEBUG( 8032631ac1aSAshley Thomas "DMCUB STATE\n" 8042631ac1aSAshley Thomas " dmcub_version : %08x\n" 8052631ac1aSAshley Thomas " scratch [0] : %08x\n" 8062631ac1aSAshley Thomas " scratch [1] : %08x\n" 8072631ac1aSAshley Thomas " scratch [2] : %08x\n" 8082631ac1aSAshley Thomas " scratch [3] : %08x\n" 8092631ac1aSAshley Thomas " scratch [4] : %08x\n" 8102631ac1aSAshley Thomas " scratch [5] : %08x\n" 8112631ac1aSAshley Thomas " scratch [6] : %08x\n" 8122631ac1aSAshley Thomas " scratch [7] : %08x\n" 8132631ac1aSAshley Thomas " scratch [8] : %08x\n" 8142631ac1aSAshley Thomas " scratch [9] : %08x\n" 8152631ac1aSAshley Thomas " scratch [10] : %08x\n" 8162631ac1aSAshley Thomas " scratch [11] : %08x\n" 8172631ac1aSAshley Thomas " scratch [12] : %08x\n" 8182631ac1aSAshley Thomas " scratch [13] : %08x\n" 8192631ac1aSAshley Thomas " scratch [14] : %08x\n" 8202631ac1aSAshley Thomas " scratch [15] : %08x\n" 8212631ac1aSAshley Thomas " pc : %08x\n" 8222631ac1aSAshley Thomas " unk_fault_addr : %08x\n" 8232631ac1aSAshley Thomas " inst_fault_addr : %08x\n" 8242631ac1aSAshley Thomas " data_fault_addr : %08x\n" 8252631ac1aSAshley Thomas " inbox1_rptr : %08x\n" 8262631ac1aSAshley Thomas " inbox1_wptr : %08x\n" 8272631ac1aSAshley Thomas " inbox1_size : %08x\n" 8282631ac1aSAshley Thomas " inbox0_rptr : %08x\n" 8292631ac1aSAshley Thomas " inbox0_wptr : %08x\n" 8302631ac1aSAshley Thomas " inbox0_size : %08x\n" 8312631ac1aSAshley Thomas " is_enabled : %d\n" 8322631ac1aSAshley Thomas " is_soft_reset : %d\n" 8332631ac1aSAshley Thomas " is_secure_reset : %d\n" 8342631ac1aSAshley Thomas " is_traceport_en : %d\n" 8352631ac1aSAshley Thomas " is_cw0_en : %d\n" 8362631ac1aSAshley Thomas " is_cw6_en : %d\n", 8372631ac1aSAshley Thomas diag_data.dmcub_version, 8382631ac1aSAshley Thomas diag_data.scratch[0], 8392631ac1aSAshley Thomas diag_data.scratch[1], 8402631ac1aSAshley Thomas diag_data.scratch[2], 8412631ac1aSAshley Thomas diag_data.scratch[3], 8422631ac1aSAshley Thomas diag_data.scratch[4], 8432631ac1aSAshley Thomas diag_data.scratch[5], 8442631ac1aSAshley Thomas diag_data.scratch[6], 8452631ac1aSAshley Thomas diag_data.scratch[7], 8462631ac1aSAshley Thomas diag_data.scratch[8], 8472631ac1aSAshley Thomas diag_data.scratch[9], 8482631ac1aSAshley Thomas diag_data.scratch[10], 8492631ac1aSAshley Thomas diag_data.scratch[11], 8502631ac1aSAshley Thomas diag_data.scratch[12], 8512631ac1aSAshley Thomas diag_data.scratch[13], 8522631ac1aSAshley Thomas diag_data.scratch[14], 8532631ac1aSAshley Thomas diag_data.scratch[15], 8542631ac1aSAshley Thomas diag_data.pc, 8552631ac1aSAshley Thomas diag_data.undefined_address_fault_addr, 8562631ac1aSAshley Thomas diag_data.inst_fetch_fault_addr, 8572631ac1aSAshley Thomas diag_data.data_write_fault_addr, 8582631ac1aSAshley Thomas diag_data.inbox1_rptr, 8592631ac1aSAshley Thomas diag_data.inbox1_wptr, 8602631ac1aSAshley Thomas diag_data.inbox1_size, 8612631ac1aSAshley Thomas diag_data.inbox0_rptr, 8622631ac1aSAshley Thomas diag_data.inbox0_wptr, 8632631ac1aSAshley Thomas diag_data.inbox0_size, 8642631ac1aSAshley Thomas diag_data.is_dmcub_enabled, 8652631ac1aSAshley Thomas diag_data.is_dmcub_soft_reset, 8662631ac1aSAshley Thomas diag_data.is_dmcub_secure_reset, 8672631ac1aSAshley Thomas diag_data.is_traceport_en, 8682631ac1aSAshley Thomas diag_data.is_cw0_enabled, 8692631ac1aSAshley Thomas diag_data.is_cw6_enabled); 8702631ac1aSAshley Thomas } 871b73353f7SMax Tseng 872f7085cbfSMax Tseng static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) 873f7085cbfSMax Tseng { 874f7085cbfSMax Tseng struct pipe_ctx *test_pipe, *split_pipe; 875f7085cbfSMax Tseng const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; 876f7085cbfSMax Tseng struct rect r1 = scl_data->recout, r2, r2_half; 877f7085cbfSMax Tseng int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b; 878f7085cbfSMax Tseng int cur_layer = pipe_ctx->plane_state->layer_index; 879f7085cbfSMax Tseng 880f7085cbfSMax Tseng /** 881f7085cbfSMax Tseng * Disable the cursor if there's another pipe above this with a 882f7085cbfSMax Tseng * plane that contains this pipe's viewport to prevent double cursor 883f7085cbfSMax Tseng * and incorrect scaling artifacts. 884f7085cbfSMax Tseng */ 885f7085cbfSMax Tseng for (test_pipe = pipe_ctx->top_pipe; test_pipe; 886f7085cbfSMax Tseng test_pipe = test_pipe->top_pipe) { 887f7085cbfSMax Tseng // Skip invisible layer and pipe-split plane on same layer 888f7085cbfSMax Tseng if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer) 889f7085cbfSMax Tseng continue; 890f7085cbfSMax Tseng 891f7085cbfSMax Tseng r2 = test_pipe->plane_res.scl_data.recout; 892f7085cbfSMax Tseng r2_r = r2.x + r2.width; 893f7085cbfSMax Tseng r2_b = r2.y + r2.height; 894f7085cbfSMax Tseng split_pipe = test_pipe; 895f7085cbfSMax Tseng 896f7085cbfSMax Tseng /** 897f7085cbfSMax Tseng * There is another half plane on same layer because of 898f7085cbfSMax Tseng * pipe-split, merge together per same height. 899f7085cbfSMax Tseng */ 900f7085cbfSMax Tseng for (split_pipe = pipe_ctx->top_pipe; split_pipe; 901f7085cbfSMax Tseng split_pipe = split_pipe->top_pipe) 902f7085cbfSMax Tseng if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) { 903f7085cbfSMax Tseng r2_half = split_pipe->plane_res.scl_data.recout; 904f7085cbfSMax Tseng r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x; 905f7085cbfSMax Tseng r2.width = r2.width + r2_half.width; 906f7085cbfSMax Tseng r2_r = r2.x + r2.width; 907f7085cbfSMax Tseng break; 908f7085cbfSMax Tseng } 909f7085cbfSMax Tseng 910f7085cbfSMax Tseng if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b) 911f7085cbfSMax Tseng return true; 912f7085cbfSMax Tseng } 913f7085cbfSMax Tseng 914f7085cbfSMax Tseng return false; 915f7085cbfSMax Tseng } 916f7085cbfSMax Tseng 917b73353f7SMax Tseng static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx) 918b73353f7SMax Tseng { 919b73353f7SMax Tseng if (pipe_ctx->plane_state != NULL) { 920b73353f7SMax Tseng if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 921b73353f7SMax Tseng return false; 922f7085cbfSMax Tseng 923f7085cbfSMax Tseng if (dc_can_pipe_disable_cursor(pipe_ctx)) 924f7085cbfSMax Tseng return false; 925b73353f7SMax Tseng } 926b73353f7SMax Tseng 927b73353f7SMax Tseng if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || 928b73353f7SMax Tseng pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) && 929b73353f7SMax Tseng pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1) 930b73353f7SMax Tseng return true; 931b73353f7SMax Tseng 932b73353f7SMax Tseng return false; 933b73353f7SMax Tseng } 934b73353f7SMax Tseng 935b73353f7SMax Tseng static void dc_build_cursor_update_payload0( 936b73353f7SMax Tseng struct pipe_ctx *pipe_ctx, uint8_t p_idx, 937b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 *payload) 938b73353f7SMax Tseng { 939b73353f7SMax Tseng struct hubp *hubp = pipe_ctx->plane_res.hubp; 940b73353f7SMax Tseng unsigned int panel_inst = 0; 941b73353f7SMax Tseng 942b73353f7SMax Tseng if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, 943b73353f7SMax Tseng pipe_ctx->stream->link, &panel_inst)) 944b73353f7SMax Tseng return; 945b73353f7SMax Tseng 946b73353f7SMax Tseng /* Payload: Cursor Rect is built from position & attribute 947b73353f7SMax Tseng * x & y are obtained from postion 948b73353f7SMax Tseng */ 949b73353f7SMax Tseng payload->cursor_rect.x = hubp->cur_rect.x; 950b73353f7SMax Tseng payload->cursor_rect.y = hubp->cur_rect.y; 951b73353f7SMax Tseng /* w & h are obtained from attribute */ 952b73353f7SMax Tseng payload->cursor_rect.width = hubp->cur_rect.w; 953b73353f7SMax Tseng payload->cursor_rect.height = hubp->cur_rect.h; 954b73353f7SMax Tseng 955b73353f7SMax Tseng payload->enable = hubp->pos.cur_ctl.bits.cur_enable; 956b73353f7SMax Tseng payload->pipe_idx = p_idx; 957b73353f7SMax Tseng payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 958b73353f7SMax Tseng payload->panel_inst = panel_inst; 959b73353f7SMax Tseng } 960b73353f7SMax Tseng 961b73353f7SMax Tseng static void dc_send_cmd_to_dmu(struct dc_dmub_srv *dmub_srv, 962b73353f7SMax Tseng union dmub_rb_cmd *cmd) 963b73353f7SMax Tseng { 964b73353f7SMax Tseng dc_dmub_srv_cmd_queue(dmub_srv, cmd); 965b73353f7SMax Tseng dc_dmub_srv_cmd_execute(dmub_srv); 966b73353f7SMax Tseng dc_dmub_srv_wait_idle(dmub_srv); 967b73353f7SMax Tseng } 968b73353f7SMax Tseng 969b73353f7SMax Tseng static void dc_build_cursor_position_update_payload0( 970b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx, 971b73353f7SMax Tseng const struct hubp *hubp, const struct dpp *dpp) 972b73353f7SMax Tseng { 973b73353f7SMax Tseng /* Hubp */ 974b73353f7SMax Tseng pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw; 975b73353f7SMax Tseng pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw; 976b73353f7SMax Tseng pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw; 977b73353f7SMax Tseng pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw; 978b73353f7SMax Tseng 979b73353f7SMax Tseng /* dpp */ 980b73353f7SMax Tseng pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw; 981b73353f7SMax Tseng pl->position_cfg.pipe_idx = p_idx; 982b73353f7SMax Tseng } 983b73353f7SMax Tseng 984b73353f7SMax Tseng static void dc_build_cursor_attribute_update_payload1( 985b73353f7SMax Tseng struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx, 986b73353f7SMax Tseng const struct hubp *hubp, const struct dpp *dpp) 987b73353f7SMax Tseng { 988b73353f7SMax Tseng /* Hubp */ 989b73353f7SMax Tseng pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH; 990b73353f7SMax Tseng pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR; 991b73353f7SMax Tseng pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw; 992b73353f7SMax Tseng pl_A->aHubp.size.raw = hubp->att.size.raw; 993b73353f7SMax Tseng pl_A->aHubp.settings.raw = hubp->att.settings.raw; 994b73353f7SMax Tseng 995b73353f7SMax Tseng /* dpp */ 996b73353f7SMax Tseng pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw; 997b73353f7SMax Tseng } 998b73353f7SMax Tseng 999b73353f7SMax Tseng /** 10006be153dcSRodrigo Siqueira * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command 1001b73353f7SMax Tseng * 10026be153dcSRodrigo Siqueira * @pCtx: [in] pipe context 10036be153dcSRodrigo Siqueira * @pipe_idx: [in] pipe index 1004b73353f7SMax Tseng * 10056be153dcSRodrigo Siqueira * This function would store the cursor related information and pass it into 10066be153dcSRodrigo Siqueira * dmub 1007b73353f7SMax Tseng */ 1008b73353f7SMax Tseng void dc_send_update_cursor_info_to_dmu( 1009b73353f7SMax Tseng struct pipe_ctx *pCtx, uint8_t pipe_idx) 1010b73353f7SMax Tseng { 1011b73353f7SMax Tseng union dmub_rb_cmd cmd = { 0 }; 1012b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data *update_cursor_info = 1013b73353f7SMax Tseng &cmd.update_cursor_info.update_cursor_info_data; 1014b73353f7SMax Tseng 1015b73353f7SMax Tseng if (!dc_dmub_should_update_cursor_data(pCtx)) 1016b73353f7SMax Tseng return; 1017b73353f7SMax Tseng /* 1018b73353f7SMax Tseng * Since we use multi_cmd_pending for dmub command, the 2nd command is 1019b73353f7SMax Tseng * only assigned to store cursor attributes info. 1020b73353f7SMax Tseng * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other 1021b73353f7SMax Tseng * is to store cursor position info. 1022b73353f7SMax Tseng * 1023b73353f7SMax Tseng * Command heaer type must be the same type if using multi_cmd_pending. 1024b73353f7SMax Tseng * Besides, while process 2nd command in DMU, the sub type is useless. 1025b73353f7SMax Tseng * So it's meanless to pass the sub type header with different type. 1026b73353f7SMax Tseng */ 1027b73353f7SMax Tseng 1028b73353f7SMax Tseng { 1029b73353f7SMax Tseng /* Build Payload#0 Header */ 1030b73353f7SMax Tseng cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 1031b73353f7SMax Tseng cmd.update_cursor_info.header.payload_bytes = 1032b73353f7SMax Tseng sizeof(cmd.update_cursor_info.update_cursor_info_data); 1033b73353f7SMax Tseng cmd.update_cursor_info.header.multi_cmd_pending = 1; /* To combine multi dmu cmd, 1st cmd */ 1034b73353f7SMax Tseng 1035b73353f7SMax Tseng /* Prepare Payload */ 1036b73353f7SMax Tseng dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info->payload0); 1037b73353f7SMax Tseng 1038b73353f7SMax Tseng dc_build_cursor_position_update_payload0(&update_cursor_info->payload0, pipe_idx, 1039b73353f7SMax Tseng pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1040b73353f7SMax Tseng /* Send update_curosr_info to queue */ 1041b73353f7SMax Tseng dc_dmub_srv_cmd_queue(pCtx->stream->ctx->dmub_srv, &cmd); 1042b73353f7SMax Tseng } 1043b73353f7SMax Tseng { 1044b73353f7SMax Tseng /* Build Payload#1 Header */ 1045b73353f7SMax Tseng memset(update_cursor_info, 0, sizeof(union dmub_cmd_update_cursor_info_data)); 1046b73353f7SMax Tseng cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 1047b73353f7SMax Tseng cmd.update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg); 1048b73353f7SMax Tseng cmd.update_cursor_info.header.multi_cmd_pending = 0; /* Indicate it's the last command. */ 1049b73353f7SMax Tseng 1050b73353f7SMax Tseng dc_build_cursor_attribute_update_payload1( 1051b73353f7SMax Tseng &cmd.update_cursor_info.update_cursor_info_data.payload1.attribute_cfg, 1052b73353f7SMax Tseng pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1053b73353f7SMax Tseng 1054b73353f7SMax Tseng /* Combine 2nd cmds update_curosr_info to DMU */ 1055b73353f7SMax Tseng dc_send_cmd_to_dmu(pCtx->stream->ctx->dmub_srv, &cmd); 1056b73353f7SMax Tseng } 1057b73353f7SMax Tseng } 1058