13a1627b0SNicholas Kazlauskas /* 23a1627b0SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 33a1627b0SNicholas Kazlauskas * 43a1627b0SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 53a1627b0SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 63a1627b0SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 73a1627b0SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 83a1627b0SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 93a1627b0SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 103a1627b0SNicholas Kazlauskas * 113a1627b0SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 123a1627b0SNicholas Kazlauskas * all copies or substantial portions of the Software. 133a1627b0SNicholas Kazlauskas * 143a1627b0SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 153a1627b0SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 163a1627b0SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 173a1627b0SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 183a1627b0SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 193a1627b0SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 203a1627b0SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 213a1627b0SNicholas Kazlauskas * 223a1627b0SNicholas Kazlauskas * Authors: AMD 233a1627b0SNicholas Kazlauskas * 243a1627b0SNicholas Kazlauskas */ 253a1627b0SNicholas Kazlauskas 263a1627b0SNicholas Kazlauskas #include "dc.h" 273a1627b0SNicholas Kazlauskas #include "dc_dmub_srv.h" 28cdca3f21SAnthony Koo #include "../dmub/dmub_srv.h" 2970732504SYongqiang Sun #include "dm_helpers.h" 30c2fbe663SFelipe Clark #include "dc_hw_types.h" 31c2fbe663SFelipe Clark #include "core_types.h" 323a1627b0SNicholas Kazlauskas 33ecdfc5c9SNicholas Kazlauskas #define CTX dc_dmub_srv->ctx 34ecdfc5c9SNicholas Kazlauskas #define DC_LOGGER CTX->logger 35ecdfc5c9SNicholas Kazlauskas 363a1627b0SNicholas Kazlauskas static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, 373a1627b0SNicholas Kazlauskas struct dmub_srv *dmub) 383a1627b0SNicholas Kazlauskas { 393a1627b0SNicholas Kazlauskas dc_srv->dmub = dmub; 403a1627b0SNicholas Kazlauskas dc_srv->ctx = dc->ctx; 413a1627b0SNicholas Kazlauskas } 423a1627b0SNicholas Kazlauskas 433a1627b0SNicholas Kazlauskas struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) 443a1627b0SNicholas Kazlauskas { 453a1627b0SNicholas Kazlauskas struct dc_dmub_srv *dc_srv = 463a1627b0SNicholas Kazlauskas kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL); 473a1627b0SNicholas Kazlauskas 483a1627b0SNicholas Kazlauskas if (dc_srv == NULL) { 493a1627b0SNicholas Kazlauskas BREAK_TO_DEBUGGER(); 503a1627b0SNicholas Kazlauskas return NULL; 513a1627b0SNicholas Kazlauskas } 523a1627b0SNicholas Kazlauskas 533a1627b0SNicholas Kazlauskas dc_dmub_srv_construct(dc_srv, dc, dmub); 543a1627b0SNicholas Kazlauskas 553a1627b0SNicholas Kazlauskas return dc_srv; 563a1627b0SNicholas Kazlauskas } 573a1627b0SNicholas Kazlauskas 583a1627b0SNicholas Kazlauskas void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv) 593a1627b0SNicholas Kazlauskas { 603a1627b0SNicholas Kazlauskas if (*dmub_srv) { 613a1627b0SNicholas Kazlauskas kfree(*dmub_srv); 623a1627b0SNicholas Kazlauskas *dmub_srv = NULL; 633a1627b0SNicholas Kazlauskas } 643a1627b0SNicholas Kazlauskas } 653a1627b0SNicholas Kazlauskas 663a1627b0SNicholas Kazlauskas void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv, 670ed3bcc4SNicholas Kazlauskas union dmub_rb_cmd *cmd) 683a1627b0SNicholas Kazlauskas { 693a1627b0SNicholas Kazlauskas struct dmub_srv *dmub = dc_dmub_srv->dmub; 703a1627b0SNicholas Kazlauskas struct dc_context *dc_ctx = dc_dmub_srv->ctx; 713a1627b0SNicholas Kazlauskas enum dmub_status status; 723a1627b0SNicholas Kazlauskas 733a1627b0SNicholas Kazlauskas status = dmub_srv_cmd_queue(dmub, cmd); 743a1627b0SNicholas Kazlauskas if (status == DMUB_STATUS_OK) 753a1627b0SNicholas Kazlauskas return; 763a1627b0SNicholas Kazlauskas 773a1627b0SNicholas Kazlauskas if (status != DMUB_STATUS_QUEUE_FULL) 783a1627b0SNicholas Kazlauskas goto error; 793a1627b0SNicholas Kazlauskas 803a1627b0SNicholas Kazlauskas /* Execute and wait for queue to become empty again. */ 813a1627b0SNicholas Kazlauskas dc_dmub_srv_cmd_execute(dc_dmub_srv); 823a1627b0SNicholas Kazlauskas dc_dmub_srv_wait_idle(dc_dmub_srv); 833a1627b0SNicholas Kazlauskas 843a1627b0SNicholas Kazlauskas /* Requeue the command. */ 853a1627b0SNicholas Kazlauskas status = dmub_srv_cmd_queue(dmub, cmd); 863a1627b0SNicholas Kazlauskas if (status == DMUB_STATUS_OK) 873a1627b0SNicholas Kazlauskas return; 883a1627b0SNicholas Kazlauskas 893a1627b0SNicholas Kazlauskas error: 903a1627b0SNicholas Kazlauskas DC_ERROR("Error queuing DMUB command: status=%d\n", status); 912631ac1aSAshley Thomas dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 923a1627b0SNicholas Kazlauskas } 933a1627b0SNicholas Kazlauskas 943a1627b0SNicholas Kazlauskas void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv) 953a1627b0SNicholas Kazlauskas { 963a1627b0SNicholas Kazlauskas struct dmub_srv *dmub = dc_dmub_srv->dmub; 973a1627b0SNicholas Kazlauskas struct dc_context *dc_ctx = dc_dmub_srv->ctx; 983a1627b0SNicholas Kazlauskas enum dmub_status status; 993a1627b0SNicholas Kazlauskas 1003a1627b0SNicholas Kazlauskas status = dmub_srv_cmd_execute(dmub); 1012631ac1aSAshley Thomas if (status != DMUB_STATUS_OK) { 102243a8f41SColin Ian King DC_ERROR("Error starting DMUB execution: status=%d\n", status); 1032631ac1aSAshley Thomas dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 1042631ac1aSAshley Thomas } 1053a1627b0SNicholas Kazlauskas } 1063a1627b0SNicholas Kazlauskas 1073a1627b0SNicholas Kazlauskas void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) 1083a1627b0SNicholas Kazlauskas { 1093a1627b0SNicholas Kazlauskas struct dmub_srv *dmub = dc_dmub_srv->dmub; 1103a1627b0SNicholas Kazlauskas struct dc_context *dc_ctx = dc_dmub_srv->ctx; 1113a1627b0SNicholas Kazlauskas enum dmub_status status; 1123a1627b0SNicholas Kazlauskas 1133a1627b0SNicholas Kazlauskas status = dmub_srv_wait_for_idle(dmub, 100000); 1142631ac1aSAshley Thomas if (status != DMUB_STATUS_OK) { 1153a1627b0SNicholas Kazlauskas DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); 1162631ac1aSAshley Thomas dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 1172631ac1aSAshley Thomas } 1183a1627b0SNicholas Kazlauskas } 1193a1627b0SNicholas Kazlauskas 120d493a024SAlvin Lee void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv) 121d493a024SAlvin Lee { 122d493a024SAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub; 123d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx; 124d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK; 125d493a024SAlvin Lee 126d493a024SAlvin Lee status = dmub_srv_clear_inbox0_ack(dmub); 127d493a024SAlvin Lee if (status != DMUB_STATUS_OK) { 128d493a024SAlvin Lee DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status); 129d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv); 130d493a024SAlvin Lee } 131d493a024SAlvin Lee } 132d493a024SAlvin Lee 133d493a024SAlvin Lee void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv) 134d493a024SAlvin Lee { 135d493a024SAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub; 136d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx; 137d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK; 138d493a024SAlvin Lee 139d493a024SAlvin Lee status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); 140d493a024SAlvin Lee if (status != DMUB_STATUS_OK) { 141d493a024SAlvin Lee DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n"); 142d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv); 143d493a024SAlvin Lee } 144d493a024SAlvin Lee } 145d493a024SAlvin Lee 146f2973d2aSAlvin Lee void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, 147f2973d2aSAlvin Lee union dmub_inbox0_data_register data) 148f2973d2aSAlvin Lee { 149f2973d2aSAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub; 150d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx; 151d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK; 152d493a024SAlvin Lee 153d493a024SAlvin Lee status = dmub_srv_send_inbox0_cmd(dmub, data); 154d493a024SAlvin Lee if (status != DMUB_STATUS_OK) { 155d493a024SAlvin Lee DC_ERROR("Error sending INBOX0 cmd\n"); 156d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv); 157d493a024SAlvin Lee } 158f2973d2aSAlvin Lee } 159f2973d2aSAlvin Lee 160ecdfc5c9SNicholas Kazlauskas bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd) 161ecdfc5c9SNicholas Kazlauskas { 162ecdfc5c9SNicholas Kazlauskas struct dmub_srv *dmub; 163ecdfc5c9SNicholas Kazlauskas enum dmub_status status; 164ecdfc5c9SNicholas Kazlauskas 165ecdfc5c9SNicholas Kazlauskas if (!dc_dmub_srv || !dc_dmub_srv->dmub) 166ecdfc5c9SNicholas Kazlauskas return false; 167ecdfc5c9SNicholas Kazlauskas 168ecdfc5c9SNicholas Kazlauskas dmub = dc_dmub_srv->dmub; 169ecdfc5c9SNicholas Kazlauskas 170ecdfc5c9SNicholas Kazlauskas status = dmub_srv_cmd_with_reply_data(dmub, cmd); 171ecdfc5c9SNicholas Kazlauskas if (status != DMUB_STATUS_OK) { 172ecdfc5c9SNicholas Kazlauskas DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 173ecdfc5c9SNicholas Kazlauskas return false; 174ecdfc5c9SNicholas Kazlauskas } 175ecdfc5c9SNicholas Kazlauskas 176ecdfc5c9SNicholas Kazlauskas return true; 177ecdfc5c9SNicholas Kazlauskas } 178ecdfc5c9SNicholas Kazlauskas 1793a1627b0SNicholas Kazlauskas void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv) 1803a1627b0SNicholas Kazlauskas { 1813a1627b0SNicholas Kazlauskas struct dmub_srv *dmub = dc_dmub_srv->dmub; 1823a1627b0SNicholas Kazlauskas struct dc_context *dc_ctx = dc_dmub_srv->ctx; 1833a1627b0SNicholas Kazlauskas enum dmub_status status; 1843a1627b0SNicholas Kazlauskas 185a6e4da40SNicholas Kazlauskas for (;;) { 186a6e4da40SNicholas Kazlauskas /* Wait up to a second for PHY init. */ 187a6e4da40SNicholas Kazlauskas status = dmub_srv_wait_for_phy_init(dmub, 1000000); 188a6e4da40SNicholas Kazlauskas if (status == DMUB_STATUS_OK) 189a6e4da40SNicholas Kazlauskas /* Initialization OK */ 190a6e4da40SNicholas Kazlauskas break; 191a6e4da40SNicholas Kazlauskas 192a6e4da40SNicholas Kazlauskas DC_ERROR("DMCUB PHY init failed: status=%d\n", status); 19356fc13feSNicholas Kazlauskas ASSERT(0); 194a6e4da40SNicholas Kazlauskas 195a6e4da40SNicholas Kazlauskas if (status != DMUB_STATUS_TIMEOUT) 196a6e4da40SNicholas Kazlauskas /* 197a6e4da40SNicholas Kazlauskas * Server likely initialized or we don't have 198a6e4da40SNicholas Kazlauskas * DMCUB HW support - this won't end. 199a6e4da40SNicholas Kazlauskas */ 200a6e4da40SNicholas Kazlauskas break; 201a6e4da40SNicholas Kazlauskas 202a6e4da40SNicholas Kazlauskas /* Continue spinning so we don't hang the ASIC. */ 20356fc13feSNicholas Kazlauskas } 2043a1627b0SNicholas Kazlauskas } 2050825d965SEric Yang 2060825d965SEric Yang bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 2070825d965SEric Yang unsigned int stream_mask) 2080825d965SEric Yang { 2090825d965SEric Yang struct dmub_srv *dmub; 2100825d965SEric Yang const uint32_t timeout = 30; 2110825d965SEric Yang 2120825d965SEric Yang if (!dc_dmub_srv || !dc_dmub_srv->dmub) 2130825d965SEric Yang return false; 2140825d965SEric Yang 2150825d965SEric Yang dmub = dc_dmub_srv->dmub; 2160825d965SEric Yang 2170825d965SEric Yang return dmub_srv_send_gpint_command( 2180825d965SEric Yang dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, 2190825d965SEric Yang stream_mask, timeout) == DMUB_STATUS_OK; 2200825d965SEric Yang } 2218fe44c08SAlex Deucher 222b04cb192SNicholas Kazlauskas bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) 223b04cb192SNicholas Kazlauskas { 224b04cb192SNicholas Kazlauskas struct dmub_srv *dmub; 225b04cb192SNicholas Kazlauskas struct dc_context *dc_ctx; 226b04cb192SNicholas Kazlauskas union dmub_fw_boot_status boot_status; 227b04cb192SNicholas Kazlauskas enum dmub_status status; 228b04cb192SNicholas Kazlauskas 229b04cb192SNicholas Kazlauskas if (!dc_dmub_srv || !dc_dmub_srv->dmub) 230b04cb192SNicholas Kazlauskas return false; 231b04cb192SNicholas Kazlauskas 232b04cb192SNicholas Kazlauskas dmub = dc_dmub_srv->dmub; 233b04cb192SNicholas Kazlauskas dc_ctx = dc_dmub_srv->ctx; 234b04cb192SNicholas Kazlauskas 235b04cb192SNicholas Kazlauskas status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 236b04cb192SNicholas Kazlauskas if (status != DMUB_STATUS_OK) { 237b04cb192SNicholas Kazlauskas DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 238b04cb192SNicholas Kazlauskas return false; 239b04cb192SNicholas Kazlauskas } 240b04cb192SNicholas Kazlauskas 241b04cb192SNicholas Kazlauskas return boot_status.bits.restore_required; 242b04cb192SNicholas Kazlauskas } 24370732504SYongqiang Sun 2446804287bSYongqiang Sun bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) 24570732504SYongqiang Sun { 24670732504SYongqiang Sun struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; 2476804287bSYongqiang Sun return dmub_srv_get_outbox0_msg(dmub, entry); 24870732504SYongqiang Sun } 24970732504SYongqiang Sun 25070732504SYongqiang Sun void dc_dmub_trace_event_control(struct dc *dc, bool enable) 25170732504SYongqiang Sun { 25281927e28SJude Shih dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); 25370732504SYongqiang Sun } 2542631ac1aSAshley Thomas 255*00fa7f03SRodrigo Siqueira void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) 256*00fa7f03SRodrigo Siqueira { 257*00fa7f03SRodrigo Siqueira union dmub_rb_cmd cmd = { 0 }; 258*00fa7f03SRodrigo Siqueira 259*00fa7f03SRodrigo Siqueira cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 260*00fa7f03SRodrigo Siqueira cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE; 261*00fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 262*00fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 263*00fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 264*00fa7f03SRodrigo Siqueira 265*00fa7f03SRodrigo Siqueira cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 266*00fa7f03SRodrigo Siqueira 267*00fa7f03SRodrigo Siqueira // Send the command to the DMCUB. 268*00fa7f03SRodrigo Siqueira dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 269*00fa7f03SRodrigo Siqueira dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 270*00fa7f03SRodrigo Siqueira dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 271*00fa7f03SRodrigo Siqueira } 272*00fa7f03SRodrigo Siqueira 273*00fa7f03SRodrigo Siqueira uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) 274*00fa7f03SRodrigo Siqueira { 275*00fa7f03SRodrigo Siqueira uint8_t pipes = 0; 276*00fa7f03SRodrigo Siqueira int i = 0; 277*00fa7f03SRodrigo Siqueira 278*00fa7f03SRodrigo Siqueira for (i = 0; i < MAX_PIPES; i++) { 279*00fa7f03SRodrigo Siqueira struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 280*00fa7f03SRodrigo Siqueira 281*00fa7f03SRodrigo Siqueira if (pipe->stream == stream && pipe->stream_res.tg) 282*00fa7f03SRodrigo Siqueira pipes = i; 283*00fa7f03SRodrigo Siqueira } 284*00fa7f03SRodrigo Siqueira return pipes; 285*00fa7f03SRodrigo Siqueira } 286*00fa7f03SRodrigo Siqueira 287*00fa7f03SRodrigo Siqueira int dc_dmub_srv_get_timing_generator_offset(struct dc *dc, struct dc_stream_state *stream) 288*00fa7f03SRodrigo Siqueira { 289*00fa7f03SRodrigo Siqueira int tg_inst = 0; 290*00fa7f03SRodrigo Siqueira int i = 0; 291*00fa7f03SRodrigo Siqueira 292*00fa7f03SRodrigo Siqueira for (i = 0; i < MAX_PIPES; i++) { 293*00fa7f03SRodrigo Siqueira struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 294*00fa7f03SRodrigo Siqueira 295*00fa7f03SRodrigo Siqueira if (pipe->stream == stream && pipe->stream_res.tg) { 296*00fa7f03SRodrigo Siqueira tg_inst = pipe->stream_res.tg->inst; 297*00fa7f03SRodrigo Siqueira break; 298*00fa7f03SRodrigo Siqueira } 299*00fa7f03SRodrigo Siqueira } 300*00fa7f03SRodrigo Siqueira return tg_inst; 301*00fa7f03SRodrigo Siqueira } 302*00fa7f03SRodrigo Siqueira 303*00fa7f03SRodrigo Siqueira bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) 304*00fa7f03SRodrigo Siqueira { 305*00fa7f03SRodrigo Siqueira union dmub_rb_cmd cmd = { 0 }; 306*00fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; 307*00fa7f03SRodrigo Siqueira int i = 0; 308*00fa7f03SRodrigo Siqueira int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. 309*00fa7f03SRodrigo Siqueira uint8_t visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; 310*00fa7f03SRodrigo Siqueira 311*00fa7f03SRodrigo Siqueira if (dc == NULL) 312*00fa7f03SRodrigo Siqueira return false; 313*00fa7f03SRodrigo Siqueira 314*00fa7f03SRodrigo Siqueira // Format command. 315*00fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 316*00fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL; 317*00fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate; 318*00fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; 319*00fa7f03SRodrigo Siqueira 320*00fa7f03SRodrigo Siqueira for (i = 0; context && i < context->stream_count; i++) { 321*00fa7f03SRodrigo Siqueira struct dc_stream_state *stream = context->streams[i]; 322*00fa7f03SRodrigo Siqueira uint8_t min_refresh_in_hz = (stream->timing.min_refresh_in_uhz + 999999) / 1000000; 323*00fa7f03SRodrigo Siqueira int tg_inst = dc_dmub_srv_get_timing_generator_offset(dc, stream); 324*00fa7f03SRodrigo Siqueira 325*00fa7f03SRodrigo Siqueira config_data->pipe_data[tg_inst].pix_clk_100hz = stream->timing.pix_clk_100hz; 326*00fa7f03SRodrigo Siqueira config_data->pipe_data[tg_inst].min_refresh_in_hz = min_refresh_in_hz; 327*00fa7f03SRodrigo Siqueira config_data->pipe_data[tg_inst].max_ramp_step = ramp_up_num_steps; 328*00fa7f03SRodrigo Siqueira config_data->pipe_data[tg_inst].pipes = dc_dmub_srv_get_pipes_for_stream(dc, stream); 329*00fa7f03SRodrigo Siqueira } 330*00fa7f03SRodrigo Siqueira 331*00fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.payload_bytes = 332*00fa7f03SRodrigo Siqueira sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header); 333*00fa7f03SRodrigo Siqueira 334*00fa7f03SRodrigo Siqueira // Send the command to the DMCUB. 335*00fa7f03SRodrigo Siqueira dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 336*00fa7f03SRodrigo Siqueira dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 337*00fa7f03SRodrigo Siqueira dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 338*00fa7f03SRodrigo Siqueira 339*00fa7f03SRodrigo Siqueira return true; 340*00fa7f03SRodrigo Siqueira } 341*00fa7f03SRodrigo Siqueira 342ac2e555eSAurabindo Pillai void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub) 343ac2e555eSAurabindo Pillai { 344ac2e555eSAurabindo Pillai union dmub_rb_cmd cmd = { 0 }; 345ac2e555eSAurabindo Pillai enum dmub_status status; 346ac2e555eSAurabindo Pillai 347ac2e555eSAurabindo Pillai if (!dmub) { 348ac2e555eSAurabindo Pillai return; 349ac2e555eSAurabindo Pillai } 350ac2e555eSAurabindo Pillai 351ac2e555eSAurabindo Pillai memset(&cmd, 0, sizeof(cmd)); 352ac2e555eSAurabindo Pillai 353ac2e555eSAurabindo Pillai /* Prepare fw command */ 354ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; 355ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.sub_type = 0; 356ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.ret_status = 1; 357ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); 358ac2e555eSAurabindo Pillai 359ac2e555eSAurabindo Pillai /* Send command to fw */ 360ac2e555eSAurabindo Pillai status = dmub_srv_cmd_with_reply_data(dmub, &cmd); 361ac2e555eSAurabindo Pillai 362ac2e555eSAurabindo Pillai ASSERT(status == DMUB_STATUS_OK); 363ac2e555eSAurabindo Pillai 364ac2e555eSAurabindo Pillai /* If command was processed, copy feature caps to dmub srv */ 365ac2e555eSAurabindo Pillai if (status == DMUB_STATUS_OK && 366ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.ret_status == 0) { 367ac2e555eSAurabindo Pillai memcpy(&dmub->feature_caps, 368ac2e555eSAurabindo Pillai &cmd.query_feature_caps.query_feature_caps_data, 369ac2e555eSAurabindo Pillai sizeof(struct dmub_feature_caps)); 370ac2e555eSAurabindo Pillai } 371ac2e555eSAurabindo Pillai } 372ac2e555eSAurabindo Pillai 37385f4bc0cSAlvin Lee /** 37485f4bc0cSAlvin Lee * *********************************************************************************************** 37585f4bc0cSAlvin Lee * populate_subvp_cmd_drr_info: Helper to populate DRR pipe info for the DMCUB subvp command 37685f4bc0cSAlvin Lee * 37785f4bc0cSAlvin Lee * Populate the DMCUB SubVP command with DRR pipe info. All the information required for calculating 37885f4bc0cSAlvin Lee * the SubVP + DRR microschedule is populated here. 37985f4bc0cSAlvin Lee * 38085f4bc0cSAlvin Lee * High level algorithm: 38185f4bc0cSAlvin Lee * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 38285f4bc0cSAlvin Lee * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule 38385f4bc0cSAlvin Lee * 3. Populate the drr_info with the min and max supported vtotal values 38485f4bc0cSAlvin Lee * 38585f4bc0cSAlvin Lee * @param [in] dc: current dc state 38685f4bc0cSAlvin Lee * @param [in] subvp_pipe: pipe_ctx for the SubVP pipe 38785f4bc0cSAlvin Lee * @param [in] vblank_pipe: pipe_ctx for the DRR pipe 38885f4bc0cSAlvin Lee * @param [in] pipe_data: Pipe data which stores the VBLANK/DRR info 38985f4bc0cSAlvin Lee * 39085f4bc0cSAlvin Lee * @return: void 39185f4bc0cSAlvin Lee * 39285f4bc0cSAlvin Lee * *********************************************************************************************** 39385f4bc0cSAlvin Lee */ 39485f4bc0cSAlvin Lee static void populate_subvp_cmd_drr_info(struct dc *dc, 39585f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipe, 39685f4bc0cSAlvin Lee struct pipe_ctx *vblank_pipe, 39785f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data) 39885f4bc0cSAlvin Lee { 39985f4bc0cSAlvin Lee struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 40085f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 40185f4bc0cSAlvin Lee struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 40285f4bc0cSAlvin Lee int16_t drr_frame_us = 0; 40385f4bc0cSAlvin Lee int16_t min_drr_supported_us = 0; 40485f4bc0cSAlvin Lee int16_t max_drr_supported_us = 0; 40585f4bc0cSAlvin Lee int16_t max_drr_vblank_us = 0; 40685f4bc0cSAlvin Lee int16_t max_drr_mallregion_us = 0; 40785f4bc0cSAlvin Lee int16_t mall_region_us = 0; 40885f4bc0cSAlvin Lee int16_t prefetch_us = 0; 40985f4bc0cSAlvin Lee int16_t subvp_active_us = 0; 41085f4bc0cSAlvin Lee int16_t drr_active_us = 0; 41185f4bc0cSAlvin Lee int16_t min_vtotal_supported = 0; 41285f4bc0cSAlvin Lee int16_t max_vtotal_supported = 0; 41385f4bc0cSAlvin Lee 41485f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; 41585f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping 41685f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now 41785f4bc0cSAlvin Lee 41885f4bc0cSAlvin Lee drr_frame_us = drr_timing->v_total * drr_timing->h_total / 41985f4bc0cSAlvin Lee (double)(drr_timing->pix_clk_100hz * 100) * 1000000; 42085f4bc0cSAlvin Lee // P-State allow width and FW delays already included phantom_timing->v_addressable 42185f4bc0cSAlvin Lee mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / 42285f4bc0cSAlvin Lee (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; 42385f4bc0cSAlvin Lee min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 42485f4bc0cSAlvin Lee min_vtotal_supported = drr_timing->pix_clk_100hz * 100 * ((double)min_drr_supported_us / 1000000) / 42585f4bc0cSAlvin Lee (double)drr_timing->h_total; 42685f4bc0cSAlvin Lee 42785f4bc0cSAlvin Lee prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / 42885f4bc0cSAlvin Lee (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + 42985f4bc0cSAlvin Lee dc->caps.subvp_prefetch_end_to_mall_start_us; 43085f4bc0cSAlvin Lee subvp_active_us = main_timing->v_addressable * main_timing->h_total / 43185f4bc0cSAlvin Lee (double)(main_timing->pix_clk_100hz * 100) * 1000000; 43285f4bc0cSAlvin Lee drr_active_us = drr_timing->v_addressable * drr_timing->h_total / 43385f4bc0cSAlvin Lee (double)(drr_timing->pix_clk_100hz * 100) * 1000000; 43485f4bc0cSAlvin Lee max_drr_vblank_us = (double)(subvp_active_us - prefetch_us - drr_active_us) / 2 + drr_active_us; 43585f4bc0cSAlvin Lee max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us; 43685f4bc0cSAlvin Lee max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; 43785f4bc0cSAlvin Lee max_vtotal_supported = drr_timing->pix_clk_100hz * 100 * ((double)max_drr_supported_us / 1000000) / 43885f4bc0cSAlvin Lee (double)drr_timing->h_total; 43985f4bc0cSAlvin Lee 44085f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; 44185f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; 44285f4bc0cSAlvin Lee } 44385f4bc0cSAlvin Lee 44485f4bc0cSAlvin Lee /** 44585f4bc0cSAlvin Lee * *********************************************************************************************** 44685f4bc0cSAlvin Lee * populate_subvp_cmd_vblank_pipe_info: Helper to populate VBLANK pipe info for the DMUB subvp command 44785f4bc0cSAlvin Lee * 44885f4bc0cSAlvin Lee * Populate the DMCUB SubVP command with VBLANK pipe info. All the information required to calculate 44985f4bc0cSAlvin Lee * the microschedule for SubVP + VBLANK case is stored in the pipe_data (subvp_data and vblank_data). 45085f4bc0cSAlvin Lee * Also check if the VBLANK pipe is a DRR display -- if it is make a call to populate drr_info. 45185f4bc0cSAlvin Lee * 45285f4bc0cSAlvin Lee * @param [in] dc: current dc state 45385f4bc0cSAlvin Lee * @param [in] context: new dc state 45485f4bc0cSAlvin Lee * @param [in] cmd: DMUB cmd to be populated with SubVP info 45585f4bc0cSAlvin Lee * @param [in] vblank_pipe: pipe_ctx for the VBLANK pipe 45685f4bc0cSAlvin Lee * @param [in] cmd_pipe_index: index for the pipe array in DMCUB SubVP cmd 45785f4bc0cSAlvin Lee * 45885f4bc0cSAlvin Lee * @return: void 45985f4bc0cSAlvin Lee * 46085f4bc0cSAlvin Lee * *********************************************************************************************** 46185f4bc0cSAlvin Lee */ 46285f4bc0cSAlvin Lee static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, 46385f4bc0cSAlvin Lee struct dc_state *context, 46485f4bc0cSAlvin Lee union dmub_rb_cmd *cmd, 46585f4bc0cSAlvin Lee struct pipe_ctx *vblank_pipe, 46685f4bc0cSAlvin Lee uint8_t cmd_pipe_index) 46785f4bc0cSAlvin Lee { 46885f4bc0cSAlvin Lee uint32_t i; 46985f4bc0cSAlvin Lee struct pipe_ctx *pipe = NULL; 47085f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 47185f4bc0cSAlvin Lee &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 47285f4bc0cSAlvin Lee 47385f4bc0cSAlvin Lee // Find the SubVP pipe 47485f4bc0cSAlvin Lee for (i = 0; i < dc->res_pool->pipe_count; i++) { 47585f4bc0cSAlvin Lee pipe = &context->res_ctx.pipe_ctx[i]; 47685f4bc0cSAlvin Lee 47785f4bc0cSAlvin Lee // We check for master pipe, but it shouldn't matter since we only need 47885f4bc0cSAlvin Lee // the pipe for timing info (stream should be same for any pipe splits) 47985f4bc0cSAlvin Lee if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) 48085f4bc0cSAlvin Lee continue; 48185f4bc0cSAlvin Lee 48285f4bc0cSAlvin Lee // Find the SubVP pipe 48385f4bc0cSAlvin Lee if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) 48485f4bc0cSAlvin Lee break; 48585f4bc0cSAlvin Lee } 48685f4bc0cSAlvin Lee 48785f4bc0cSAlvin Lee pipe_data->mode = VBLANK; 48885f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; 48985f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - 49085f4bc0cSAlvin Lee vblank_pipe->stream->timing.v_front_porch; 49185f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; 49285f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; 49385f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; 49485f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; 49585f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_end = 49685f4bc0cSAlvin Lee vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; 49785f4bc0cSAlvin Lee 49885f4bc0cSAlvin Lee if (vblank_pipe->stream->ignore_msa_timing_param) 49985f4bc0cSAlvin Lee populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data); 50085f4bc0cSAlvin Lee } 50185f4bc0cSAlvin Lee 50285f4bc0cSAlvin Lee /** 50385f4bc0cSAlvin Lee * *********************************************************************************************** 50485f4bc0cSAlvin Lee * update_subvp_prefetch_end_to_mall_start: Helper for SubVP + SubVP case 50585f4bc0cSAlvin Lee * 50685f4bc0cSAlvin Lee * For SubVP + SubVP, we use a single vertical interrupt to start the microschedule for both 50785f4bc0cSAlvin Lee * SubVP pipes. In order for this to work correctly, the MALL REGION of both SubVP pipes must 50885f4bc0cSAlvin Lee * start at the same time. This function lengthens the prefetch end to mall start delay of the 50985f4bc0cSAlvin Lee * SubVP pipe that has the shorter prefetch so that both MALL REGION's will start at the same time. 51085f4bc0cSAlvin Lee * 51185f4bc0cSAlvin Lee * @param [in] dc: current dc state 51285f4bc0cSAlvin Lee * @param [in] context: new dc state 51385f4bc0cSAlvin Lee * @param [in] cmd: DMUB cmd to be populated with SubVP info 51485f4bc0cSAlvin Lee * @param [in] subvp_pipes: Array of SubVP pipes (should always be length 2) 51585f4bc0cSAlvin Lee * 51685f4bc0cSAlvin Lee * @return: void 51785f4bc0cSAlvin Lee * 51885f4bc0cSAlvin Lee * *********************************************************************************************** 51985f4bc0cSAlvin Lee */ 52085f4bc0cSAlvin Lee static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, 52185f4bc0cSAlvin Lee struct dc_state *context, 52285f4bc0cSAlvin Lee union dmub_rb_cmd *cmd, 52385f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipes[]) 52485f4bc0cSAlvin Lee { 52585f4bc0cSAlvin Lee uint32_t subvp0_prefetch_us = 0; 52685f4bc0cSAlvin Lee uint32_t subvp1_prefetch_us = 0; 52785f4bc0cSAlvin Lee uint32_t prefetch_delta_us = 0; 52885f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing; 52985f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing; 53085f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL; 53185f4bc0cSAlvin Lee 53285f4bc0cSAlvin Lee subvp0_prefetch_us = (phantom_timing0->v_total - phantom_timing0->v_front_porch) * phantom_timing0->h_total / 53385f4bc0cSAlvin Lee (double)(phantom_timing0->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us; 53485f4bc0cSAlvin Lee subvp1_prefetch_us = (phantom_timing1->v_total - phantom_timing1->v_front_porch) * phantom_timing1->h_total / 53585f4bc0cSAlvin Lee (double)(phantom_timing1->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us; 53685f4bc0cSAlvin Lee 53785f4bc0cSAlvin Lee // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) 53885f4bc0cSAlvin Lee // should increase it's prefetch time to match the other 53985f4bc0cSAlvin Lee if (subvp0_prefetch_us > subvp1_prefetch_us) { 54085f4bc0cSAlvin Lee pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; 54185f4bc0cSAlvin Lee prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; 54285f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 54385f4bc0cSAlvin Lee (((double)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) / 1000000) * 54485f4bc0cSAlvin Lee (phantom_timing1->pix_clk_100hz * 100) + phantom_timing1->h_total - 1) / 54585f4bc0cSAlvin Lee (double)phantom_timing1->h_total; 54685f4bc0cSAlvin Lee } else if (subvp1_prefetch_us > subvp0_prefetch_us) { 54785f4bc0cSAlvin Lee pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; 54885f4bc0cSAlvin Lee prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; 54985f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 55085f4bc0cSAlvin Lee (((double)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) / 1000000) * 55185f4bc0cSAlvin Lee (phantom_timing0->pix_clk_100hz * 100) + phantom_timing0->h_total - 1) / 55285f4bc0cSAlvin Lee (double)phantom_timing0->h_total; 55385f4bc0cSAlvin Lee } 55485f4bc0cSAlvin Lee } 55585f4bc0cSAlvin Lee 55685f4bc0cSAlvin Lee /** 55785f4bc0cSAlvin Lee * *************************************************************************************** 55885f4bc0cSAlvin Lee * setup_subvp_dmub_command: Helper to populate the SubVP pipe info for the DMUB subvp command 55985f4bc0cSAlvin Lee * 56085f4bc0cSAlvin Lee * Populate the DMCUB SubVP command with SubVP pipe info. All the information required to 56185f4bc0cSAlvin Lee * calculate the microschedule for the SubVP pipe is stored in the pipe_data of the DMCUB 56285f4bc0cSAlvin Lee * SubVP command. 56385f4bc0cSAlvin Lee * 56485f4bc0cSAlvin Lee * @param [in] dc: current dc state 56585f4bc0cSAlvin Lee * @param [in] context: new dc state 56685f4bc0cSAlvin Lee * @param [in] cmd: DMUB cmd to be populated with SubVP info 56785f4bc0cSAlvin Lee * @param [in] subvp_pipe: pipe_ctx for the SubVP pipe 56885f4bc0cSAlvin Lee * @param [in] cmd_pipe_index: index for the pipe array in DMCUB SubVP cmd 56985f4bc0cSAlvin Lee * 57085f4bc0cSAlvin Lee * @return: void 57185f4bc0cSAlvin Lee * 57285f4bc0cSAlvin Lee * *************************************************************************************** 57385f4bc0cSAlvin Lee */ 57485f4bc0cSAlvin Lee static void populate_subvp_cmd_pipe_info(struct dc *dc, 57585f4bc0cSAlvin Lee struct dc_state *context, 57685f4bc0cSAlvin Lee union dmub_rb_cmd *cmd, 57785f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipe, 57885f4bc0cSAlvin Lee uint8_t cmd_pipe_index) 57985f4bc0cSAlvin Lee { 58085f4bc0cSAlvin Lee uint32_t j; 58185f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 58285f4bc0cSAlvin Lee &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 58385f4bc0cSAlvin Lee struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 58485f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 58585f4bc0cSAlvin Lee 58685f4bc0cSAlvin Lee pipe_data->mode = SUBVP; 58785f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; 58885f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; 58985f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; 59085f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.main_vblank_start = 59185f4bc0cSAlvin Lee main_timing->v_total - main_timing->v_front_porch; 59285f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.main_vblank_end = 59385f4bc0cSAlvin Lee main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; 59485f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; 59585f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->pipe_idx; 59685f4bc0cSAlvin Lee 59785f4bc0cSAlvin Lee // Prefetch lines is equal to VACTIVE + BP + VSYNC 59885f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_lines = 59985f4bc0cSAlvin Lee phantom_timing->v_total - phantom_timing->v_front_porch; 60085f4bc0cSAlvin Lee 60185f4bc0cSAlvin Lee // Round up 60285f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 60385f4bc0cSAlvin Lee (((double)dc->caps.subvp_prefetch_end_to_mall_start_us / 1000000) * 60485f4bc0cSAlvin Lee (phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1) / 60585f4bc0cSAlvin Lee (double)phantom_timing->h_total; 60685f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.processing_delay_lines = 60785f4bc0cSAlvin Lee (((double)dc->caps.subvp_fw_processing_delay_us / 1000000) * 60885f4bc0cSAlvin Lee (phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1) / 60985f4bc0cSAlvin Lee (double)phantom_timing->h_total; 61085f4bc0cSAlvin Lee // Find phantom pipe index based on phantom stream 61185f4bc0cSAlvin Lee for (j = 0; j < dc->res_pool->pipe_count; j++) { 61285f4bc0cSAlvin Lee struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; 61385f4bc0cSAlvin Lee 61485f4bc0cSAlvin Lee if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) { 61585f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->pipe_idx; 61685f4bc0cSAlvin Lee break; 61785f4bc0cSAlvin Lee } 61885f4bc0cSAlvin Lee } 61985f4bc0cSAlvin Lee } 62085f4bc0cSAlvin Lee 62185f4bc0cSAlvin Lee /** 62285f4bc0cSAlvin Lee * *************************************************************************************** 62385f4bc0cSAlvin Lee * dc_dmub_setup_subvp_dmub_command: Populate the DMCUB SubVP command 62485f4bc0cSAlvin Lee * 62585f4bc0cSAlvin Lee * This function loops through each pipe and populates the DMUB 62685f4bc0cSAlvin Lee * SubVP CMD info based on the pipe (e.g. SubVP, VBLANK). 62785f4bc0cSAlvin Lee * 62885f4bc0cSAlvin Lee * @param [in] dc: current dc state 62985f4bc0cSAlvin Lee * @param [in] context: new dc state 63085f4bc0cSAlvin Lee * @param [in] cmd: DMUB cmd to be populated with SubVP info 63185f4bc0cSAlvin Lee * 63285f4bc0cSAlvin Lee * @return: void 63385f4bc0cSAlvin Lee * 63485f4bc0cSAlvin Lee * *************************************************************************************** 63585f4bc0cSAlvin Lee */ 63685f4bc0cSAlvin Lee void dc_dmub_setup_subvp_dmub_command(struct dc *dc, 63785f4bc0cSAlvin Lee struct dc_state *context, 63885f4bc0cSAlvin Lee bool enable) 63985f4bc0cSAlvin Lee { 64085f4bc0cSAlvin Lee uint8_t cmd_pipe_index = 0; 64185f4bc0cSAlvin Lee uint32_t i, pipe_idx; 64285f4bc0cSAlvin Lee uint8_t subvp_count = 0; 64385f4bc0cSAlvin Lee union dmub_rb_cmd cmd; 64485f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipes[2]; 64585f4bc0cSAlvin Lee uint32_t wm_val_refclk = 0; 64685f4bc0cSAlvin Lee 64785f4bc0cSAlvin Lee memset(&cmd, 0, sizeof(cmd)); 64885f4bc0cSAlvin Lee // FW command for SUBVP 64985f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 65085f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD; 65185f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.payload_bytes = 65285f4bc0cSAlvin Lee sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header); 65385f4bc0cSAlvin Lee 65485f4bc0cSAlvin Lee for (i = 0; i < dc->res_pool->pipe_count; i++) { 65585f4bc0cSAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 65685f4bc0cSAlvin Lee 65785f4bc0cSAlvin Lee if (!pipe->stream) 65885f4bc0cSAlvin Lee continue; 65985f4bc0cSAlvin Lee 66085f4bc0cSAlvin Lee if (pipe->plane_state && !pipe->top_pipe && 66185f4bc0cSAlvin Lee pipe->stream->mall_stream_config.type == SUBVP_MAIN) 66285f4bc0cSAlvin Lee subvp_pipes[subvp_count++] = pipe; 66385f4bc0cSAlvin Lee } 66485f4bc0cSAlvin Lee 66585f4bc0cSAlvin Lee if (enable) { 66685f4bc0cSAlvin Lee // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd 66785f4bc0cSAlvin Lee for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 66885f4bc0cSAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 66985f4bc0cSAlvin Lee 67085f4bc0cSAlvin Lee if (!pipe->stream) 67185f4bc0cSAlvin Lee continue; 67285f4bc0cSAlvin Lee 67385f4bc0cSAlvin Lee if (pipe->plane_state && pipe->stream->mall_stream_config.paired_stream && 67485f4bc0cSAlvin Lee pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 67585f4bc0cSAlvin Lee populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 67685f4bc0cSAlvin Lee } else if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_NONE) { 67785f4bc0cSAlvin Lee // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where 67885f4bc0cSAlvin Lee // we run through DML without calculating "natural" P-state support 67985f4bc0cSAlvin Lee populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 68085f4bc0cSAlvin Lee 68185f4bc0cSAlvin Lee } 68285f4bc0cSAlvin Lee pipe_idx++; 68385f4bc0cSAlvin Lee } 68485f4bc0cSAlvin Lee if (subvp_count == 2) { 68585f4bc0cSAlvin Lee update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); 68685f4bc0cSAlvin Lee } 68785f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 68885f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; 68985f4bc0cSAlvin Lee 69085f4bc0cSAlvin Lee // Store the original watermark value for this SubVP config so we can lower it when the 69185f4bc0cSAlvin Lee // MCLK switch starts 69285f4bc0cSAlvin Lee wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * 69385f4bc0cSAlvin Lee dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 / 1000; 69485f4bc0cSAlvin Lee 69585f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; 69685f4bc0cSAlvin Lee } 69785f4bc0cSAlvin Lee dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 69885f4bc0cSAlvin Lee dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 69985f4bc0cSAlvin Lee dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 70085f4bc0cSAlvin Lee } 70185f4bc0cSAlvin Lee 7022631ac1aSAshley Thomas bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) 7032631ac1aSAshley Thomas { 7042631ac1aSAshley Thomas if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) 7052631ac1aSAshley Thomas return false; 7062631ac1aSAshley Thomas return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data); 7072631ac1aSAshley Thomas } 7082631ac1aSAshley Thomas 7092631ac1aSAshley Thomas void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 7102631ac1aSAshley Thomas { 7112631ac1aSAshley Thomas struct dmub_diagnostic_data diag_data = {0}; 7122631ac1aSAshley Thomas 7132631ac1aSAshley Thomas if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 7142631ac1aSAshley Thomas DC_LOG_ERROR("%s: invalid parameters.", __func__); 7152631ac1aSAshley Thomas return; 7162631ac1aSAshley Thomas } 7172631ac1aSAshley Thomas 7182631ac1aSAshley Thomas if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) { 7192631ac1aSAshley Thomas DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); 7202631ac1aSAshley Thomas return; 7212631ac1aSAshley Thomas } 7222631ac1aSAshley Thomas 7232631ac1aSAshley Thomas DC_LOG_DEBUG( 7242631ac1aSAshley Thomas "DMCUB STATE\n" 7252631ac1aSAshley Thomas " dmcub_version : %08x\n" 7262631ac1aSAshley Thomas " scratch [0] : %08x\n" 7272631ac1aSAshley Thomas " scratch [1] : %08x\n" 7282631ac1aSAshley Thomas " scratch [2] : %08x\n" 7292631ac1aSAshley Thomas " scratch [3] : %08x\n" 7302631ac1aSAshley Thomas " scratch [4] : %08x\n" 7312631ac1aSAshley Thomas " scratch [5] : %08x\n" 7322631ac1aSAshley Thomas " scratch [6] : %08x\n" 7332631ac1aSAshley Thomas " scratch [7] : %08x\n" 7342631ac1aSAshley Thomas " scratch [8] : %08x\n" 7352631ac1aSAshley Thomas " scratch [9] : %08x\n" 7362631ac1aSAshley Thomas " scratch [10] : %08x\n" 7372631ac1aSAshley Thomas " scratch [11] : %08x\n" 7382631ac1aSAshley Thomas " scratch [12] : %08x\n" 7392631ac1aSAshley Thomas " scratch [13] : %08x\n" 7402631ac1aSAshley Thomas " scratch [14] : %08x\n" 7412631ac1aSAshley Thomas " scratch [15] : %08x\n" 7422631ac1aSAshley Thomas " pc : %08x\n" 7432631ac1aSAshley Thomas " unk_fault_addr : %08x\n" 7442631ac1aSAshley Thomas " inst_fault_addr : %08x\n" 7452631ac1aSAshley Thomas " data_fault_addr : %08x\n" 7462631ac1aSAshley Thomas " inbox1_rptr : %08x\n" 7472631ac1aSAshley Thomas " inbox1_wptr : %08x\n" 7482631ac1aSAshley Thomas " inbox1_size : %08x\n" 7492631ac1aSAshley Thomas " inbox0_rptr : %08x\n" 7502631ac1aSAshley Thomas " inbox0_wptr : %08x\n" 7512631ac1aSAshley Thomas " inbox0_size : %08x\n" 7522631ac1aSAshley Thomas " is_enabled : %d\n" 7532631ac1aSAshley Thomas " is_soft_reset : %d\n" 7542631ac1aSAshley Thomas " is_secure_reset : %d\n" 7552631ac1aSAshley Thomas " is_traceport_en : %d\n" 7562631ac1aSAshley Thomas " is_cw0_en : %d\n" 7572631ac1aSAshley Thomas " is_cw6_en : %d\n", 7582631ac1aSAshley Thomas diag_data.dmcub_version, 7592631ac1aSAshley Thomas diag_data.scratch[0], 7602631ac1aSAshley Thomas diag_data.scratch[1], 7612631ac1aSAshley Thomas diag_data.scratch[2], 7622631ac1aSAshley Thomas diag_data.scratch[3], 7632631ac1aSAshley Thomas diag_data.scratch[4], 7642631ac1aSAshley Thomas diag_data.scratch[5], 7652631ac1aSAshley Thomas diag_data.scratch[6], 7662631ac1aSAshley Thomas diag_data.scratch[7], 7672631ac1aSAshley Thomas diag_data.scratch[8], 7682631ac1aSAshley Thomas diag_data.scratch[9], 7692631ac1aSAshley Thomas diag_data.scratch[10], 7702631ac1aSAshley Thomas diag_data.scratch[11], 7712631ac1aSAshley Thomas diag_data.scratch[12], 7722631ac1aSAshley Thomas diag_data.scratch[13], 7732631ac1aSAshley Thomas diag_data.scratch[14], 7742631ac1aSAshley Thomas diag_data.scratch[15], 7752631ac1aSAshley Thomas diag_data.pc, 7762631ac1aSAshley Thomas diag_data.undefined_address_fault_addr, 7772631ac1aSAshley Thomas diag_data.inst_fetch_fault_addr, 7782631ac1aSAshley Thomas diag_data.data_write_fault_addr, 7792631ac1aSAshley Thomas diag_data.inbox1_rptr, 7802631ac1aSAshley Thomas diag_data.inbox1_wptr, 7812631ac1aSAshley Thomas diag_data.inbox1_size, 7822631ac1aSAshley Thomas diag_data.inbox0_rptr, 7832631ac1aSAshley Thomas diag_data.inbox0_wptr, 7842631ac1aSAshley Thomas diag_data.inbox0_size, 7852631ac1aSAshley Thomas diag_data.is_dmcub_enabled, 7862631ac1aSAshley Thomas diag_data.is_dmcub_soft_reset, 7872631ac1aSAshley Thomas diag_data.is_dmcub_secure_reset, 7882631ac1aSAshley Thomas diag_data.is_traceport_en, 7892631ac1aSAshley Thomas diag_data.is_cw0_enabled, 7902631ac1aSAshley Thomas diag_data.is_cw6_enabled); 7912631ac1aSAshley Thomas } 792