13a1627b0SNicholas Kazlauskas /*
23a1627b0SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc.
33a1627b0SNicholas Kazlauskas *
43a1627b0SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a
53a1627b0SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"),
63a1627b0SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation
73a1627b0SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense,
83a1627b0SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the
93a1627b0SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions:
103a1627b0SNicholas Kazlauskas *
113a1627b0SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in
123a1627b0SNicholas Kazlauskas * all copies or substantial portions of the Software.
133a1627b0SNicholas Kazlauskas *
143a1627b0SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
153a1627b0SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
163a1627b0SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
173a1627b0SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
183a1627b0SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
193a1627b0SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
203a1627b0SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE.
213a1627b0SNicholas Kazlauskas *
223a1627b0SNicholas Kazlauskas * Authors: AMD
233a1627b0SNicholas Kazlauskas *
243a1627b0SNicholas Kazlauskas */
253a1627b0SNicholas Kazlauskas
263a1627b0SNicholas Kazlauskas #include "dc.h"
273a1627b0SNicholas Kazlauskas #include "dc_dmub_srv.h"
28cdca3f21SAnthony Koo #include "../dmub/dmub_srv.h"
2970732504SYongqiang Sun #include "dm_helpers.h"
30c2fbe663SFelipe Clark #include "dc_hw_types.h"
31c2fbe663SFelipe Clark #include "core_types.h"
32fbe43dcdSAlvin Lee #include "../basics/conversion.h"
33b73353f7SMax Tseng #include "cursor_reg_cache.h"
34*53f32880SWenjing Liu #include "resource.h"
353a1627b0SNicholas Kazlauskas
36ecdfc5c9SNicholas Kazlauskas #define CTX dc_dmub_srv->ctx
37ecdfc5c9SNicholas Kazlauskas #define DC_LOGGER CTX->logger
38ecdfc5c9SNicholas Kazlauskas
dc_dmub_srv_construct(struct dc_dmub_srv * dc_srv,struct dc * dc,struct dmub_srv * dmub)393a1627b0SNicholas Kazlauskas static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,
403a1627b0SNicholas Kazlauskas struct dmub_srv *dmub)
413a1627b0SNicholas Kazlauskas {
423a1627b0SNicholas Kazlauskas dc_srv->dmub = dmub;
433a1627b0SNicholas Kazlauskas dc_srv->ctx = dc->ctx;
443a1627b0SNicholas Kazlauskas }
453a1627b0SNicholas Kazlauskas
dc_dmub_srv_create(struct dc * dc,struct dmub_srv * dmub)463a1627b0SNicholas Kazlauskas struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)
473a1627b0SNicholas Kazlauskas {
483a1627b0SNicholas Kazlauskas struct dc_dmub_srv *dc_srv =
493a1627b0SNicholas Kazlauskas kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL);
503a1627b0SNicholas Kazlauskas
513a1627b0SNicholas Kazlauskas if (dc_srv == NULL) {
523a1627b0SNicholas Kazlauskas BREAK_TO_DEBUGGER();
533a1627b0SNicholas Kazlauskas return NULL;
543a1627b0SNicholas Kazlauskas }
553a1627b0SNicholas Kazlauskas
563a1627b0SNicholas Kazlauskas dc_dmub_srv_construct(dc_srv, dc, dmub);
573a1627b0SNicholas Kazlauskas
583a1627b0SNicholas Kazlauskas return dc_srv;
593a1627b0SNicholas Kazlauskas }
603a1627b0SNicholas Kazlauskas
dc_dmub_srv_destroy(struct dc_dmub_srv ** dmub_srv)613a1627b0SNicholas Kazlauskas void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)
623a1627b0SNicholas Kazlauskas {
633a1627b0SNicholas Kazlauskas if (*dmub_srv) {
643a1627b0SNicholas Kazlauskas kfree(*dmub_srv);
653a1627b0SNicholas Kazlauskas *dmub_srv = NULL;
663a1627b0SNicholas Kazlauskas }
673a1627b0SNicholas Kazlauskas }
683a1627b0SNicholas Kazlauskas
dc_dmub_srv_wait_idle(struct dc_dmub_srv * dc_dmub_srv)693a1627b0SNicholas Kazlauskas void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
703a1627b0SNicholas Kazlauskas {
713a1627b0SNicholas Kazlauskas struct dmub_srv *dmub = dc_dmub_srv->dmub;
723a1627b0SNicholas Kazlauskas struct dc_context *dc_ctx = dc_dmub_srv->ctx;
733a1627b0SNicholas Kazlauskas enum dmub_status status;
743a1627b0SNicholas Kazlauskas
753a1627b0SNicholas Kazlauskas status = dmub_srv_wait_for_idle(dmub, 100000);
762631ac1aSAshley Thomas if (status != DMUB_STATUS_OK) {
773a1627b0SNicholas Kazlauskas DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
782631ac1aSAshley Thomas dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
792631ac1aSAshley Thomas }
803a1627b0SNicholas Kazlauskas }
813a1627b0SNicholas Kazlauskas
dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv * dmub_srv)82d493a024SAlvin Lee void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv)
83d493a024SAlvin Lee {
84d493a024SAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub;
85d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx;
86d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK;
87d493a024SAlvin Lee
88d493a024SAlvin Lee status = dmub_srv_clear_inbox0_ack(dmub);
89d493a024SAlvin Lee if (status != DMUB_STATUS_OK) {
90d493a024SAlvin Lee DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status);
91d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv);
92d493a024SAlvin Lee }
93d493a024SAlvin Lee }
94d493a024SAlvin Lee
dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv * dmub_srv)95d493a024SAlvin Lee void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv)
96d493a024SAlvin Lee {
97d493a024SAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub;
98d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx;
99d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK;
100d493a024SAlvin Lee
101d493a024SAlvin Lee status = dmub_srv_wait_for_inbox0_ack(dmub, 100000);
102d493a024SAlvin Lee if (status != DMUB_STATUS_OK) {
103d493a024SAlvin Lee DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n");
104d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv);
105d493a024SAlvin Lee }
106d493a024SAlvin Lee }
107d493a024SAlvin Lee
dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv * dmub_srv,union dmub_inbox0_data_register data)108f2973d2aSAlvin Lee void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
109f2973d2aSAlvin Lee union dmub_inbox0_data_register data)
110f2973d2aSAlvin Lee {
111f2973d2aSAlvin Lee struct dmub_srv *dmub = dmub_srv->dmub;
112d493a024SAlvin Lee struct dc_context *dc_ctx = dmub_srv->ctx;
113d493a024SAlvin Lee enum dmub_status status = DMUB_STATUS_OK;
114d493a024SAlvin Lee
115d493a024SAlvin Lee status = dmub_srv_send_inbox0_cmd(dmub, data);
116d493a024SAlvin Lee if (status != DMUB_STATUS_OK) {
117d493a024SAlvin Lee DC_ERROR("Error sending INBOX0 cmd\n");
118d493a024SAlvin Lee dc_dmub_srv_log_diagnostic_data(dmub_srv);
119d493a024SAlvin Lee }
120f2973d2aSAlvin Lee }
121f2973d2aSAlvin Lee
dc_dmub_srv_cmd_run(struct dc_dmub_srv * dc_dmub_srv,union dmub_rb_cmd * cmd,enum dm_dmub_wait_type wait_type)122e97cc04fSJosip Pavic bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
123ecdfc5c9SNicholas Kazlauskas {
124e97cc04fSJosip Pavic return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type);
125e97cc04fSJosip Pavic }
126e97cc04fSJosip Pavic
dc_dmub_srv_cmd_run_list(struct dc_dmub_srv * dc_dmub_srv,unsigned int count,union dmub_rb_cmd * cmd_list,enum dm_dmub_wait_type wait_type)127e97cc04fSJosip Pavic bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type)
128e97cc04fSJosip Pavic {
12944407010SHarshit Mogalapalli struct dc_context *dc_ctx;
130ecdfc5c9SNicholas Kazlauskas struct dmub_srv *dmub;
131ecdfc5c9SNicholas Kazlauskas enum dmub_status status;
132e97cc04fSJosip Pavic int i;
133ecdfc5c9SNicholas Kazlauskas
134ecdfc5c9SNicholas Kazlauskas if (!dc_dmub_srv || !dc_dmub_srv->dmub)
135ecdfc5c9SNicholas Kazlauskas return false;
136ecdfc5c9SNicholas Kazlauskas
13744407010SHarshit Mogalapalli dc_ctx = dc_dmub_srv->ctx;
138ecdfc5c9SNicholas Kazlauskas dmub = dc_dmub_srv->dmub;
139ecdfc5c9SNicholas Kazlauskas
140e97cc04fSJosip Pavic for (i = 0 ; i < count; i++) {
141e97cc04fSJosip Pavic // Queue command
142e97cc04fSJosip Pavic status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
143e97cc04fSJosip Pavic
144522b9a5dSJosip Pavic if (status == DMUB_STATUS_QUEUE_FULL) {
145522b9a5dSJosip Pavic /* Execute and wait for queue to become empty again. */
146522b9a5dSJosip Pavic dmub_srv_cmd_execute(dmub);
147522b9a5dSJosip Pavic dmub_srv_wait_for_idle(dmub, 100000);
148522b9a5dSJosip Pavic
149522b9a5dSJosip Pavic /* Requeue the command. */
150522b9a5dSJosip Pavic status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
151522b9a5dSJosip Pavic }
152522b9a5dSJosip Pavic
153e97cc04fSJosip Pavic if (status != DMUB_STATUS_OK) {
154e97cc04fSJosip Pavic DC_ERROR("Error queueing DMUB command: status=%d\n", status);
155e97cc04fSJosip Pavic dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
156e97cc04fSJosip Pavic return false;
157e97cc04fSJosip Pavic }
158e97cc04fSJosip Pavic }
159e97cc04fSJosip Pavic
160e97cc04fSJosip Pavic status = dmub_srv_cmd_execute(dmub);
161e97cc04fSJosip Pavic if (status != DMUB_STATUS_OK) {
162e97cc04fSJosip Pavic DC_ERROR("Error starting DMUB execution: status=%d\n", status);
163e97cc04fSJosip Pavic dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
164e97cc04fSJosip Pavic return false;
165e97cc04fSJosip Pavic }
166e97cc04fSJosip Pavic
167e97cc04fSJosip Pavic // Wait for DMUB to process command
168e97cc04fSJosip Pavic if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {
169e97cc04fSJosip Pavic status = dmub_srv_wait_for_idle(dmub, 100000);
170e97cc04fSJosip Pavic
171ecdfc5c9SNicholas Kazlauskas if (status != DMUB_STATUS_OK) {
172ecdfc5c9SNicholas Kazlauskas DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
173f36f2648SCruise Hung dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
174ecdfc5c9SNicholas Kazlauskas return false;
175ecdfc5c9SNicholas Kazlauskas }
176ecdfc5c9SNicholas Kazlauskas
177e97cc04fSJosip Pavic // Copy data back from ring buffer into command
178e97cc04fSJosip Pavic if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
179e97cc04fSJosip Pavic dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list);
180e97cc04fSJosip Pavic }
181e97cc04fSJosip Pavic
182ecdfc5c9SNicholas Kazlauskas return true;
183ecdfc5c9SNicholas Kazlauskas }
184ecdfc5c9SNicholas Kazlauskas
dc_dmub_srv_optimized_init_done(struct dc_dmub_srv * dc_dmub_srv)185499e4b1cSEric Yang bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
1863a1627b0SNicholas Kazlauskas {
187499e4b1cSEric Yang struct dmub_srv *dmub;
188b94f1cc9STom Rix struct dc_context *dc_ctx;
189b94f1cc9STom Rix union dmub_fw_boot_status boot_status;
190b94f1cc9STom Rix enum dmub_status status;
1913a1627b0SNicholas Kazlauskas
192499e4b1cSEric Yang if (!dc_dmub_srv || !dc_dmub_srv->dmub)
193499e4b1cSEric Yang return false;
194a6e4da40SNicholas Kazlauskas
195499e4b1cSEric Yang dmub = dc_dmub_srv->dmub;
196b94f1cc9STom Rix dc_ctx = dc_dmub_srv->ctx;
197a6e4da40SNicholas Kazlauskas
198b94f1cc9STom Rix status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
199b94f1cc9STom Rix if (status != DMUB_STATUS_OK) {
200b94f1cc9STom Rix DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
201b94f1cc9STom Rix return false;
202b94f1cc9STom Rix }
203b94f1cc9STom Rix
204b94f1cc9STom Rix return boot_status.bits.optimized_init_done;
2053a1627b0SNicholas Kazlauskas }
2060825d965SEric Yang
dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv * dc_dmub_srv,unsigned int stream_mask)2070825d965SEric Yang bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
2080825d965SEric Yang unsigned int stream_mask)
2090825d965SEric Yang {
2100825d965SEric Yang struct dmub_srv *dmub;
2110825d965SEric Yang const uint32_t timeout = 30;
2120825d965SEric Yang
2130825d965SEric Yang if (!dc_dmub_srv || !dc_dmub_srv->dmub)
2140825d965SEric Yang return false;
2150825d965SEric Yang
2160825d965SEric Yang dmub = dc_dmub_srv->dmub;
2170825d965SEric Yang
2180825d965SEric Yang return dmub_srv_send_gpint_command(
2190825d965SEric Yang dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
2200825d965SEric Yang stream_mask, timeout) == DMUB_STATUS_OK;
2210825d965SEric Yang }
2228fe44c08SAlex Deucher
dc_dmub_srv_is_restore_required(struct dc_dmub_srv * dc_dmub_srv)223b04cb192SNicholas Kazlauskas bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
224b04cb192SNicholas Kazlauskas {
225b04cb192SNicholas Kazlauskas struct dmub_srv *dmub;
226b04cb192SNicholas Kazlauskas struct dc_context *dc_ctx;
227b04cb192SNicholas Kazlauskas union dmub_fw_boot_status boot_status;
228b04cb192SNicholas Kazlauskas enum dmub_status status;
229b04cb192SNicholas Kazlauskas
230b04cb192SNicholas Kazlauskas if (!dc_dmub_srv || !dc_dmub_srv->dmub)
231b04cb192SNicholas Kazlauskas return false;
232b04cb192SNicholas Kazlauskas
233b04cb192SNicholas Kazlauskas dmub = dc_dmub_srv->dmub;
234b04cb192SNicholas Kazlauskas dc_ctx = dc_dmub_srv->ctx;
235b04cb192SNicholas Kazlauskas
236b04cb192SNicholas Kazlauskas status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
237b04cb192SNicholas Kazlauskas if (status != DMUB_STATUS_OK) {
238b04cb192SNicholas Kazlauskas DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
239b04cb192SNicholas Kazlauskas return false;
240b04cb192SNicholas Kazlauskas }
241b04cb192SNicholas Kazlauskas
242b04cb192SNicholas Kazlauskas return boot_status.bits.restore_required;
243b04cb192SNicholas Kazlauskas }
24470732504SYongqiang Sun
dc_dmub_srv_get_dmub_outbox0_msg(const struct dc * dc,struct dmcub_trace_buf_entry * entry)2456804287bSYongqiang Sun bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
24670732504SYongqiang Sun {
24770732504SYongqiang Sun struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;
2486804287bSYongqiang Sun return dmub_srv_get_outbox0_msg(dmub, entry);
24970732504SYongqiang Sun }
25070732504SYongqiang Sun
dc_dmub_trace_event_control(struct dc * dc,bool enable)25170732504SYongqiang Sun void dc_dmub_trace_event_control(struct dc *dc, bool enable)
25270732504SYongqiang Sun {
25381927e28SJude Shih dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
25470732504SYongqiang Sun }
2552631ac1aSAshley Thomas
dc_dmub_srv_drr_update_cmd(struct dc * dc,uint32_t tg_inst,uint32_t vtotal_min,uint32_t vtotal_max)25600fa7f03SRodrigo Siqueira void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)
25700fa7f03SRodrigo Siqueira {
25800fa7f03SRodrigo Siqueira union dmub_rb_cmd cmd = { 0 };
25900fa7f03SRodrigo Siqueira
26000fa7f03SRodrigo Siqueira cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
26100fa7f03SRodrigo Siqueira cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE;
26200fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max;
26300fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min;
26400fa7f03SRodrigo Siqueira cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
26500fa7f03SRodrigo Siqueira
26600fa7f03SRodrigo Siqueira cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
26700fa7f03SRodrigo Siqueira
26800fa7f03SRodrigo Siqueira // Send the command to the DMCUB.
269e97cc04fSJosip Pavic dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
27000fa7f03SRodrigo Siqueira }
27100fa7f03SRodrigo Siqueira
dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc * dc,uint32_t tg_inst)272319568d7SAlvin Lee void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
273319568d7SAlvin Lee {
274319568d7SAlvin Lee union dmub_rb_cmd cmd = { 0 };
275319568d7SAlvin Lee
276319568d7SAlvin Lee cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
2779f5171ceSAlvin Lee cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
278319568d7SAlvin Lee cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
279319568d7SAlvin Lee
280319568d7SAlvin Lee cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
281319568d7SAlvin Lee
282319568d7SAlvin Lee // Send the command to the DMCUB.
283e97cc04fSJosip Pavic dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
284319568d7SAlvin Lee }
285319568d7SAlvin Lee
dc_dmub_srv_get_pipes_for_stream(struct dc * dc,struct dc_stream_state * stream)28684900aeeSAlex Deucher static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)
28700fa7f03SRodrigo Siqueira {
28800fa7f03SRodrigo Siqueira uint8_t pipes = 0;
28900fa7f03SRodrigo Siqueira int i = 0;
29000fa7f03SRodrigo Siqueira
29100fa7f03SRodrigo Siqueira for (i = 0; i < MAX_PIPES; i++) {
29200fa7f03SRodrigo Siqueira struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
29300fa7f03SRodrigo Siqueira
29400fa7f03SRodrigo Siqueira if (pipe->stream == stream && pipe->stream_res.tg)
29500fa7f03SRodrigo Siqueira pipes = i;
29600fa7f03SRodrigo Siqueira }
29700fa7f03SRodrigo Siqueira return pipes;
29800fa7f03SRodrigo Siqueira }
29900fa7f03SRodrigo Siqueira
dc_dmub_srv_populate_fams_pipe_info(struct dc * dc,struct dc_state * context,struct pipe_ctx * head_pipe,struct dmub_cmd_fw_assisted_mclk_switch_pipe_data * fams_pipe_data)3004ed79308SAlvin Lee static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,
3014ed79308SAlvin Lee struct pipe_ctx *head_pipe,
3024ed79308SAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data)
30300fa7f03SRodrigo Siqueira {
3044ed79308SAlvin Lee int j;
305b0d58d11SAlvin Lee int pipe_idx = 0;
30600fa7f03SRodrigo Siqueira
307b0d58d11SAlvin Lee fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;
3084ed79308SAlvin Lee for (j = 0; j < dc->res_pool->pipe_count; j++) {
3094ed79308SAlvin Lee struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
31000fa7f03SRodrigo Siqueira
3114ed79308SAlvin Lee if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
312b0d58d11SAlvin Lee fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;
31300fa7f03SRodrigo Siqueira }
31400fa7f03SRodrigo Siqueira }
315b0d58d11SAlvin Lee fams_pipe_data->pipe_count = pipe_idx;
31600fa7f03SRodrigo Siqueira }
31700fa7f03SRodrigo Siqueira
dc_dmub_srv_p_state_delegate(struct dc * dc,bool should_manage_pstate,struct dc_state * context)31800fa7f03SRodrigo Siqueira bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
31900fa7f03SRodrigo Siqueira {
32000fa7f03SRodrigo Siqueira union dmub_rb_cmd cmd = { 0 };
32100fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data;
3224ed79308SAlvin Lee int i = 0, k = 0;
32300fa7f03SRodrigo Siqueira int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it.
32445a92f45Ssunliming uint8_t visual_confirm_enabled;
3250289e0edSAlvin Lee int pipe_idx = 0;
32600fa7f03SRodrigo Siqueira
32700fa7f03SRodrigo Siqueira if (dc == NULL)
32800fa7f03SRodrigo Siqueira return false;
32900fa7f03SRodrigo Siqueira
33045a92f45Ssunliming visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;
33145a92f45Ssunliming
33200fa7f03SRodrigo Siqueira // Format command.
33300fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
33400fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL;
33500fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate;
33600fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled;
33700fa7f03SRodrigo Siqueira
3380289e0edSAlvin Lee if (should_manage_pstate) {
3390289e0edSAlvin Lee for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3400289e0edSAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3410289e0edSAlvin Lee
3420289e0edSAlvin Lee if (!pipe->stream)
3430289e0edSAlvin Lee continue;
3440289e0edSAlvin Lee
3450289e0edSAlvin Lee /* If FAMS is being used to support P-State and there is a stream
3460289e0edSAlvin Lee * that does not use FAMS, we are in an FPO + VActive scenario.
3470289e0edSAlvin Lee * Assign vactive stretch margin in this case.
3480289e0edSAlvin Lee */
3490289e0edSAlvin Lee if (!pipe->stream->fpo_in_use) {
3500289e0edSAlvin Lee cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us;
3510289e0edSAlvin Lee break;
3520289e0edSAlvin Lee }
3530289e0edSAlvin Lee pipe_idx++;
3540289e0edSAlvin Lee }
3550289e0edSAlvin Lee }
3560289e0edSAlvin Lee
3574ed79308SAlvin Lee for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
3584ed79308SAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
35900fa7f03SRodrigo Siqueira
360*53f32880SWenjing Liu if (resource_is_pipe_type(pipe, OTG_MASTER) && pipe->stream->fpo_in_use) {
3614ed79308SAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3624ed79308SAlvin Lee uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;
3634ed79308SAlvin Lee
3644ed79308SAlvin Lee config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
3654ed79308SAlvin Lee config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
3664ed79308SAlvin Lee config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
3674ed79308SAlvin Lee config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
3684ed79308SAlvin Lee dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);
3694ed79308SAlvin Lee k++;
37000fa7f03SRodrigo Siqueira }
3714ed79308SAlvin Lee }
37200fa7f03SRodrigo Siqueira cmd.fw_assisted_mclk_switch.header.payload_bytes =
37300fa7f03SRodrigo Siqueira sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header);
37400fa7f03SRodrigo Siqueira
37500fa7f03SRodrigo Siqueira // Send the command to the DMCUB.
376e97cc04fSJosip Pavic dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
37700fa7f03SRodrigo Siqueira
37800fa7f03SRodrigo Siqueira return true;
37900fa7f03SRodrigo Siqueira }
38000fa7f03SRodrigo Siqueira
dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv * dc_dmub_srv)381e97cc04fSJosip Pavic void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv)
382ac2e555eSAurabindo Pillai {
383ac2e555eSAurabindo Pillai union dmub_rb_cmd cmd = { 0 };
384ac2e555eSAurabindo Pillai
385a243e38eSNicholas Kazlauskas if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
386a243e38eSNicholas Kazlauskas return;
387a243e38eSNicholas Kazlauskas
388ac2e555eSAurabindo Pillai memset(&cmd, 0, sizeof(cmd));
389ac2e555eSAurabindo Pillai
390ac2e555eSAurabindo Pillai /* Prepare fw command */
391ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS;
392ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.sub_type = 0;
393ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.ret_status = 1;
394ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);
395ac2e555eSAurabindo Pillai
396ac2e555eSAurabindo Pillai /* If command was processed, copy feature caps to dmub srv */
397e97cc04fSJosip Pavic if (dm_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
398ac2e555eSAurabindo Pillai cmd.query_feature_caps.header.ret_status == 0) {
399e97cc04fSJosip Pavic memcpy(&dc_dmub_srv->dmub->feature_caps,
400ac2e555eSAurabindo Pillai &cmd.query_feature_caps.query_feature_caps_data,
401ac2e555eSAurabindo Pillai sizeof(struct dmub_feature_caps));
402ac2e555eSAurabindo Pillai }
403ac2e555eSAurabindo Pillai }
404ac2e555eSAurabindo Pillai
dc_dmub_srv_get_visual_confirm_color_cmd(struct dc * dc,struct pipe_ctx * pipe_ctx)405b09c1fffSLeo (Hanghong) Ma void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)
406b09c1fffSLeo (Hanghong) Ma {
407b09c1fffSLeo (Hanghong) Ma union dmub_rb_cmd cmd = { 0 };
408b09c1fffSLeo (Hanghong) Ma unsigned int panel_inst = 0;
409b09c1fffSLeo (Hanghong) Ma
410b09c1fffSLeo (Hanghong) Ma dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst);
411b09c1fffSLeo (Hanghong) Ma
412b09c1fffSLeo (Hanghong) Ma memset(&cmd, 0, sizeof(cmd));
413b09c1fffSLeo (Hanghong) Ma
414b09c1fffSLeo (Hanghong) Ma // Prepare fw command
415b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
416b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.sub_type = 0;
417b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.ret_status = 1;
418b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
419b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
420b09c1fffSLeo (Hanghong) Ma
421b09c1fffSLeo (Hanghong) Ma // If command was processed, copy feature caps to dmub srv
422e97cc04fSJosip Pavic if (dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
423b09c1fffSLeo (Hanghong) Ma cmd.visual_confirm_color.header.ret_status == 0) {
424b09c1fffSLeo (Hanghong) Ma memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
425b09c1fffSLeo (Hanghong) Ma &cmd.visual_confirm_color.visual_confirm_color_data,
426b09c1fffSLeo (Hanghong) Ma sizeof(struct dmub_visual_confirm_color));
427b09c1fffSLeo (Hanghong) Ma }
428b09c1fffSLeo (Hanghong) Ma }
429b09c1fffSLeo (Hanghong) Ma
43085f4bc0cSAlvin Lee /**
4316be153dcSRodrigo Siqueira * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command
43285f4bc0cSAlvin Lee *
4336be153dcSRodrigo Siqueira * @dc: [in] current dc state
4346be153dcSRodrigo Siqueira * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
4356be153dcSRodrigo Siqueira * @vblank_pipe: [in] pipe_ctx for the DRR pipe
4366be153dcSRodrigo Siqueira * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info
4376be153dcSRodrigo Siqueira *
4386be153dcSRodrigo Siqueira * Populate the DMCUB SubVP command with DRR pipe info. All the information
4396be153dcSRodrigo Siqueira * required for calculating the SubVP + DRR microschedule is populated here.
44085f4bc0cSAlvin Lee *
44185f4bc0cSAlvin Lee * High level algorithm:
44285f4bc0cSAlvin Lee * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
44385f4bc0cSAlvin Lee * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule
44485f4bc0cSAlvin Lee * 3. Populate the drr_info with the min and max supported vtotal values
44585f4bc0cSAlvin Lee */
populate_subvp_cmd_drr_info(struct dc * dc,struct pipe_ctx * subvp_pipe,struct pipe_ctx * vblank_pipe,struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 * pipe_data)44685f4bc0cSAlvin Lee static void populate_subvp_cmd_drr_info(struct dc *dc,
44785f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipe,
44885f4bc0cSAlvin Lee struct pipe_ctx *vblank_pipe,
44985f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data)
45085f4bc0cSAlvin Lee {
45185f4bc0cSAlvin Lee struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
45285f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
45385f4bc0cSAlvin Lee struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
454410e7474SAlvin Lee uint16_t drr_frame_us = 0;
455410e7474SAlvin Lee uint16_t min_drr_supported_us = 0;
456410e7474SAlvin Lee uint16_t max_drr_supported_us = 0;
457410e7474SAlvin Lee uint16_t max_drr_vblank_us = 0;
458410e7474SAlvin Lee uint16_t max_drr_mallregion_us = 0;
459410e7474SAlvin Lee uint16_t mall_region_us = 0;
460410e7474SAlvin Lee uint16_t prefetch_us = 0;
461410e7474SAlvin Lee uint16_t subvp_active_us = 0;
462410e7474SAlvin Lee uint16_t drr_active_us = 0;
463410e7474SAlvin Lee uint16_t min_vtotal_supported = 0;
464410e7474SAlvin Lee uint16_t max_vtotal_supported = 0;
46585f4bc0cSAlvin Lee
46685f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;
46785f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
46885f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
46985f4bc0cSAlvin Lee
470410e7474SAlvin Lee drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000),
471410e7474SAlvin Lee (((uint64_t)drr_timing->pix_clk_100hz * 100)));
47285f4bc0cSAlvin Lee // P-State allow width and FW delays already included phantom_timing->v_addressable
473410e7474SAlvin Lee mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000),
474410e7474SAlvin Lee (((uint64_t)phantom_timing->pix_clk_100hz * 100)));
47585f4bc0cSAlvin Lee min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
476410e7474SAlvin Lee min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us),
477410e7474SAlvin Lee (((uint64_t)drr_timing->h_total * 1000000)));
47885f4bc0cSAlvin Lee
479410e7474SAlvin Lee prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000),
480410e7474SAlvin Lee (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
481410e7474SAlvin Lee subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000),
482410e7474SAlvin Lee (((uint64_t)main_timing->pix_clk_100hz * 100)));
483410e7474SAlvin Lee drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000),
484410e7474SAlvin Lee (((uint64_t)drr_timing->pix_clk_100hz * 100)));
485964d6416SAlvin Lee max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us -
486964d6416SAlvin Lee dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us;
487964d6416SAlvin Lee max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;
48885f4bc0cSAlvin Lee max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
489410e7474SAlvin Lee max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us),
490410e7474SAlvin Lee (((uint64_t)drr_timing->h_total * 1000000)));
49185f4bc0cSAlvin Lee
492964d6416SAlvin Lee /* When calculating the max vtotal supported for SubVP + DRR cases, add
493964d6416SAlvin Lee * margin due to possible rounding errors (being off by 1 line in the
494964d6416SAlvin Lee * FW calculation can incorrectly push the P-State switch to wait 1 frame
495964d6416SAlvin Lee * longer).
496964d6416SAlvin Lee */
497964d6416SAlvin Lee max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
498964d6416SAlvin Lee
49985f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
50085f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
501ae7169a9SAlvin Lee pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
50285f4bc0cSAlvin Lee }
50385f4bc0cSAlvin Lee
50485f4bc0cSAlvin Lee /**
5056be153dcSRodrigo Siqueira * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command
50685f4bc0cSAlvin Lee *
5076be153dcSRodrigo Siqueira * @dc: [in] current dc state
5086be153dcSRodrigo Siqueira * @context: [in] new dc state
5096be153dcSRodrigo Siqueira * @cmd: [in] DMUB cmd to be populated with SubVP info
5106be153dcSRodrigo Siqueira * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe
5116be153dcSRodrigo Siqueira * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
51285f4bc0cSAlvin Lee *
5136be153dcSRodrigo Siqueira * Populate the DMCUB SubVP command with VBLANK pipe info. All the information
5146be153dcSRodrigo Siqueira * required to calculate the microschedule for SubVP + VBLANK case is stored in
5156be153dcSRodrigo Siqueira * the pipe_data (subvp_data and vblank_data). Also check if the VBLANK pipe
5166be153dcSRodrigo Siqueira * is a DRR display -- if it is make a call to populate drr_info.
51785f4bc0cSAlvin Lee */
populate_subvp_cmd_vblank_pipe_info(struct dc * dc,struct dc_state * context,union dmub_rb_cmd * cmd,struct pipe_ctx * vblank_pipe,uint8_t cmd_pipe_index)51885f4bc0cSAlvin Lee static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,
51985f4bc0cSAlvin Lee struct dc_state *context,
52085f4bc0cSAlvin Lee union dmub_rb_cmd *cmd,
52185f4bc0cSAlvin Lee struct pipe_ctx *vblank_pipe,
52285f4bc0cSAlvin Lee uint8_t cmd_pipe_index)
52385f4bc0cSAlvin Lee {
52485f4bc0cSAlvin Lee uint32_t i;
52585f4bc0cSAlvin Lee struct pipe_ctx *pipe = NULL;
52685f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
52785f4bc0cSAlvin Lee &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
52885f4bc0cSAlvin Lee
52985f4bc0cSAlvin Lee // Find the SubVP pipe
53085f4bc0cSAlvin Lee for (i = 0; i < dc->res_pool->pipe_count; i++) {
53185f4bc0cSAlvin Lee pipe = &context->res_ctx.pipe_ctx[i];
53285f4bc0cSAlvin Lee
53385f4bc0cSAlvin Lee // We check for master pipe, but it shouldn't matter since we only need
53485f4bc0cSAlvin Lee // the pipe for timing info (stream should be same for any pipe splits)
535*53f32880SWenjing Liu if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
536*53f32880SWenjing Liu !resource_is_pipe_type(pipe, DPP_PIPE))
53785f4bc0cSAlvin Lee continue;
53885f4bc0cSAlvin Lee
53985f4bc0cSAlvin Lee // Find the SubVP pipe
54085f4bc0cSAlvin Lee if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
54185f4bc0cSAlvin Lee break;
54285f4bc0cSAlvin Lee }
54385f4bc0cSAlvin Lee
54485f4bc0cSAlvin Lee pipe_data->mode = VBLANK;
54585f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
54685f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
54785f4bc0cSAlvin Lee vblank_pipe->stream->timing.v_front_porch;
54885f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
54985f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;
55085f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;
55185f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;
55285f4bc0cSAlvin Lee pipe_data->pipe_config.vblank_data.vblank_end =
55385f4bc0cSAlvin Lee vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
55485f4bc0cSAlvin Lee
55585f4bc0cSAlvin Lee if (vblank_pipe->stream->ignore_msa_timing_param)
55685f4bc0cSAlvin Lee populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data);
55785f4bc0cSAlvin Lee }
55885f4bc0cSAlvin Lee
55985f4bc0cSAlvin Lee /**
5606be153dcSRodrigo Siqueira * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case
56185f4bc0cSAlvin Lee *
5626be153dcSRodrigo Siqueira * @dc: [in] current dc state
5636be153dcSRodrigo Siqueira * @context: [in] new dc state
5646be153dcSRodrigo Siqueira * @cmd: [in] DMUB cmd to be populated with SubVP info
5656be153dcSRodrigo Siqueira * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2)
56685f4bc0cSAlvin Lee *
5676be153dcSRodrigo Siqueira * For SubVP + SubVP, we use a single vertical interrupt to start the
5686be153dcSRodrigo Siqueira * microschedule for both SubVP pipes. In order for this to work correctly, the
5696be153dcSRodrigo Siqueira * MALL REGION of both SubVP pipes must start at the same time. This function
5706be153dcSRodrigo Siqueira * lengthens the prefetch end to mall start delay of the SubVP pipe that has
5716be153dcSRodrigo Siqueira * the shorter prefetch so that both MALL REGION's will start at the same time.
57285f4bc0cSAlvin Lee */
update_subvp_prefetch_end_to_mall_start(struct dc * dc,struct dc_state * context,union dmub_rb_cmd * cmd,struct pipe_ctx * subvp_pipes[])57385f4bc0cSAlvin Lee static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
57485f4bc0cSAlvin Lee struct dc_state *context,
57585f4bc0cSAlvin Lee union dmub_rb_cmd *cmd,
57685f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipes[])
57785f4bc0cSAlvin Lee {
57885f4bc0cSAlvin Lee uint32_t subvp0_prefetch_us = 0;
57985f4bc0cSAlvin Lee uint32_t subvp1_prefetch_us = 0;
58085f4bc0cSAlvin Lee uint32_t prefetch_delta_us = 0;
58185f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing;
58285f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing;
58385f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
58485f4bc0cSAlvin Lee
585410e7474SAlvin Lee subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
586410e7474SAlvin Lee (uint64_t)phantom_timing0->h_total * 1000000),
587410e7474SAlvin Lee (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
588410e7474SAlvin Lee subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
589410e7474SAlvin Lee (uint64_t)phantom_timing1->h_total * 1000000),
590410e7474SAlvin Lee (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
59185f4bc0cSAlvin Lee
59285f4bc0cSAlvin Lee // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
59385f4bc0cSAlvin Lee // should increase it's prefetch time to match the other
59485f4bc0cSAlvin Lee if (subvp0_prefetch_us > subvp1_prefetch_us) {
59585f4bc0cSAlvin Lee pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
59685f4bc0cSAlvin Lee prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
59785f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
598410e7474SAlvin Lee div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
599410e7474SAlvin Lee ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
600410e7474SAlvin Lee ((uint64_t)phantom_timing1->h_total * 1000000));
601410e7474SAlvin Lee
60285f4bc0cSAlvin Lee } else if (subvp1_prefetch_us > subvp0_prefetch_us) {
60385f4bc0cSAlvin Lee pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
60485f4bc0cSAlvin Lee prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
60585f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
606410e7474SAlvin Lee div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
607410e7474SAlvin Lee ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
608410e7474SAlvin Lee ((uint64_t)phantom_timing0->h_total * 1000000));
60985f4bc0cSAlvin Lee }
61085f4bc0cSAlvin Lee }
61185f4bc0cSAlvin Lee
61285f4bc0cSAlvin Lee /**
6130645b7a6SJiapeng Chong * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command
61485f4bc0cSAlvin Lee *
6156be153dcSRodrigo Siqueira * @dc: [in] current dc state
6166be153dcSRodrigo Siqueira * @context: [in] new dc state
6176be153dcSRodrigo Siqueira * @cmd: [in] DMUB cmd to be populated with SubVP info
6186be153dcSRodrigo Siqueira * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
6196be153dcSRodrigo Siqueira * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
62085f4bc0cSAlvin Lee *
6216be153dcSRodrigo Siqueira * Populate the DMCUB SubVP command with SubVP pipe info. All the information
6226be153dcSRodrigo Siqueira * required to calculate the microschedule for the SubVP pipe is stored in the
6236be153dcSRodrigo Siqueira * pipe_data of the DMCUB SubVP command.
62485f4bc0cSAlvin Lee */
populate_subvp_cmd_pipe_info(struct dc * dc,struct dc_state * context,union dmub_rb_cmd * cmd,struct pipe_ctx * subvp_pipe,uint8_t cmd_pipe_index)62585f4bc0cSAlvin Lee static void populate_subvp_cmd_pipe_info(struct dc *dc,
62685f4bc0cSAlvin Lee struct dc_state *context,
62785f4bc0cSAlvin Lee union dmub_rb_cmd *cmd,
62885f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipe,
62985f4bc0cSAlvin Lee uint8_t cmd_pipe_index)
63085f4bc0cSAlvin Lee {
63185f4bc0cSAlvin Lee uint32_t j;
63285f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
63385f4bc0cSAlvin Lee &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
63485f4bc0cSAlvin Lee struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
63585f4bc0cSAlvin Lee struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
6367857825bSAlvin Lee uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;
63785f4bc0cSAlvin Lee
63885f4bc0cSAlvin Lee pipe_data->mode = SUBVP;
63985f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
64085f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;
64185f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;
64285f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.main_vblank_start =
64385f4bc0cSAlvin Lee main_timing->v_total - main_timing->v_front_porch;
64485f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.main_vblank_end =
64585f4bc0cSAlvin Lee main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
64685f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
6477da2bcdaSAlvin Lee pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;
6489f5171ceSAlvin Lee pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param;
64985f4bc0cSAlvin Lee
650fbe43dcdSAlvin Lee /* Calculate the scaling factor from the src and dst height.
651fbe43dcdSAlvin Lee * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.
652fbe43dcdSAlvin Lee * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor"
6537857825bSAlvin Lee *
6547857825bSAlvin Lee * Make sure to combine stream and plane scaling together.
655fbe43dcdSAlvin Lee */
6567857825bSAlvin Lee reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height,
6577857825bSAlvin Lee &out_num_stream, &out_den_stream);
6587857825bSAlvin Lee reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,
6597857825bSAlvin Lee &out_num_plane, &out_den_plane);
6607857825bSAlvin Lee reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den);
66174f4e84dSAlvin Lee pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
66274f4e84dSAlvin Lee pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
663fbe43dcdSAlvin Lee
66485f4bc0cSAlvin Lee // Prefetch lines is equal to VACTIVE + BP + VSYNC
66585f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_lines =
66685f4bc0cSAlvin Lee phantom_timing->v_total - phantom_timing->v_front_porch;
66785f4bc0cSAlvin Lee
66885f4bc0cSAlvin Lee // Round up
66985f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
670410e7474SAlvin Lee div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
671410e7474SAlvin Lee ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
67285f4bc0cSAlvin Lee pipe_data->pipe_config.subvp_data.processing_delay_lines =
673410e7474SAlvin Lee div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
674410e7474SAlvin Lee ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
675b0d6de32SAlvin Lee
676b0d6de32SAlvin Lee if (subvp_pipe->bottom_pipe) {
677b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;
678b0d6de32SAlvin Lee } else if (subvp_pipe->next_odm_pipe) {
679b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
680b0d6de32SAlvin Lee } else {
681b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0;
682b0d6de32SAlvin Lee }
683b0d6de32SAlvin Lee
68485f4bc0cSAlvin Lee // Find phantom pipe index based on phantom stream
68585f4bc0cSAlvin Lee for (j = 0; j < dc->res_pool->pipe_count; j++) {
68685f4bc0cSAlvin Lee struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
68785f4bc0cSAlvin Lee
68885f4bc0cSAlvin Lee if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) {
6897da2bcdaSAlvin Lee pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;
690b0d6de32SAlvin Lee if (phantom_pipe->bottom_pipe) {
6917da2bcdaSAlvin Lee pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;
692b0d6de32SAlvin Lee } else if (phantom_pipe->next_odm_pipe) {
6937da2bcdaSAlvin Lee pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
694b0d6de32SAlvin Lee } else {
695b0d6de32SAlvin Lee pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0;
696b0d6de32SAlvin Lee }
69785f4bc0cSAlvin Lee break;
69885f4bc0cSAlvin Lee }
69985f4bc0cSAlvin Lee }
70085f4bc0cSAlvin Lee }
70185f4bc0cSAlvin Lee
70285f4bc0cSAlvin Lee /**
7036be153dcSRodrigo Siqueira * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command
70485f4bc0cSAlvin Lee *
7056be153dcSRodrigo Siqueira * @dc: [in] current dc state
7066be153dcSRodrigo Siqueira * @context: [in] new dc state
70701543dcfSArthur Grillo * @enable: [in] if true enables the pipes population
70885f4bc0cSAlvin Lee *
7096be153dcSRodrigo Siqueira * This function loops through each pipe and populates the DMUB SubVP CMD info
7106be153dcSRodrigo Siqueira * based on the pipe (e.g. SubVP, VBLANK).
71185f4bc0cSAlvin Lee */
dc_dmub_setup_subvp_dmub_command(struct dc * dc,struct dc_state * context,bool enable)71285f4bc0cSAlvin Lee void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
71385f4bc0cSAlvin Lee struct dc_state *context,
71485f4bc0cSAlvin Lee bool enable)
71585f4bc0cSAlvin Lee {
71685f4bc0cSAlvin Lee uint8_t cmd_pipe_index = 0;
71785f4bc0cSAlvin Lee uint32_t i, pipe_idx;
71885f4bc0cSAlvin Lee uint8_t subvp_count = 0;
71985f4bc0cSAlvin Lee union dmub_rb_cmd cmd;
72085f4bc0cSAlvin Lee struct pipe_ctx *subvp_pipes[2];
72185f4bc0cSAlvin Lee uint32_t wm_val_refclk = 0;
72285f4bc0cSAlvin Lee
72385f4bc0cSAlvin Lee memset(&cmd, 0, sizeof(cmd));
72485f4bc0cSAlvin Lee // FW command for SUBVP
72585f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
72685f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD;
72785f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.header.payload_bytes =
72885f4bc0cSAlvin Lee sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header);
72985f4bc0cSAlvin Lee
73085f4bc0cSAlvin Lee for (i = 0; i < dc->res_pool->pipe_count; i++) {
73185f4bc0cSAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
73285f4bc0cSAlvin Lee
733b0d6de32SAlvin Lee /* For SubVP pipe count, only count the top most (ODM / MPC) pipe
734b0d6de32SAlvin Lee */
735*53f32880SWenjing Liu if (resource_is_pipe_type(pipe, OTG_MASTER) &&
736*53f32880SWenjing Liu resource_is_pipe_type(pipe, DPP_PIPE) &&
73785f4bc0cSAlvin Lee pipe->stream->mall_stream_config.type == SUBVP_MAIN)
73885f4bc0cSAlvin Lee subvp_pipes[subvp_count++] = pipe;
73985f4bc0cSAlvin Lee }
74085f4bc0cSAlvin Lee
74185f4bc0cSAlvin Lee if (enable) {
74285f4bc0cSAlvin Lee // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd
74385f4bc0cSAlvin Lee for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
74485f4bc0cSAlvin Lee struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
74585f4bc0cSAlvin Lee
74685f4bc0cSAlvin Lee if (!pipe->stream)
74785f4bc0cSAlvin Lee continue;
74885f4bc0cSAlvin Lee
749b0d6de32SAlvin Lee /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe.
750b0d6de32SAlvin Lee * Any ODM or MPC splits being used in SubVP will be handled internally in
751b0d6de32SAlvin Lee * populate_subvp_cmd_pipe_info
752b0d6de32SAlvin Lee */
753*53f32880SWenjing Liu if (resource_is_pipe_type(pipe, OTG_MASTER) &&
754*53f32880SWenjing Liu resource_is_pipe_type(pipe, DPP_PIPE) &&
755*53f32880SWenjing Liu pipe->stream->mall_stream_config.paired_stream &&
75685f4bc0cSAlvin Lee pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
75785f4bc0cSAlvin Lee populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
758*53f32880SWenjing Liu } else if (resource_is_pipe_type(pipe, OTG_MASTER) &&
759*53f32880SWenjing Liu resource_is_pipe_type(pipe, DPP_PIPE) &&
760*53f32880SWenjing Liu pipe->stream->mall_stream_config.type == SUBVP_NONE) {
76185f4bc0cSAlvin Lee // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where
76285f4bc0cSAlvin Lee // we run through DML without calculating "natural" P-state support
76385f4bc0cSAlvin Lee populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
76485f4bc0cSAlvin Lee
76585f4bc0cSAlvin Lee }
76685f4bc0cSAlvin Lee pipe_idx++;
76785f4bc0cSAlvin Lee }
76885f4bc0cSAlvin Lee if (subvp_count == 2) {
76985f4bc0cSAlvin Lee update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);
77085f4bc0cSAlvin Lee }
77185f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
77285f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;
77385f4bc0cSAlvin Lee
77485f4bc0cSAlvin Lee // Store the original watermark value for this SubVP config so we can lower it when the
77585f4bc0cSAlvin Lee // MCLK switch starts
77685f4bc0cSAlvin Lee wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
77797997023SAlvin Lee (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
77885f4bc0cSAlvin Lee
77985f4bc0cSAlvin Lee cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
78085f4bc0cSAlvin Lee }
781e97cc04fSJosip Pavic
782e97cc04fSJosip Pavic dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
78385f4bc0cSAlvin Lee }
78485f4bc0cSAlvin Lee
dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv * dc_dmub_srv,struct dmub_diagnostic_data * diag_data)7852631ac1aSAshley Thomas bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
7862631ac1aSAshley Thomas {
7872631ac1aSAshley Thomas if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
7882631ac1aSAshley Thomas return false;
7892631ac1aSAshley Thomas return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data);
7902631ac1aSAshley Thomas }
7912631ac1aSAshley Thomas
dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv * dc_dmub_srv)7922631ac1aSAshley Thomas void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
7932631ac1aSAshley Thomas {
7942631ac1aSAshley Thomas struct dmub_diagnostic_data diag_data = {0};
7952631ac1aSAshley Thomas
7962631ac1aSAshley Thomas if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
7972631ac1aSAshley Thomas DC_LOG_ERROR("%s: invalid parameters.", __func__);
7982631ac1aSAshley Thomas return;
7992631ac1aSAshley Thomas }
8002631ac1aSAshley Thomas
8012631ac1aSAshley Thomas if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) {
8022631ac1aSAshley Thomas DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);
8032631ac1aSAshley Thomas return;
8042631ac1aSAshley Thomas }
8052631ac1aSAshley Thomas
806f36f2648SCruise Hung DC_LOG_DEBUG("DMCUB STATE:");
807f36f2648SCruise Hung DC_LOG_DEBUG(" dmcub_version : %08x", diag_data.dmcub_version);
808f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [0] : %08x", diag_data.scratch[0]);
809f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [1] : %08x", diag_data.scratch[1]);
810f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [2] : %08x", diag_data.scratch[2]);
811f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [3] : %08x", diag_data.scratch[3]);
812f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [4] : %08x", diag_data.scratch[4]);
813f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [5] : %08x", diag_data.scratch[5]);
814f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [6] : %08x", diag_data.scratch[6]);
815f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [7] : %08x", diag_data.scratch[7]);
816f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [8] : %08x", diag_data.scratch[8]);
817f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [9] : %08x", diag_data.scratch[9]);
818f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [10] : %08x", diag_data.scratch[10]);
819f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [11] : %08x", diag_data.scratch[11]);
820f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [12] : %08x", diag_data.scratch[12]);
821f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [13] : %08x", diag_data.scratch[13]);
822f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [14] : %08x", diag_data.scratch[14]);
823f36f2648SCruise Hung DC_LOG_DEBUG(" scratch [15] : %08x", diag_data.scratch[15]);
824f36f2648SCruise Hung DC_LOG_DEBUG(" pc : %08x", diag_data.pc);
825f36f2648SCruise Hung DC_LOG_DEBUG(" unk_fault_addr : %08x", diag_data.undefined_address_fault_addr);
826f36f2648SCruise Hung DC_LOG_DEBUG(" inst_fault_addr : %08x", diag_data.inst_fetch_fault_addr);
827f36f2648SCruise Hung DC_LOG_DEBUG(" data_fault_addr : %08x", diag_data.data_write_fault_addr);
828f36f2648SCruise Hung DC_LOG_DEBUG(" inbox1_rptr : %08x", diag_data.inbox1_rptr);
829f36f2648SCruise Hung DC_LOG_DEBUG(" inbox1_wptr : %08x", diag_data.inbox1_wptr);
830f36f2648SCruise Hung DC_LOG_DEBUG(" inbox1_size : %08x", diag_data.inbox1_size);
831f36f2648SCruise Hung DC_LOG_DEBUG(" inbox0_rptr : %08x", diag_data.inbox0_rptr);
832f36f2648SCruise Hung DC_LOG_DEBUG(" inbox0_wptr : %08x", diag_data.inbox0_wptr);
833f36f2648SCruise Hung DC_LOG_DEBUG(" inbox0_size : %08x", diag_data.inbox0_size);
834f36f2648SCruise Hung DC_LOG_DEBUG(" is_enabled : %d", diag_data.is_dmcub_enabled);
835f36f2648SCruise Hung DC_LOG_DEBUG(" is_soft_reset : %d", diag_data.is_dmcub_soft_reset);
836f36f2648SCruise Hung DC_LOG_DEBUG(" is_secure_reset : %d", diag_data.is_dmcub_secure_reset);
837f36f2648SCruise Hung DC_LOG_DEBUG(" is_traceport_en : %d", diag_data.is_traceport_en);
838f36f2648SCruise Hung DC_LOG_DEBUG(" is_cw0_en : %d", diag_data.is_cw0_enabled);
839f36f2648SCruise Hung DC_LOG_DEBUG(" is_cw6_en : %d", diag_data.is_cw6_enabled);
8402631ac1aSAshley Thomas }
841b73353f7SMax Tseng
dc_can_pipe_disable_cursor(struct pipe_ctx * pipe_ctx)842f7085cbfSMax Tseng static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
843f7085cbfSMax Tseng {
844f7085cbfSMax Tseng struct pipe_ctx *test_pipe, *split_pipe;
845f7085cbfSMax Tseng const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data;
846f7085cbfSMax Tseng struct rect r1 = scl_data->recout, r2, r2_half;
847f7085cbfSMax Tseng int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b;
848f7085cbfSMax Tseng int cur_layer = pipe_ctx->plane_state->layer_index;
849f7085cbfSMax Tseng
850f7085cbfSMax Tseng /**
851f7085cbfSMax Tseng * Disable the cursor if there's another pipe above this with a
852f7085cbfSMax Tseng * plane that contains this pipe's viewport to prevent double cursor
853f7085cbfSMax Tseng * and incorrect scaling artifacts.
854f7085cbfSMax Tseng */
855f7085cbfSMax Tseng for (test_pipe = pipe_ctx->top_pipe; test_pipe;
856f7085cbfSMax Tseng test_pipe = test_pipe->top_pipe) {
857f7085cbfSMax Tseng // Skip invisible layer and pipe-split plane on same layer
858f7085cbfSMax Tseng if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer)
859f7085cbfSMax Tseng continue;
860f7085cbfSMax Tseng
861f7085cbfSMax Tseng r2 = test_pipe->plane_res.scl_data.recout;
862f7085cbfSMax Tseng r2_r = r2.x + r2.width;
863f7085cbfSMax Tseng r2_b = r2.y + r2.height;
864f7085cbfSMax Tseng split_pipe = test_pipe;
865f7085cbfSMax Tseng
866f7085cbfSMax Tseng /**
867f7085cbfSMax Tseng * There is another half plane on same layer because of
868f7085cbfSMax Tseng * pipe-split, merge together per same height.
869f7085cbfSMax Tseng */
870f7085cbfSMax Tseng for (split_pipe = pipe_ctx->top_pipe; split_pipe;
871f7085cbfSMax Tseng split_pipe = split_pipe->top_pipe)
872f7085cbfSMax Tseng if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {
873f7085cbfSMax Tseng r2_half = split_pipe->plane_res.scl_data.recout;
874f7085cbfSMax Tseng r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x;
875f7085cbfSMax Tseng r2.width = r2.width + r2_half.width;
876f7085cbfSMax Tseng r2_r = r2.x + r2.width;
877f7085cbfSMax Tseng break;
878f7085cbfSMax Tseng }
879f7085cbfSMax Tseng
880f7085cbfSMax Tseng if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b)
881f7085cbfSMax Tseng return true;
882f7085cbfSMax Tseng }
883f7085cbfSMax Tseng
884f7085cbfSMax Tseng return false;
885f7085cbfSMax Tseng }
886f7085cbfSMax Tseng
dc_dmub_should_update_cursor_data(struct pipe_ctx * pipe_ctx)887b73353f7SMax Tseng static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)
888b73353f7SMax Tseng {
889b73353f7SMax Tseng if (pipe_ctx->plane_state != NULL) {
890b73353f7SMax Tseng if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
891b73353f7SMax Tseng return false;
892f7085cbfSMax Tseng
893f7085cbfSMax Tseng if (dc_can_pipe_disable_cursor(pipe_ctx))
894f7085cbfSMax Tseng return false;
895b73353f7SMax Tseng }
896b73353f7SMax Tseng
897b73353f7SMax Tseng if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
898b73353f7SMax Tseng pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&
899b73353f7SMax Tseng pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)
900b73353f7SMax Tseng return true;
901b73353f7SMax Tseng
902c84f5123SBhawanpreet Lakha if (pipe_ctx->stream->link->replay_settings.config.replay_supported)
903c84f5123SBhawanpreet Lakha return true;
904c84f5123SBhawanpreet Lakha
905b73353f7SMax Tseng return false;
906b73353f7SMax Tseng }
907b73353f7SMax Tseng
dc_build_cursor_update_payload0(struct pipe_ctx * pipe_ctx,uint8_t p_idx,struct dmub_cmd_update_cursor_payload0 * payload)908b73353f7SMax Tseng static void dc_build_cursor_update_payload0(
909b73353f7SMax Tseng struct pipe_ctx *pipe_ctx, uint8_t p_idx,
910b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 *payload)
911b73353f7SMax Tseng {
912b73353f7SMax Tseng struct hubp *hubp = pipe_ctx->plane_res.hubp;
913b73353f7SMax Tseng unsigned int panel_inst = 0;
914b73353f7SMax Tseng
915b73353f7SMax Tseng if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
916b73353f7SMax Tseng pipe_ctx->stream->link, &panel_inst))
917b73353f7SMax Tseng return;
918b73353f7SMax Tseng
919b73353f7SMax Tseng /* Payload: Cursor Rect is built from position & attribute
920b73353f7SMax Tseng * x & y are obtained from postion
921b73353f7SMax Tseng */
922b73353f7SMax Tseng payload->cursor_rect.x = hubp->cur_rect.x;
923b73353f7SMax Tseng payload->cursor_rect.y = hubp->cur_rect.y;
924b73353f7SMax Tseng /* w & h are obtained from attribute */
925b73353f7SMax Tseng payload->cursor_rect.width = hubp->cur_rect.w;
926b73353f7SMax Tseng payload->cursor_rect.height = hubp->cur_rect.h;
927b73353f7SMax Tseng
928b73353f7SMax Tseng payload->enable = hubp->pos.cur_ctl.bits.cur_enable;
929b73353f7SMax Tseng payload->pipe_idx = p_idx;
930b73353f7SMax Tseng payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
931b73353f7SMax Tseng payload->panel_inst = panel_inst;
932b73353f7SMax Tseng }
933b73353f7SMax Tseng
dc_build_cursor_position_update_payload0(struct dmub_cmd_update_cursor_payload0 * pl,const uint8_t p_idx,const struct hubp * hubp,const struct dpp * dpp)934b73353f7SMax Tseng static void dc_build_cursor_position_update_payload0(
935b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx,
936b73353f7SMax Tseng const struct hubp *hubp, const struct dpp *dpp)
937b73353f7SMax Tseng {
938b73353f7SMax Tseng /* Hubp */
939b73353f7SMax Tseng pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw;
940b73353f7SMax Tseng pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;
941b73353f7SMax Tseng pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;
942b73353f7SMax Tseng pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;
943b73353f7SMax Tseng
944b73353f7SMax Tseng /* dpp */
945b73353f7SMax Tseng pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;
946b73353f7SMax Tseng pl->position_cfg.pipe_idx = p_idx;
947b73353f7SMax Tseng }
948b73353f7SMax Tseng
dc_build_cursor_attribute_update_payload1(struct dmub_cursor_attributes_cfg * pl_A,const uint8_t p_idx,const struct hubp * hubp,const struct dpp * dpp)949b73353f7SMax Tseng static void dc_build_cursor_attribute_update_payload1(
950b73353f7SMax Tseng struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx,
951b73353f7SMax Tseng const struct hubp *hubp, const struct dpp *dpp)
952b73353f7SMax Tseng {
953b73353f7SMax Tseng /* Hubp */
954b73353f7SMax Tseng pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;
955b73353f7SMax Tseng pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;
956b73353f7SMax Tseng pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw;
957b73353f7SMax Tseng pl_A->aHubp.size.raw = hubp->att.size.raw;
958b73353f7SMax Tseng pl_A->aHubp.settings.raw = hubp->att.settings.raw;
959b73353f7SMax Tseng
960b73353f7SMax Tseng /* dpp */
961b73353f7SMax Tseng pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;
962b73353f7SMax Tseng }
963b73353f7SMax Tseng
964b73353f7SMax Tseng /**
9656be153dcSRodrigo Siqueira * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command
966b73353f7SMax Tseng *
9676be153dcSRodrigo Siqueira * @pCtx: [in] pipe context
9686be153dcSRodrigo Siqueira * @pipe_idx: [in] pipe index
969b73353f7SMax Tseng *
9706be153dcSRodrigo Siqueira * This function would store the cursor related information and pass it into
9716be153dcSRodrigo Siqueira * dmub
972b73353f7SMax Tseng */
dc_send_update_cursor_info_to_dmu(struct pipe_ctx * pCtx,uint8_t pipe_idx)973b73353f7SMax Tseng void dc_send_update_cursor_info_to_dmu(
974b73353f7SMax Tseng struct pipe_ctx *pCtx, uint8_t pipe_idx)
975b73353f7SMax Tseng {
976e97cc04fSJosip Pavic union dmub_rb_cmd cmd[2];
977e97cc04fSJosip Pavic union dmub_cmd_update_cursor_info_data *update_cursor_info_0 =
978e97cc04fSJosip Pavic &cmd[0].update_cursor_info.update_cursor_info_data;
979e97cc04fSJosip Pavic
980e97cc04fSJosip Pavic memset(cmd, 0, sizeof(cmd));
981b73353f7SMax Tseng
982b73353f7SMax Tseng if (!dc_dmub_should_update_cursor_data(pCtx))
983b73353f7SMax Tseng return;
984b73353f7SMax Tseng /*
985b73353f7SMax Tseng * Since we use multi_cmd_pending for dmub command, the 2nd command is
986b73353f7SMax Tseng * only assigned to store cursor attributes info.
987b73353f7SMax Tseng * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other
988b73353f7SMax Tseng * is to store cursor position info.
989b73353f7SMax Tseng *
990b73353f7SMax Tseng * Command heaer type must be the same type if using multi_cmd_pending.
991b73353f7SMax Tseng * Besides, while process 2nd command in DMU, the sub type is useless.
992b73353f7SMax Tseng * So it's meanless to pass the sub type header with different type.
993b73353f7SMax Tseng */
994b73353f7SMax Tseng
995b73353f7SMax Tseng {
996b73353f7SMax Tseng /* Build Payload#0 Header */
997e97cc04fSJosip Pavic cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
998e97cc04fSJosip Pavic cmd[0].update_cursor_info.header.payload_bytes =
999e97cc04fSJosip Pavic sizeof(cmd[0].update_cursor_info.update_cursor_info_data);
1000e97cc04fSJosip Pavic cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd
1001b73353f7SMax Tseng
1002b73353f7SMax Tseng /* Prepare Payload */
1003e97cc04fSJosip Pavic dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info_0->payload0);
1004b73353f7SMax Tseng
1005e97cc04fSJosip Pavic dc_build_cursor_position_update_payload0(&update_cursor_info_0->payload0, pipe_idx,
1006b73353f7SMax Tseng pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1007b73353f7SMax Tseng }
1008b73353f7SMax Tseng {
1009b73353f7SMax Tseng /* Build Payload#1 Header */
1010e97cc04fSJosip Pavic cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1011e97cc04fSJosip Pavic cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg);
1012e97cc04fSJosip Pavic cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command.
1013b73353f7SMax Tseng
1014b73353f7SMax Tseng dc_build_cursor_attribute_update_payload1(
1015e97cc04fSJosip Pavic &cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg,
1016b73353f7SMax Tseng pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1017b73353f7SMax Tseng
1018b73353f7SMax Tseng /* Combine 2nd cmds update_curosr_info to DMU */
1019e97cc04fSJosip Pavic dm_execute_dmub_cmd_list(pCtx->stream->ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT);
1020b73353f7SMax Tseng }
1021b73353f7SMax Tseng }
1022c35b6ea8SMario Limonciello
dc_dmub_check_min_version(struct dmub_srv * srv)1023c35b6ea8SMario Limonciello bool dc_dmub_check_min_version(struct dmub_srv *srv)
1024c35b6ea8SMario Limonciello {
1025c35b6ea8SMario Limonciello if (!srv->hw_funcs.is_psrsu_supported)
1026c35b6ea8SMario Limonciello return true;
1027c35b6ea8SMario Limonciello return srv->hw_funcs.is_psrsu_supported(srv);
1028c35b6ea8SMario Limonciello }
102971ba6b57SStylon Wang
dc_dmub_srv_enable_dpia_trace(const struct dc * dc)103071ba6b57SStylon Wang void dc_dmub_srv_enable_dpia_trace(const struct dc *dc)
103171ba6b57SStylon Wang {
103271ba6b57SStylon Wang struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;
103371ba6b57SStylon Wang struct dmub_srv *dmub;
103471ba6b57SStylon Wang enum dmub_status status;
103571ba6b57SStylon Wang static const uint32_t timeout_us = 30;
103671ba6b57SStylon Wang
103771ba6b57SStylon Wang if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
103871ba6b57SStylon Wang DC_LOG_ERROR("%s: invalid parameters.", __func__);
103971ba6b57SStylon Wang return;
104071ba6b57SStylon Wang }
104171ba6b57SStylon Wang
104271ba6b57SStylon Wang dmub = dc_dmub_srv->dmub;
104371ba6b57SStylon Wang
104471ba6b57SStylon Wang status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1, 0x0010, timeout_us);
104571ba6b57SStylon Wang if (status != DMUB_STATUS_OK) {
104671ba6b57SStylon Wang DC_LOG_ERROR("timeout updating trace buffer mask word\n");
104771ba6b57SStylon Wang return;
104871ba6b57SStylon Wang }
104971ba6b57SStylon Wang
105071ba6b57SStylon Wang status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK, 0x0000, timeout_us);
105171ba6b57SStylon Wang if (status != DMUB_STATUS_OK) {
105271ba6b57SStylon Wang DC_LOG_ERROR("timeout updating trace buffer mask word\n");
105371ba6b57SStylon Wang return;
105471ba6b57SStylon Wang }
105571ba6b57SStylon Wang
105671ba6b57SStylon Wang DC_LOG_DEBUG("Enabled DPIA trace\n");
105771ba6b57SStylon Wang }