1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #ifndef DC_DDC_TYPES_H_
26 #define DC_DDC_TYPES_H_
27 
28 enum aux_transaction_type {
29 	AUX_TRANSACTION_TYPE_DP,
30 	AUX_TRANSACTION_TYPE_I2C
31 };
32 
33 
34 enum i2caux_transaction_action {
35 	I2CAUX_TRANSACTION_ACTION_I2C_WRITE = 0x00,
36 	I2CAUX_TRANSACTION_ACTION_I2C_READ = 0x10,
37 	I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20,
38 
39 	I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40,
40 	I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT = 0x50,
41 	I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60,
42 
43 	I2CAUX_TRANSACTION_ACTION_DP_WRITE = 0x80,
44 	I2CAUX_TRANSACTION_ACTION_DP_READ = 0x90
45 };
46 
47 enum aux_channel_operation_result {
48 	AUX_CHANNEL_OPERATION_SUCCEEDED,
49 	AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN,
50 	AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY,
51 	AUX_CHANNEL_OPERATION_FAILED_TIMEOUT,
52 	AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON
53 };
54 
55 
56 struct aux_request_transaction_data {
57 	enum aux_transaction_type type;
58 	enum i2caux_transaction_action action;
59 	/* 20-bit AUX channel transaction address */
60 	uint32_t address;
61 	/* delay, in 100-microsecond units */
62 	uint8_t delay;
63 	uint32_t length;
64 	uint8_t *data;
65 };
66 
67 enum aux_transaction_reply {
68 	AUX_TRANSACTION_REPLY_AUX_ACK = 0x00,
69 	AUX_TRANSACTION_REPLY_AUX_NACK = 0x01,
70 	AUX_TRANSACTION_REPLY_AUX_DEFER = 0x02,
71 
72 	AUX_TRANSACTION_REPLY_I2C_ACK = 0x00,
73 	AUX_TRANSACTION_REPLY_I2C_NACK = 0x10,
74 	AUX_TRANSACTION_REPLY_I2C_DEFER = 0x20,
75 
76 	AUX_TRANSACTION_REPLY_HPD_DISCON = 0x40,
77 
78 	AUX_TRANSACTION_REPLY_INVALID = 0xFF
79 };
80 
81 struct aux_reply_transaction_data {
82 	enum aux_transaction_reply status;
83 	uint32_t length;
84 	uint8_t *data;
85 };
86 
87 struct i2c_payload {
88 	bool write;
89 	uint8_t address;
90 	uint32_t length;
91 	uint8_t *data;
92 };
93 
94 enum i2c_command_engine {
95 	I2C_COMMAND_ENGINE_DEFAULT,
96 	I2C_COMMAND_ENGINE_SW,
97 	I2C_COMMAND_ENGINE_HW
98 };
99 
100 struct i2c_command {
101 	struct i2c_payload *payloads;
102 	uint8_t number_of_payloads;
103 
104 	enum i2c_command_engine engine;
105 
106 	/* expressed in KHz
107 	 * zero means "use default value" */
108 	uint32_t speed;
109 };
110 
111 struct gpio_ddc_hw_info {
112 	bool hw_supported;
113 	uint32_t ddc_channel;
114 };
115 
116 struct ddc {
117 	struct gpio *pin_data;
118 	struct gpio *pin_clock;
119 	struct gpio_ddc_hw_info hw_info;
120 	struct dc_context *ctx;
121 };
122 
123 union ddc_wa {
124 	struct {
125 		uint32_t DP_SKIP_POWER_OFF:1;
126 		uint32_t DP_AUX_POWER_UP_WA_DELAY:1;
127 	} bits;
128 	uint32_t raw;
129 };
130 
131 struct ddc_flags {
132 	uint8_t EDID_QUERY_DONE_ONCE:1;
133 	uint8_t IS_INTERNAL_DISPLAY:1;
134 	uint8_t FORCE_READ_REPEATED_START:1;
135 	uint8_t EDID_STRESS_READ:1;
136 
137 };
138 
139 enum ddc_transaction_type {
140 	DDC_TRANSACTION_TYPE_NONE = 0,
141 	DDC_TRANSACTION_TYPE_I2C,
142 	DDC_TRANSACTION_TYPE_I2C_OVER_AUX,
143 	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER,
144 	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER
145 };
146 
147 enum display_dongle_type {
148 	DISPLAY_DONGLE_NONE = 0,
149 	/* Active converter types*/
150 	DISPLAY_DONGLE_DP_VGA_CONVERTER,
151 	DISPLAY_DONGLE_DP_DVI_CONVERTER,
152 	DISPLAY_DONGLE_DP_HDMI_CONVERTER,
153 	/* DP-HDMI/DVI passive dongles (Type 1 and Type 2)*/
154 	DISPLAY_DONGLE_DP_DVI_DONGLE,
155 	DISPLAY_DONGLE_DP_HDMI_DONGLE,
156 	/* Other types of dongle*/
157 	DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE,
158 };
159 
160 struct ddc_service {
161 	struct ddc *ddc_pin;
162 	struct ddc_flags flags;
163 	union ddc_wa wa;
164 	enum ddc_transaction_type transaction_type;
165 	enum display_dongle_type dongle_type;
166 	struct dc_context *ctx;
167 	struct dc_link *link;
168 
169 	uint32_t address;
170 	uint32_t edid_buf_len;
171 	uint8_t edid_buf[DC_MAX_EDID_BUFFER_SIZE];
172 };
173 
174 #endif /* DC_DDC_TYPES_H_ */
175