1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.35" 43 44 #define MAX_SURFACES 3 45 #define MAX_PLANES 6 46 #define MAX_STREAMS 6 47 #define MAX_SINKS_PER_LINK 4 48 49 /******************************************************************************* 50 * Display Core Interfaces 51 ******************************************************************************/ 52 struct dc_versions { 53 const char *dc_ver; 54 struct dmcu_version dmcu_version; 55 }; 56 57 enum dc_plane_type { 58 DC_PLANE_TYPE_INVALID, 59 DC_PLANE_TYPE_DCE_RGB, 60 DC_PLANE_TYPE_DCE_UNDERLAY, 61 DC_PLANE_TYPE_DCN_UNIVERSAL, 62 }; 63 64 struct dc_plane_cap { 65 enum dc_plane_type type; 66 uint32_t blends_with_above : 1; 67 uint32_t blends_with_below : 1; 68 uint32_t per_pixel_alpha : 1; 69 struct { 70 uint32_t argb8888 : 1; 71 uint32_t nv12 : 1; 72 uint32_t fp16 : 1; 73 } pixel_format_support; 74 // max upscaling factor x1000 75 // upscaling factors are always >= 1 76 // for example, 1080p -> 8K is 4.0, or 4000 raw value 77 struct { 78 uint32_t argb8888; 79 uint32_t nv12; 80 uint32_t fp16; 81 } max_upscale_factor; 82 // max downscale factor x1000 83 // downscale factors are always <= 1 84 // for example, 8K -> 1080p is 0.25, or 250 raw value 85 struct { 86 uint32_t argb8888; 87 uint32_t nv12; 88 uint32_t fp16; 89 } max_downscale_factor; 90 }; 91 92 struct dc_caps { 93 uint32_t max_streams; 94 uint32_t max_links; 95 uint32_t max_audios; 96 uint32_t max_slave_planes; 97 uint32_t max_planes; 98 uint32_t max_downscale_ratio; 99 uint32_t i2c_speed_in_khz; 100 uint32_t dmdata_alloc_size; 101 unsigned int max_cursor_size; 102 unsigned int max_video_width; 103 int linear_pitch_alignment; 104 bool dcc_const_color; 105 bool dynamic_audio; 106 bool is_apu; 107 bool dual_link_dvi; 108 bool post_blend_color_processing; 109 bool force_dp_tps4_for_cp2520; 110 bool disable_dp_clk_share; 111 bool psp_setup_panel_mode; 112 struct dc_plane_cap planes[MAX_PLANES]; 113 }; 114 115 struct dc_dcc_surface_param { 116 struct dc_size surface_size; 117 enum surface_pixel_format format; 118 enum swizzle_mode_values swizzle_mode; 119 enum dc_scan_direction scan; 120 }; 121 122 struct dc_dcc_setting { 123 unsigned int max_compressed_blk_size; 124 unsigned int max_uncompressed_blk_size; 125 bool independent_64b_blks; 126 }; 127 128 struct dc_surface_dcc_cap { 129 union { 130 struct { 131 struct dc_dcc_setting rgb; 132 } grph; 133 134 struct { 135 struct dc_dcc_setting luma; 136 struct dc_dcc_setting chroma; 137 } video; 138 }; 139 140 bool capable; 141 bool const_color_support; 142 }; 143 144 struct dc_static_screen_events { 145 bool force_trigger; 146 bool cursor_update; 147 bool surface_update; 148 bool overlay_update; 149 }; 150 151 152 /* Surface update type is used by dc_update_surfaces_and_stream 153 * The update type is determined at the very beginning of the function based 154 * on parameters passed in and decides how much programming (or updating) is 155 * going to be done during the call. 156 * 157 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 158 * logical calculations or hardware register programming. This update MUST be 159 * ISR safe on windows. Currently fast update will only be used to flip surface 160 * address. 161 * 162 * UPDATE_TYPE_MED is used for slower updates which require significant hw 163 * re-programming however do not affect bandwidth consumption or clock 164 * requirements. At present, this is the level at which front end updates 165 * that do not require us to run bw_calcs happen. These are in/out transfer func 166 * updates, viewport offset changes, recout size changes and pixel depth changes. 167 * This update can be done at ISR, but we want to minimize how often this happens. 168 * 169 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 170 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 171 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 172 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 173 * a full update. This cannot be done at ISR level and should be a rare event. 174 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 175 * underscan we don't expect to see this call at all. 176 */ 177 178 enum surface_update_type { 179 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 180 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 181 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 182 }; 183 184 /* Forward declaration*/ 185 struct dc; 186 struct dc_plane_state; 187 struct dc_state; 188 189 190 struct dc_cap_funcs { 191 bool (*get_dcc_compression_cap)(const struct dc *dc, 192 const struct dc_dcc_surface_param *input, 193 struct dc_surface_dcc_cap *output); 194 }; 195 196 struct link_training_settings; 197 198 199 /* Structure to hold configuration flags set by dm at dc creation. */ 200 struct dc_config { 201 bool gpu_vm_support; 202 bool disable_disp_pll_sharing; 203 bool fbc_support; 204 bool optimize_edp_link_rate; 205 bool disable_fractional_pwm; 206 bool allow_seamless_boot_optimization; 207 bool power_down_display_on_boot; 208 bool edp_not_connected; 209 }; 210 211 enum visual_confirm { 212 VISUAL_CONFIRM_DISABLE = 0, 213 VISUAL_CONFIRM_SURFACE = 1, 214 VISUAL_CONFIRM_HDR = 2, 215 }; 216 217 enum dcc_option { 218 DCC_ENABLE = 0, 219 DCC_DISABLE = 1, 220 DCC_HALF_REQ_DISALBE = 2, 221 }; 222 223 enum pipe_split_policy { 224 MPC_SPLIT_DYNAMIC = 0, 225 MPC_SPLIT_AVOID = 1, 226 MPC_SPLIT_AVOID_MULT_DISP = 2, 227 }; 228 229 enum wm_report_mode { 230 WM_REPORT_DEFAULT = 0, 231 WM_REPORT_OVERRIDE = 1, 232 }; 233 234 /* 235 * For any clocks that may differ per pipe 236 * only the max is stored in this structure 237 */ 238 struct dc_clocks { 239 int dispclk_khz; 240 int max_supported_dppclk_khz; 241 int dppclk_khz; 242 int dcfclk_khz; 243 int socclk_khz; 244 int dcfclk_deep_sleep_khz; 245 int fclk_khz; 246 int phyclk_khz; 247 int dramclk_khz; 248 bool p_state_change_support; 249 }; 250 251 struct dc_bw_validation_profile { 252 bool enable; 253 254 unsigned long long total_ticks; 255 unsigned long long voltage_level_ticks; 256 unsigned long long watermark_ticks; 257 unsigned long long rq_dlg_ticks; 258 259 unsigned long long total_count; 260 unsigned long long skip_fast_count; 261 unsigned long long skip_pass_count; 262 unsigned long long skip_fail_count; 263 }; 264 265 #define BW_VAL_TRACE_SETUP() \ 266 unsigned long long end_tick = 0; \ 267 unsigned long long voltage_level_tick = 0; \ 268 unsigned long long watermark_tick = 0; \ 269 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 270 dm_get_timestamp(dc->ctx) : 0 271 272 #define BW_VAL_TRACE_COUNT() \ 273 if (dc->debug.bw_val_profile.enable) \ 274 dc->debug.bw_val_profile.total_count++ 275 276 #define BW_VAL_TRACE_SKIP(status) \ 277 if (dc->debug.bw_val_profile.enable) { \ 278 if (!voltage_level_tick) \ 279 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 280 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 281 } 282 283 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 284 if (dc->debug.bw_val_profile.enable) \ 285 voltage_level_tick = dm_get_timestamp(dc->ctx) 286 287 #define BW_VAL_TRACE_END_WATERMARKS() \ 288 if (dc->debug.bw_val_profile.enable) \ 289 watermark_tick = dm_get_timestamp(dc->ctx) 290 291 #define BW_VAL_TRACE_FINISH() \ 292 if (dc->debug.bw_val_profile.enable) { \ 293 end_tick = dm_get_timestamp(dc->ctx); \ 294 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 295 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 296 if (watermark_tick) { \ 297 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 298 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 299 } \ 300 } 301 302 struct dc_debug_options { 303 enum visual_confirm visual_confirm; 304 bool sanity_checks; 305 bool max_disp_clk; 306 bool surface_trace; 307 bool timing_trace; 308 bool clock_trace; 309 bool validation_trace; 310 bool bandwidth_calcs_trace; 311 int max_downscale_src_width; 312 313 /* stutter efficiency related */ 314 bool disable_stutter; 315 bool use_max_lb; 316 enum dcc_option disable_dcc; 317 enum pipe_split_policy pipe_split_policy; 318 bool force_single_disp_pipe_split; 319 bool voltage_align_fclk; 320 321 bool disable_dfs_bypass; 322 bool disable_dpp_power_gate; 323 bool disable_hubp_power_gate; 324 bool disable_pplib_wm_range; 325 enum wm_report_mode pplib_wm_report_mode; 326 unsigned int min_disp_clk_khz; 327 int sr_exit_time_dpm0_ns; 328 int sr_enter_plus_exit_time_dpm0_ns; 329 int sr_exit_time_ns; 330 int sr_enter_plus_exit_time_ns; 331 int urgent_latency_ns; 332 int percent_of_ideal_drambw; 333 int dram_clock_change_latency_ns; 334 bool optimized_watermark; 335 int always_scale; 336 bool disable_pplib_clock_request; 337 bool disable_clock_gate; 338 bool disable_dmcu; 339 bool disable_psr; 340 bool force_abm_enable; 341 bool disable_stereo_support; 342 bool vsr_support; 343 bool performance_trace; 344 bool az_endpoint_mute_only; 345 bool always_use_regamma; 346 bool p010_mpo_support; 347 bool recovery_enabled; 348 bool avoid_vbios_exec_table; 349 bool scl_reset_length10; 350 bool hdmi20_disable; 351 bool skip_detection_link_training; 352 unsigned int force_odm_combine; //bit vector based on otg inst 353 unsigned int force_fclk_khz; 354 bool disable_tri_buf; 355 struct dc_bw_validation_profile bw_val_profile; 356 }; 357 358 struct dc_debug_data { 359 uint32_t ltFailCount; 360 uint32_t i2cErrorCount; 361 uint32_t auxErrorCount; 362 }; 363 364 struct dc_bounding_box_overrides { 365 int sr_exit_time_ns; 366 int sr_enter_plus_exit_time_ns; 367 int urgent_latency_ns; 368 int percent_of_ideal_drambw; 369 int dram_clock_change_latency_ns; 370 int min_dcfclk_mhz; 371 }; 372 373 struct dc_state; 374 struct resource_pool; 375 struct dce_hwseq; 376 struct gpu_info_soc_bounding_box_v1_0; 377 struct dc { 378 struct dc_versions versions; 379 struct dc_caps caps; 380 struct dc_cap_funcs cap_funcs; 381 struct dc_config config; 382 struct dc_debug_options debug; 383 struct dc_bounding_box_overrides bb_overrides; 384 struct dc_context *ctx; 385 386 uint8_t link_count; 387 struct dc_link *links[MAX_PIPES * 2]; 388 389 struct dc_state *current_state; 390 struct resource_pool *res_pool; 391 392 struct clk_mgr *clk_mgr; 393 394 /* Display Engine Clock levels */ 395 struct dm_pp_clock_levels sclk_lvls; 396 397 /* Inputs into BW and WM calculations. */ 398 struct bw_calcs_dceip *bw_dceip; 399 struct bw_calcs_vbios *bw_vbios; 400 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 401 struct dcn_soc_bounding_box *dcn_soc; 402 struct dcn_ip_params *dcn_ip; 403 struct display_mode_lib dml; 404 #endif 405 406 /* HW functions */ 407 struct hw_sequencer_funcs hwss; 408 struct dce_hwseq *hwseq; 409 410 /* Require to optimize clocks and bandwidth for added/removed planes */ 411 bool optimized_required; 412 413 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 414 bool optimize_seamless_boot; 415 416 /* FBC compressor */ 417 struct compressor *fbc_compressor; 418 419 struct dc_debug_data debug_data; 420 421 const char *build_id; 422 }; 423 424 enum frame_buffer_mode { 425 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 426 FRAME_BUFFER_MODE_ZFB_ONLY, 427 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 428 } ; 429 430 struct dchub_init_data { 431 int64_t zfb_phys_addr_base; 432 int64_t zfb_mc_base_addr; 433 uint64_t zfb_size_in_byte; 434 enum frame_buffer_mode fb_mode; 435 bool dchub_initialzied; 436 bool dchub_info_valid; 437 }; 438 439 struct dc_init_data { 440 struct hw_asic_id asic_id; 441 void *driver; /* ctx */ 442 struct cgs_device *cgs_device; 443 struct dc_bounding_box_overrides bb_overrides; 444 445 int num_virtual_links; 446 /* 447 * If 'vbios_override' not NULL, it will be called instead 448 * of the real VBIOS. Intended use is Diagnostics on FPGA. 449 */ 450 struct dc_bios *vbios_override; 451 enum dce_environment dce_environment; 452 453 struct dc_config flags; 454 uint32_t log_mask; 455 456 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 457 /** 458 * gpu_info FW provided soc bounding box struct or 0 if not 459 * available in FW 460 */ 461 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 462 #endif 463 }; 464 465 struct dc_callback_init { 466 uint8_t reserved; 467 }; 468 469 struct dc *dc_create(const struct dc_init_data *init_params); 470 void dc_init_callbacks(struct dc *dc, 471 const struct dc_callback_init *init_params); 472 void dc_destroy(struct dc **dc); 473 474 /******************************************************************************* 475 * Surface Interfaces 476 ******************************************************************************/ 477 478 enum { 479 TRANSFER_FUNC_POINTS = 1025 480 }; 481 482 struct dc_hdr_static_metadata { 483 /* display chromaticities and white point in units of 0.00001 */ 484 unsigned int chromaticity_green_x; 485 unsigned int chromaticity_green_y; 486 unsigned int chromaticity_blue_x; 487 unsigned int chromaticity_blue_y; 488 unsigned int chromaticity_red_x; 489 unsigned int chromaticity_red_y; 490 unsigned int chromaticity_white_point_x; 491 unsigned int chromaticity_white_point_y; 492 493 uint32_t min_luminance; 494 uint32_t max_luminance; 495 uint32_t maximum_content_light_level; 496 uint32_t maximum_frame_average_light_level; 497 }; 498 499 enum dc_transfer_func_type { 500 TF_TYPE_PREDEFINED, 501 TF_TYPE_DISTRIBUTED_POINTS, 502 TF_TYPE_BYPASS, 503 TF_TYPE_HWPWL 504 }; 505 506 struct dc_transfer_func_distributed_points { 507 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 508 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 509 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 510 511 uint16_t end_exponent; 512 uint16_t x_point_at_y1_red; 513 uint16_t x_point_at_y1_green; 514 uint16_t x_point_at_y1_blue; 515 }; 516 517 enum dc_transfer_func_predefined { 518 TRANSFER_FUNCTION_SRGB, 519 TRANSFER_FUNCTION_BT709, 520 TRANSFER_FUNCTION_PQ, 521 TRANSFER_FUNCTION_LINEAR, 522 TRANSFER_FUNCTION_UNITY, 523 TRANSFER_FUNCTION_HLG, 524 TRANSFER_FUNCTION_HLG12, 525 TRANSFER_FUNCTION_GAMMA22 526 }; 527 528 struct dc_transfer_func { 529 struct kref refcount; 530 enum dc_transfer_func_type type; 531 enum dc_transfer_func_predefined tf; 532 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 533 uint32_t sdr_ref_white_level; 534 struct dc_context *ctx; 535 union { 536 struct pwl_params pwl; 537 struct dc_transfer_func_distributed_points tf_pts; 538 }; 539 }; 540 541 /* 542 * This structure is filled in by dc_surface_get_status and contains 543 * the last requested address and the currently active address so the called 544 * can determine if there are any outstanding flips 545 */ 546 struct dc_plane_status { 547 struct dc_plane_address requested_address; 548 struct dc_plane_address current_address; 549 bool is_flip_pending; 550 bool is_right_eye; 551 }; 552 553 union surface_update_flags { 554 555 struct { 556 uint32_t addr_update:1; 557 /* Medium updates */ 558 uint32_t dcc_change:1; 559 uint32_t color_space_change:1; 560 uint32_t horizontal_mirror_change:1; 561 uint32_t per_pixel_alpha_change:1; 562 uint32_t global_alpha_change:1; 563 uint32_t sdr_white_level:1; 564 uint32_t rotation_change:1; 565 uint32_t swizzle_change:1; 566 uint32_t scaling_change:1; 567 uint32_t position_change:1; 568 uint32_t in_transfer_func_change:1; 569 uint32_t input_csc_change:1; 570 uint32_t coeff_reduction_change:1; 571 uint32_t output_tf_change:1; 572 uint32_t pixel_format_change:1; 573 uint32_t plane_size_change:1; 574 575 /* Full updates */ 576 uint32_t new_plane:1; 577 uint32_t bpp_change:1; 578 uint32_t gamma_change:1; 579 uint32_t bandwidth_change:1; 580 uint32_t clock_change:1; 581 uint32_t stereo_format_change:1; 582 uint32_t full_update:1; 583 } bits; 584 585 uint32_t raw; 586 }; 587 588 struct dc_plane_state { 589 struct dc_plane_address address; 590 struct dc_plane_flip_time time; 591 struct scaling_taps scaling_quality; 592 struct rect src_rect; 593 struct rect dst_rect; 594 struct rect clip_rect; 595 596 union plane_size plane_size; 597 union dc_tiling_info tiling_info; 598 599 struct dc_plane_dcc_param dcc; 600 601 struct dc_gamma *gamma_correction; 602 struct dc_transfer_func *in_transfer_func; 603 struct dc_bias_and_scale *bias_and_scale; 604 struct dc_csc_transform input_csc_color_matrix; 605 struct fixed31_32 coeff_reduction_factor; 606 uint32_t sdr_white_level; 607 608 // TODO: No longer used, remove 609 struct dc_hdr_static_metadata hdr_static_ctx; 610 611 enum dc_color_space color_space; 612 613 enum surface_pixel_format format; 614 enum dc_rotation_angle rotation; 615 enum plane_stereo_format stereo_format; 616 617 bool is_tiling_rotated; 618 bool per_pixel_alpha; 619 bool global_alpha; 620 int global_alpha_value; 621 bool visible; 622 bool flip_immediate; 623 bool horizontal_mirror; 624 625 union surface_update_flags update_flags; 626 /* private to DC core */ 627 struct dc_plane_status status; 628 struct dc_context *ctx; 629 630 /* HACK: Workaround for forcing full reprogramming under some conditions */ 631 bool force_full_update; 632 633 /* private to dc_surface.c */ 634 enum dc_irq_source irq_source; 635 struct kref refcount; 636 }; 637 638 struct dc_plane_info { 639 union plane_size plane_size; 640 union dc_tiling_info tiling_info; 641 struct dc_plane_dcc_param dcc; 642 enum surface_pixel_format format; 643 enum dc_rotation_angle rotation; 644 enum plane_stereo_format stereo_format; 645 enum dc_color_space color_space; 646 unsigned int sdr_white_level; 647 bool horizontal_mirror; 648 bool visible; 649 bool per_pixel_alpha; 650 bool global_alpha; 651 int global_alpha_value; 652 bool input_csc_enabled; 653 }; 654 655 struct dc_scaling_info { 656 struct rect src_rect; 657 struct rect dst_rect; 658 struct rect clip_rect; 659 struct scaling_taps scaling_quality; 660 }; 661 662 struct dc_surface_update { 663 struct dc_plane_state *surface; 664 665 /* isr safe update parameters. null means no updates */ 666 const struct dc_flip_addrs *flip_addr; 667 const struct dc_plane_info *plane_info; 668 const struct dc_scaling_info *scaling_info; 669 670 /* following updates require alloc/sleep/spin that is not isr safe, 671 * null means no updates 672 */ 673 const struct dc_gamma *gamma; 674 const struct dc_transfer_func *in_transfer_func; 675 676 const struct dc_csc_transform *input_csc_color_matrix; 677 const struct fixed31_32 *coeff_reduction_factor; 678 }; 679 680 /* 681 * Create a new surface with default parameters; 682 */ 683 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 684 const struct dc_plane_status *dc_plane_get_status( 685 const struct dc_plane_state *plane_state); 686 687 void dc_plane_state_retain(struct dc_plane_state *plane_state); 688 void dc_plane_state_release(struct dc_plane_state *plane_state); 689 690 void dc_gamma_retain(struct dc_gamma *dc_gamma); 691 void dc_gamma_release(struct dc_gamma **dc_gamma); 692 struct dc_gamma *dc_create_gamma(void); 693 694 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 695 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 696 struct dc_transfer_func *dc_create_transfer_func(void); 697 698 /* 699 * This structure holds a surface address. There could be multiple addresses 700 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 701 * as frame durations and DCC format can also be set. 702 */ 703 struct dc_flip_addrs { 704 struct dc_plane_address address; 705 unsigned int flip_timestamp_in_us; 706 bool flip_immediate; 707 /* TODO: add flip duration for FreeSync */ 708 }; 709 710 bool dc_post_update_surfaces_to_stream( 711 struct dc *dc); 712 713 #include "dc_stream.h" 714 715 /* 716 * Structure to store surface/stream associations for validation 717 */ 718 struct dc_validation_set { 719 struct dc_stream_state *stream; 720 struct dc_plane_state *plane_states[MAX_SURFACES]; 721 uint8_t plane_count; 722 }; 723 724 bool dc_validate_seamless_boot_timing(const struct dc *dc, 725 const struct dc_sink *sink, 726 struct dc_crtc_timing *crtc_timing); 727 728 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 729 730 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 731 732 /* 733 * fast_validate: we return after determining if we can support the new state, 734 * but before we populate the programming info 735 */ 736 enum dc_status dc_validate_global_state( 737 struct dc *dc, 738 struct dc_state *new_ctx, 739 bool fast_validate); 740 741 742 void dc_resource_state_construct( 743 const struct dc *dc, 744 struct dc_state *dst_ctx); 745 746 void dc_resource_state_copy_construct( 747 const struct dc_state *src_ctx, 748 struct dc_state *dst_ctx); 749 750 void dc_resource_state_copy_construct_current( 751 const struct dc *dc, 752 struct dc_state *dst_ctx); 753 754 void dc_resource_state_destruct(struct dc_state *context); 755 756 /* 757 * TODO update to make it about validation sets 758 * Set up streams and links associated to drive sinks 759 * The streams parameter is an absolute set of all active streams. 760 * 761 * After this call: 762 * Phy, Encoder, Timing Generator are programmed and enabled. 763 * New streams are enabled with blank stream; no memory read. 764 */ 765 bool dc_commit_state(struct dc *dc, struct dc_state *context); 766 767 768 struct dc_state *dc_create_state(struct dc *dc); 769 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 770 void dc_retain_state(struct dc_state *context); 771 void dc_release_state(struct dc_state *context); 772 773 /******************************************************************************* 774 * Link Interfaces 775 ******************************************************************************/ 776 777 struct dpcd_caps { 778 union dpcd_rev dpcd_rev; 779 union max_lane_count max_ln_count; 780 union max_down_spread max_down_spread; 781 union dprx_feature dprx_feature; 782 783 /* valid only for eDP v1.4 or higher*/ 784 uint8_t edp_supported_link_rates_count; 785 enum dc_link_rate edp_supported_link_rates[8]; 786 787 /* dongle type (DP converter, CV smart dongle) */ 788 enum display_dongle_type dongle_type; 789 /* branch device or sink device */ 790 bool is_branch_dev; 791 /* Dongle's downstream count. */ 792 union sink_count sink_count; 793 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 794 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 795 struct dc_dongle_caps dongle_caps; 796 797 uint32_t sink_dev_id; 798 int8_t sink_dev_id_str[6]; 799 int8_t sink_hw_revision; 800 int8_t sink_fw_revision[2]; 801 802 uint32_t branch_dev_id; 803 int8_t branch_dev_name[6]; 804 int8_t branch_hw_revision; 805 int8_t branch_fw_revision[2]; 806 807 bool allow_invalid_MSA_timing_param; 808 bool panel_mode_edp; 809 bool dpcd_display_control_capable; 810 bool ext_receiver_cap_field_present; 811 }; 812 813 #include "dc_link.h" 814 815 /******************************************************************************* 816 * Sink Interfaces - A sink corresponds to a display output device 817 ******************************************************************************/ 818 819 struct dc_container_id { 820 // 128bit GUID in binary form 821 unsigned char guid[16]; 822 // 8 byte port ID -> ELD.PortID 823 unsigned int portId[2]; 824 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 825 unsigned short manufacturerName; 826 // 2 byte product code -> ELD.ProductCode 827 unsigned short productCode; 828 }; 829 830 831 832 /* 833 * The sink structure contains EDID and other display device properties 834 */ 835 struct dc_sink { 836 enum signal_type sink_signal; 837 struct dc_edid dc_edid; /* raw edid */ 838 struct dc_edid_caps edid_caps; /* parse display caps */ 839 struct dc_container_id *dc_container_id; 840 uint32_t dongle_max_pix_clk; 841 void *priv; 842 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 843 bool converter_disable_audio; 844 845 /* private to DC core */ 846 struct dc_link *link; 847 struct dc_context *ctx; 848 849 uint32_t sink_id; 850 851 /* private to dc_sink.c */ 852 // refcount must be the last member in dc_sink, since we want the 853 // sink structure to be logically cloneable up to (but not including) 854 // refcount 855 struct kref refcount; 856 }; 857 858 void dc_sink_retain(struct dc_sink *sink); 859 void dc_sink_release(struct dc_sink *sink); 860 861 struct dc_sink_init_data { 862 enum signal_type sink_signal; 863 struct dc_link *link; 864 uint32_t dongle_max_pix_clk; 865 bool converter_disable_audio; 866 }; 867 868 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 869 870 /* Newer interfaces */ 871 struct dc_cursor { 872 struct dc_plane_address address; 873 struct dc_cursor_attributes attributes; 874 }; 875 876 877 /******************************************************************************* 878 * Interrupt interfaces 879 ******************************************************************************/ 880 enum dc_irq_source dc_interrupt_to_irq_source( 881 struct dc *dc, 882 uint32_t src_id, 883 uint32_t ext_id); 884 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 885 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 886 enum dc_irq_source dc_get_hpd_irq_source_at_index( 887 struct dc *dc, uint32_t link_index); 888 889 /******************************************************************************* 890 * Power Interfaces 891 ******************************************************************************/ 892 893 void dc_set_power_state( 894 struct dc *dc, 895 enum dc_acpi_cm_power_state power_state); 896 void dc_resume(struct dc *dc); 897 unsigned int dc_get_current_backlight_pwm(struct dc *dc); 898 unsigned int dc_get_target_backlight_pwm(struct dc *dc); 899 900 bool dc_is_dmcu_initialized(struct dc *dc); 901 902 #endif /* DC_INTERFACE_H_ */ 903