1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.196" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 // Sizes defined as multiples of 64KB 79 enum det_size { 80 DET_SIZE_DEFAULT = 0, 81 DET_SIZE_192KB = 3, 82 DET_SIZE_256KB = 4, 83 DET_SIZE_320KB = 5, 84 DET_SIZE_384KB = 6 85 }; 86 87 88 struct dc_plane_cap { 89 enum dc_plane_type type; 90 uint32_t blends_with_above : 1; 91 uint32_t blends_with_below : 1; 92 uint32_t per_pixel_alpha : 1; 93 struct { 94 uint32_t argb8888 : 1; 95 uint32_t nv12 : 1; 96 uint32_t fp16 : 1; 97 uint32_t p010 : 1; 98 uint32_t ayuv : 1; 99 } pixel_format_support; 100 // max upscaling factor x1000 101 // upscaling factors are always >= 1 102 // for example, 1080p -> 8K is 4.0, or 4000 raw value 103 struct { 104 uint32_t argb8888; 105 uint32_t nv12; 106 uint32_t fp16; 107 } max_upscale_factor; 108 // max downscale factor x1000 109 // downscale factors are always <= 1 110 // for example, 8K -> 1080p is 0.25, or 250 raw value 111 struct { 112 uint32_t argb8888; 113 uint32_t nv12; 114 uint32_t fp16; 115 } max_downscale_factor; 116 // minimal width/height 117 uint32_t min_width; 118 uint32_t min_height; 119 }; 120 121 // Color management caps (DPP and MPC) 122 struct rom_curve_caps { 123 uint16_t srgb : 1; 124 uint16_t bt2020 : 1; 125 uint16_t gamma2_2 : 1; 126 uint16_t pq : 1; 127 uint16_t hlg : 1; 128 }; 129 130 struct dpp_color_caps { 131 uint16_t dcn_arch : 1; // all DCE generations treated the same 132 // input lut is different than most LUTs, just plain 256-entry lookup 133 uint16_t input_lut_shared : 1; // shared with DGAM 134 uint16_t icsc : 1; 135 uint16_t dgam_ram : 1; 136 uint16_t post_csc : 1; // before gamut remap 137 uint16_t gamma_corr : 1; 138 139 // hdr_mult and gamut remap always available in DPP (in that order) 140 // 3d lut implies shaper LUT, 141 // it may be shared with MPC - check MPC:shared_3d_lut flag 142 uint16_t hw_3d_lut : 1; 143 uint16_t ogam_ram : 1; // blnd gam 144 uint16_t ocsc : 1; 145 uint16_t dgam_rom_for_yuv : 1; 146 struct rom_curve_caps dgam_rom_caps; 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct mpc_color_caps { 151 uint16_t gamut_remap : 1; 152 uint16_t ogam_ram : 1; 153 uint16_t ocsc : 1; 154 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 155 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 156 157 struct rom_curve_caps ogam_rom_caps; 158 }; 159 160 struct dc_color_caps { 161 struct dpp_color_caps dpp; 162 struct mpc_color_caps mpc; 163 }; 164 165 struct dc_dmub_caps { 166 bool psr; 167 bool mclk_sw; 168 }; 169 170 struct dc_caps { 171 uint32_t max_streams; 172 uint32_t max_links; 173 uint32_t max_audios; 174 uint32_t max_slave_planes; 175 uint32_t max_slave_yuv_planes; 176 uint32_t max_slave_rgb_planes; 177 uint32_t max_planes; 178 uint32_t max_downscale_ratio; 179 uint32_t i2c_speed_in_khz; 180 uint32_t i2c_speed_in_khz_hdcp; 181 uint32_t dmdata_alloc_size; 182 unsigned int max_cursor_size; 183 unsigned int max_video_width; 184 unsigned int min_horizontal_blanking_period; 185 int linear_pitch_alignment; 186 bool dcc_const_color; 187 bool dynamic_audio; 188 bool is_apu; 189 bool dual_link_dvi; 190 bool post_blend_color_processing; 191 bool force_dp_tps4_for_cp2520; 192 bool disable_dp_clk_share; 193 bool psp_setup_panel_mode; 194 bool extended_aux_timeout_support; 195 bool dmcub_support; 196 bool zstate_support; 197 uint32_t num_of_internal_disp; 198 enum dp_protocol_version max_dp_protocol_version; 199 unsigned int mall_size_per_mem_channel; 200 unsigned int mall_size_total; 201 unsigned int cursor_cache_size; 202 struct dc_plane_cap planes[MAX_PLANES]; 203 struct dc_color_caps color; 204 struct dc_dmub_caps dmub_caps; 205 bool dp_hpo; 206 bool dp_hdmi21_pcon_support; 207 bool edp_dsc_support; 208 bool vbios_lttpr_aware; 209 bool vbios_lttpr_enable; 210 uint32_t max_otg_num; 211 uint32_t max_cab_allocation_bytes; 212 uint32_t cache_line_size; 213 uint32_t cache_num_ways; 214 uint16_t subvp_fw_processing_delay_us; 215 uint16_t subvp_prefetch_end_to_mall_start_us; 216 uint16_t subvp_pstate_allow_width_us; 217 uint16_t subvp_vertical_int_margin_us; 218 bool seamless_odm; 219 }; 220 221 struct dc_bug_wa { 222 bool no_connect_phy_config; 223 bool dedcn20_305_wa; 224 bool skip_clock_update; 225 bool lt_early_cr_pattern; 226 }; 227 228 struct dc_dcc_surface_param { 229 struct dc_size surface_size; 230 enum surface_pixel_format format; 231 enum swizzle_mode_values swizzle_mode; 232 enum dc_scan_direction scan; 233 }; 234 235 struct dc_dcc_setting { 236 unsigned int max_compressed_blk_size; 237 unsigned int max_uncompressed_blk_size; 238 bool independent_64b_blks; 239 //These bitfields to be used starting with DCN 240 struct { 241 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 242 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 243 uint32_t dcc_256_128_128 : 1; //available starting with DCN 244 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 245 } dcc_controls; 246 }; 247 248 struct dc_surface_dcc_cap { 249 union { 250 struct { 251 struct dc_dcc_setting rgb; 252 } grph; 253 254 struct { 255 struct dc_dcc_setting luma; 256 struct dc_dcc_setting chroma; 257 } video; 258 }; 259 260 bool capable; 261 bool const_color_support; 262 }; 263 264 struct dc_static_screen_params { 265 struct { 266 bool force_trigger; 267 bool cursor_update; 268 bool surface_update; 269 bool overlay_update; 270 } triggers; 271 unsigned int num_frames; 272 }; 273 274 275 /* Surface update type is used by dc_update_surfaces_and_stream 276 * The update type is determined at the very beginning of the function based 277 * on parameters passed in and decides how much programming (or updating) is 278 * going to be done during the call. 279 * 280 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 281 * logical calculations or hardware register programming. This update MUST be 282 * ISR safe on windows. Currently fast update will only be used to flip surface 283 * address. 284 * 285 * UPDATE_TYPE_MED is used for slower updates which require significant hw 286 * re-programming however do not affect bandwidth consumption or clock 287 * requirements. At present, this is the level at which front end updates 288 * that do not require us to run bw_calcs happen. These are in/out transfer func 289 * updates, viewport offset changes, recout size changes and pixel depth changes. 290 * This update can be done at ISR, but we want to minimize how often this happens. 291 * 292 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 293 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 294 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 295 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 296 * a full update. This cannot be done at ISR level and should be a rare event. 297 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 298 * underscan we don't expect to see this call at all. 299 */ 300 301 enum surface_update_type { 302 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 303 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 304 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 305 }; 306 307 /* Forward declaration*/ 308 struct dc; 309 struct dc_plane_state; 310 struct dc_state; 311 312 313 struct dc_cap_funcs { 314 bool (*get_dcc_compression_cap)(const struct dc *dc, 315 const struct dc_dcc_surface_param *input, 316 struct dc_surface_dcc_cap *output); 317 }; 318 319 struct link_training_settings; 320 321 union allow_lttpr_non_transparent_mode { 322 struct { 323 bool DP1_4A : 1; 324 bool DP2_0 : 1; 325 } bits; 326 unsigned char raw; 327 }; 328 329 /* Structure to hold configuration flags set by dm at dc creation. */ 330 struct dc_config { 331 bool gpu_vm_support; 332 bool disable_disp_pll_sharing; 333 bool fbc_support; 334 bool disable_fractional_pwm; 335 bool allow_seamless_boot_optimization; 336 bool seamless_boot_edp_requested; 337 bool edp_not_connected; 338 bool edp_no_power_sequencing; 339 bool force_enum_edp; 340 bool forced_clocks; 341 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 342 bool multi_mon_pp_mclk_switch; 343 bool disable_dmcu; 344 bool enable_4to1MPC; 345 bool enable_windowed_mpo_odm; 346 uint32_t allow_edp_hotplug_detection; 347 bool clamp_min_dcfclk; 348 uint64_t vblank_alignment_dto_params; 349 uint8_t vblank_alignment_max_frame_time_diff; 350 bool is_asymmetric_memory; 351 bool is_single_rank_dimm; 352 bool use_pipe_ctx_sync_logic; 353 bool ignore_dpref_ss; 354 bool enable_mipi_converter_optimization; 355 }; 356 357 enum visual_confirm { 358 VISUAL_CONFIRM_DISABLE = 0, 359 VISUAL_CONFIRM_SURFACE = 1, 360 VISUAL_CONFIRM_HDR = 2, 361 VISUAL_CONFIRM_MPCTREE = 4, 362 VISUAL_CONFIRM_PSR = 5, 363 VISUAL_CONFIRM_SWAPCHAIN = 6, 364 VISUAL_CONFIRM_FAMS = 7, 365 VISUAL_CONFIRM_SWIZZLE = 9, 366 }; 367 368 enum dc_psr_power_opts { 369 psr_power_opt_invalid = 0x0, 370 psr_power_opt_smu_opt_static_screen = 0x1, 371 psr_power_opt_z10_static_screen = 0x10, 372 psr_power_opt_ds_disable_allow = 0x100, 373 }; 374 375 enum dml_hostvm_override_opts { 376 DML_HOSTVM_NO_OVERRIDE = 0x0, 377 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 378 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 379 }; 380 381 enum dcc_option { 382 DCC_ENABLE = 0, 383 DCC_DISABLE = 1, 384 DCC_HALF_REQ_DISALBE = 2, 385 }; 386 387 enum pipe_split_policy { 388 MPC_SPLIT_DYNAMIC = 0, 389 MPC_SPLIT_AVOID = 1, 390 MPC_SPLIT_AVOID_MULT_DISP = 2, 391 }; 392 393 enum wm_report_mode { 394 WM_REPORT_DEFAULT = 0, 395 WM_REPORT_OVERRIDE = 1, 396 }; 397 enum dtm_pstate{ 398 dtm_level_p0 = 0,/*highest voltage*/ 399 dtm_level_p1, 400 dtm_level_p2, 401 dtm_level_p3, 402 dtm_level_p4,/*when active_display_count = 0*/ 403 }; 404 405 enum dcn_pwr_state { 406 DCN_PWR_STATE_UNKNOWN = -1, 407 DCN_PWR_STATE_MISSION_MODE = 0, 408 DCN_PWR_STATE_LOW_POWER = 3, 409 }; 410 411 enum dcn_zstate_support_state { 412 DCN_ZSTATE_SUPPORT_UNKNOWN, 413 DCN_ZSTATE_SUPPORT_ALLOW, 414 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 415 DCN_ZSTATE_SUPPORT_DISALLOW, 416 }; 417 /* 418 * For any clocks that may differ per pipe 419 * only the max is stored in this structure 420 */ 421 struct dc_clocks { 422 int dispclk_khz; 423 int actual_dispclk_khz; 424 int dppclk_khz; 425 int actual_dppclk_khz; 426 int disp_dpp_voltage_level_khz; 427 int dcfclk_khz; 428 int socclk_khz; 429 int dcfclk_deep_sleep_khz; 430 int fclk_khz; 431 int phyclk_khz; 432 int dramclk_khz; 433 bool p_state_change_support; 434 enum dcn_zstate_support_state zstate_support; 435 bool dtbclk_en; 436 int ref_dtbclk_khz; 437 bool fclk_p_state_change_support; 438 enum dcn_pwr_state pwr_state; 439 /* 440 * Elements below are not compared for the purposes of 441 * optimization required 442 */ 443 bool prev_p_state_change_support; 444 bool fclk_prev_p_state_change_support; 445 int num_ways; 446 bool fw_based_mclk_switching; 447 bool fw_based_mclk_switching_shut_down; 448 int prev_num_ways; 449 enum dtm_pstate dtm_level; 450 int max_supported_dppclk_khz; 451 int max_supported_dispclk_khz; 452 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 453 int bw_dispclk_khz; 454 }; 455 456 struct dc_bw_validation_profile { 457 bool enable; 458 459 unsigned long long total_ticks; 460 unsigned long long voltage_level_ticks; 461 unsigned long long watermark_ticks; 462 unsigned long long rq_dlg_ticks; 463 464 unsigned long long total_count; 465 unsigned long long skip_fast_count; 466 unsigned long long skip_pass_count; 467 unsigned long long skip_fail_count; 468 }; 469 470 #define BW_VAL_TRACE_SETUP() \ 471 unsigned long long end_tick = 0; \ 472 unsigned long long voltage_level_tick = 0; \ 473 unsigned long long watermark_tick = 0; \ 474 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 475 dm_get_timestamp(dc->ctx) : 0 476 477 #define BW_VAL_TRACE_COUNT() \ 478 if (dc->debug.bw_val_profile.enable) \ 479 dc->debug.bw_val_profile.total_count++ 480 481 #define BW_VAL_TRACE_SKIP(status) \ 482 if (dc->debug.bw_val_profile.enable) { \ 483 if (!voltage_level_tick) \ 484 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 485 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 486 } 487 488 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 489 if (dc->debug.bw_val_profile.enable) \ 490 voltage_level_tick = dm_get_timestamp(dc->ctx) 491 492 #define BW_VAL_TRACE_END_WATERMARKS() \ 493 if (dc->debug.bw_val_profile.enable) \ 494 watermark_tick = dm_get_timestamp(dc->ctx) 495 496 #define BW_VAL_TRACE_FINISH() \ 497 if (dc->debug.bw_val_profile.enable) { \ 498 end_tick = dm_get_timestamp(dc->ctx); \ 499 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 500 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 501 if (watermark_tick) { \ 502 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 503 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 504 } \ 505 } 506 507 union mem_low_power_enable_options { 508 struct { 509 bool vga: 1; 510 bool i2c: 1; 511 bool dmcu: 1; 512 bool dscl: 1; 513 bool cm: 1; 514 bool mpc: 1; 515 bool optc: 1; 516 bool vpg: 1; 517 bool afmt: 1; 518 } bits; 519 uint32_t u32All; 520 }; 521 522 union root_clock_optimization_options { 523 struct { 524 bool dpp: 1; 525 bool dsc: 1; 526 bool hdmistream: 1; 527 bool hdmichar: 1; 528 bool dpstream: 1; 529 bool symclk32_se: 1; 530 bool symclk32_le: 1; 531 bool symclk_fe: 1; 532 bool physymclk: 1; 533 bool dpiasymclk: 1; 534 uint32_t reserved: 22; 535 } bits; 536 uint32_t u32All; 537 }; 538 539 union dpia_debug_options { 540 struct { 541 uint32_t disable_dpia:1; /* bit 0 */ 542 uint32_t force_non_lttpr:1; /* bit 1 */ 543 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 544 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 545 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 546 uint32_t reserved:27; 547 } bits; 548 uint32_t raw; 549 }; 550 551 /* AUX wake work around options 552 * 0: enable/disable work around 553 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 554 * 15-2: reserved 555 * 31-16: timeout in ms 556 */ 557 union aux_wake_wa_options { 558 struct { 559 uint32_t enable_wa : 1; 560 uint32_t use_default_timeout : 1; 561 uint32_t rsvd: 14; 562 uint32_t timeout_ms : 16; 563 } bits; 564 uint32_t raw; 565 }; 566 567 struct dc_debug_data { 568 uint32_t ltFailCount; 569 uint32_t i2cErrorCount; 570 uint32_t auxErrorCount; 571 }; 572 573 struct dc_phy_addr_space_config { 574 struct { 575 uint64_t start_addr; 576 uint64_t end_addr; 577 uint64_t fb_top; 578 uint64_t fb_offset; 579 uint64_t fb_base; 580 uint64_t agp_top; 581 uint64_t agp_bot; 582 uint64_t agp_base; 583 } system_aperture; 584 585 struct { 586 uint64_t page_table_start_addr; 587 uint64_t page_table_end_addr; 588 uint64_t page_table_base_addr; 589 bool base_addr_is_mc_addr; 590 } gart_config; 591 592 bool valid; 593 bool is_hvm_enabled; 594 uint64_t page_table_default_page_addr; 595 }; 596 597 struct dc_virtual_addr_space_config { 598 uint64_t page_table_base_addr; 599 uint64_t page_table_start_addr; 600 uint64_t page_table_end_addr; 601 uint32_t page_table_block_size_in_bytes; 602 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 603 }; 604 605 struct dc_bounding_box_overrides { 606 int sr_exit_time_ns; 607 int sr_enter_plus_exit_time_ns; 608 int urgent_latency_ns; 609 int percent_of_ideal_drambw; 610 int dram_clock_change_latency_ns; 611 int dummy_clock_change_latency_ns; 612 /* This forces a hard min on the DCFCLK we use 613 * for DML. Unlike the debug option for forcing 614 * DCFCLK, this override affects watermark calculations 615 */ 616 int min_dcfclk_mhz; 617 }; 618 619 struct dc_state; 620 struct resource_pool; 621 struct dce_hwseq; 622 623 struct dc_debug_options { 624 bool native422_support; 625 bool disable_dsc; 626 enum visual_confirm visual_confirm; 627 int visual_confirm_rect_height; 628 629 bool sanity_checks; 630 bool max_disp_clk; 631 bool surface_trace; 632 bool timing_trace; 633 bool clock_trace; 634 bool validation_trace; 635 bool bandwidth_calcs_trace; 636 int max_downscale_src_width; 637 638 /* stutter efficiency related */ 639 bool disable_stutter; 640 bool use_max_lb; 641 enum dcc_option disable_dcc; 642 enum pipe_split_policy pipe_split_policy; 643 bool force_single_disp_pipe_split; 644 bool voltage_align_fclk; 645 bool disable_min_fclk; 646 647 bool disable_dfs_bypass; 648 bool disable_dpp_power_gate; 649 bool disable_hubp_power_gate; 650 bool disable_dsc_power_gate; 651 int dsc_min_slice_height_override; 652 int dsc_bpp_increment_div; 653 bool disable_pplib_wm_range; 654 enum wm_report_mode pplib_wm_report_mode; 655 unsigned int min_disp_clk_khz; 656 unsigned int min_dpp_clk_khz; 657 unsigned int min_dram_clk_khz; 658 int sr_exit_time_dpm0_ns; 659 int sr_enter_plus_exit_time_dpm0_ns; 660 int sr_exit_time_ns; 661 int sr_enter_plus_exit_time_ns; 662 int urgent_latency_ns; 663 uint32_t underflow_assert_delay_us; 664 int percent_of_ideal_drambw; 665 int dram_clock_change_latency_ns; 666 bool optimized_watermark; 667 int always_scale; 668 bool disable_pplib_clock_request; 669 bool disable_clock_gate; 670 bool disable_mem_low_power; 671 bool pstate_enabled; 672 bool disable_dmcu; 673 bool disable_psr; 674 bool force_abm_enable; 675 bool disable_stereo_support; 676 bool vsr_support; 677 bool performance_trace; 678 bool az_endpoint_mute_only; 679 bool always_use_regamma; 680 bool recovery_enabled; 681 bool avoid_vbios_exec_table; 682 bool scl_reset_length10; 683 bool hdmi20_disable; 684 bool skip_detection_link_training; 685 uint32_t edid_read_retry_times; 686 unsigned int force_odm_combine; //bit vector based on otg inst 687 unsigned int seamless_boot_odm_combine; 688 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 689 bool disable_z9_mpc; 690 unsigned int force_fclk_khz; 691 bool enable_tri_buf; 692 bool dmub_offload_enabled; 693 bool dmcub_emulation; 694 bool disable_idle_power_optimizations; 695 unsigned int mall_size_override; 696 unsigned int mall_additional_timer_percent; 697 bool mall_error_as_fatal; 698 bool dmub_command_table; /* for testing only */ 699 struct dc_bw_validation_profile bw_val_profile; 700 bool disable_fec; 701 bool disable_48mhz_pwrdwn; 702 /* This forces a hard min on the DCFCLK requested to SMU/PP 703 * watermarks are not affected. 704 */ 705 unsigned int force_min_dcfclk_mhz; 706 int dwb_fi_phase; 707 bool disable_timing_sync; 708 bool cm_in_bypass; 709 int force_clock_mode;/*every mode change.*/ 710 711 bool disable_dram_clock_change_vactive_support; 712 bool validate_dml_output; 713 bool enable_dmcub_surface_flip; 714 bool usbc_combo_phy_reset_wa; 715 bool disable_dsc_edp; 716 unsigned int force_dsc_edp_policy; 717 bool enable_dram_clock_change_one_display_vactive; 718 /* TODO - remove once tested */ 719 bool legacy_dp2_lt; 720 bool set_mst_en_for_sst; 721 bool disable_uhbr; 722 bool force_dp2_lt_fallback_method; 723 bool ignore_cable_id; 724 union mem_low_power_enable_options enable_mem_low_power; 725 union root_clock_optimization_options root_clock_optimization; 726 bool hpo_optimization; 727 bool force_vblank_alignment; 728 729 /* Enable dmub aux for legacy ddc */ 730 bool enable_dmub_aux_for_legacy_ddc; 731 bool disable_fams; 732 bool optimize_edp_link_rate; /* eDP ILR */ 733 /* FEC/PSR1 sequence enable delay in 100us */ 734 uint8_t fec_enable_delay_in100us; 735 bool enable_driver_sequence_debug; 736 enum det_size crb_alloc_policy; 737 int crb_alloc_policy_min_disp_count; 738 bool disable_z10; 739 bool enable_z9_disable_interface; 740 bool enable_sw_cntl_psr; 741 union dpia_debug_options dpia_debug; 742 bool disable_fixed_vs_aux_timeout_wa; 743 bool force_disable_subvp; 744 bool force_subvp_mclk_switch; 745 bool force_usr_allow; 746 /* uses value at boot and disables switch */ 747 bool disable_dtb_ref_clk_switch; 748 uint32_t fixed_vs_aux_delay_config_wa; 749 bool extended_blank_optimization; 750 union aux_wake_wa_options aux_wake_wa; 751 uint32_t mst_start_top_delay; 752 uint8_t psr_power_use_phy_fsm; 753 enum dml_hostvm_override_opts dml_hostvm_override; 754 bool use_legacy_soc_bb_mechanism; 755 bool exit_idle_opt_for_cursor_updates; 756 bool enable_single_display_2to1_odm_policy; 757 bool enable_dp_dig_pixel_rate_div_policy; 758 }; 759 760 struct gpu_info_soc_bounding_box_v1_0; 761 struct dc { 762 struct dc_debug_options debug; 763 struct dc_versions versions; 764 struct dc_caps caps; 765 struct dc_cap_funcs cap_funcs; 766 struct dc_config config; 767 struct dc_bounding_box_overrides bb_overrides; 768 struct dc_bug_wa work_arounds; 769 struct dc_context *ctx; 770 struct dc_phy_addr_space_config vm_pa_config; 771 772 uint8_t link_count; 773 struct dc_link *links[MAX_PIPES * 2]; 774 775 struct dc_state *current_state; 776 struct resource_pool *res_pool; 777 778 struct clk_mgr *clk_mgr; 779 780 /* Display Engine Clock levels */ 781 struct dm_pp_clock_levels sclk_lvls; 782 783 /* Inputs into BW and WM calculations. */ 784 struct bw_calcs_dceip *bw_dceip; 785 struct bw_calcs_vbios *bw_vbios; 786 struct dcn_soc_bounding_box *dcn_soc; 787 struct dcn_ip_params *dcn_ip; 788 struct display_mode_lib dml; 789 790 /* HW functions */ 791 struct hw_sequencer_funcs hwss; 792 struct dce_hwseq *hwseq; 793 794 /* Require to optimize clocks and bandwidth for added/removed planes */ 795 bool optimized_required; 796 bool wm_optimized_required; 797 bool idle_optimizations_allowed; 798 bool enable_c20_dtm_b0; 799 800 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 801 802 /* FBC compressor */ 803 struct compressor *fbc_compressor; 804 805 struct dc_debug_data debug_data; 806 struct dpcd_vendor_signature vendor_signature; 807 808 const char *build_id; 809 struct vm_helper *vm_helper; 810 811 uint32_t *dcn_reg_offsets; 812 uint32_t *nbio_reg_offsets; 813 }; 814 815 enum frame_buffer_mode { 816 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 817 FRAME_BUFFER_MODE_ZFB_ONLY, 818 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 819 } ; 820 821 struct dchub_init_data { 822 int64_t zfb_phys_addr_base; 823 int64_t zfb_mc_base_addr; 824 uint64_t zfb_size_in_byte; 825 enum frame_buffer_mode fb_mode; 826 bool dchub_initialzied; 827 bool dchub_info_valid; 828 }; 829 830 struct dc_init_data { 831 struct hw_asic_id asic_id; 832 void *driver; /* ctx */ 833 struct cgs_device *cgs_device; 834 struct dc_bounding_box_overrides bb_overrides; 835 836 int num_virtual_links; 837 /* 838 * If 'vbios_override' not NULL, it will be called instead 839 * of the real VBIOS. Intended use is Diagnostics on FPGA. 840 */ 841 struct dc_bios *vbios_override; 842 enum dce_environment dce_environment; 843 844 struct dmub_offload_funcs *dmub_if; 845 struct dc_reg_helper_state *dmub_offload; 846 847 struct dc_config flags; 848 uint64_t log_mask; 849 850 struct dpcd_vendor_signature vendor_signature; 851 bool force_smu_not_present; 852 /* 853 * IP offset for run time initializaion of register addresses 854 * 855 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 856 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 857 * before them. 858 */ 859 uint32_t *dcn_reg_offsets; 860 uint32_t *nbio_reg_offsets; 861 }; 862 863 struct dc_callback_init { 864 #ifdef CONFIG_DRM_AMD_DC_HDCP 865 struct cp_psp cp_psp; 866 #else 867 uint8_t reserved; 868 #endif 869 }; 870 871 struct dc *dc_create(const struct dc_init_data *init_params); 872 void dc_hardware_init(struct dc *dc); 873 874 int dc_get_vmid_use_vector(struct dc *dc); 875 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 876 /* Returns the number of vmids supported */ 877 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 878 void dc_init_callbacks(struct dc *dc, 879 const struct dc_callback_init *init_params); 880 void dc_deinit_callbacks(struct dc *dc); 881 void dc_destroy(struct dc **dc); 882 883 /******************************************************************************* 884 * Surface Interfaces 885 ******************************************************************************/ 886 887 enum { 888 TRANSFER_FUNC_POINTS = 1025 889 }; 890 891 struct dc_hdr_static_metadata { 892 /* display chromaticities and white point in units of 0.00001 */ 893 unsigned int chromaticity_green_x; 894 unsigned int chromaticity_green_y; 895 unsigned int chromaticity_blue_x; 896 unsigned int chromaticity_blue_y; 897 unsigned int chromaticity_red_x; 898 unsigned int chromaticity_red_y; 899 unsigned int chromaticity_white_point_x; 900 unsigned int chromaticity_white_point_y; 901 902 uint32_t min_luminance; 903 uint32_t max_luminance; 904 uint32_t maximum_content_light_level; 905 uint32_t maximum_frame_average_light_level; 906 }; 907 908 enum dc_transfer_func_type { 909 TF_TYPE_PREDEFINED, 910 TF_TYPE_DISTRIBUTED_POINTS, 911 TF_TYPE_BYPASS, 912 TF_TYPE_HWPWL 913 }; 914 915 struct dc_transfer_func_distributed_points { 916 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 917 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 918 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 919 920 uint16_t end_exponent; 921 uint16_t x_point_at_y1_red; 922 uint16_t x_point_at_y1_green; 923 uint16_t x_point_at_y1_blue; 924 }; 925 926 enum dc_transfer_func_predefined { 927 TRANSFER_FUNCTION_SRGB, 928 TRANSFER_FUNCTION_BT709, 929 TRANSFER_FUNCTION_PQ, 930 TRANSFER_FUNCTION_LINEAR, 931 TRANSFER_FUNCTION_UNITY, 932 TRANSFER_FUNCTION_HLG, 933 TRANSFER_FUNCTION_HLG12, 934 TRANSFER_FUNCTION_GAMMA22, 935 TRANSFER_FUNCTION_GAMMA24, 936 TRANSFER_FUNCTION_GAMMA26 937 }; 938 939 940 struct dc_transfer_func { 941 struct kref refcount; 942 enum dc_transfer_func_type type; 943 enum dc_transfer_func_predefined tf; 944 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 945 uint32_t sdr_ref_white_level; 946 union { 947 struct pwl_params pwl; 948 struct dc_transfer_func_distributed_points tf_pts; 949 }; 950 }; 951 952 953 union dc_3dlut_state { 954 struct { 955 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 956 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 957 uint32_t rmu_mux_num:3; /*index of mux to use*/ 958 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 959 uint32_t mpc_rmu1_mux:4; 960 uint32_t mpc_rmu2_mux:4; 961 uint32_t reserved:15; 962 } bits; 963 uint32_t raw; 964 }; 965 966 967 struct dc_3dlut { 968 struct kref refcount; 969 struct tetrahedral_params lut_3d; 970 struct fixed31_32 hdr_multiplier; 971 union dc_3dlut_state state; 972 }; 973 /* 974 * This structure is filled in by dc_surface_get_status and contains 975 * the last requested address and the currently active address so the called 976 * can determine if there are any outstanding flips 977 */ 978 struct dc_plane_status { 979 struct dc_plane_address requested_address; 980 struct dc_plane_address current_address; 981 bool is_flip_pending; 982 bool is_right_eye; 983 }; 984 985 union surface_update_flags { 986 987 struct { 988 uint32_t addr_update:1; 989 /* Medium updates */ 990 uint32_t dcc_change:1; 991 uint32_t color_space_change:1; 992 uint32_t horizontal_mirror_change:1; 993 uint32_t per_pixel_alpha_change:1; 994 uint32_t global_alpha_change:1; 995 uint32_t hdr_mult:1; 996 uint32_t rotation_change:1; 997 uint32_t swizzle_change:1; 998 uint32_t scaling_change:1; 999 uint32_t position_change:1; 1000 uint32_t in_transfer_func_change:1; 1001 uint32_t input_csc_change:1; 1002 uint32_t coeff_reduction_change:1; 1003 uint32_t output_tf_change:1; 1004 uint32_t pixel_format_change:1; 1005 uint32_t plane_size_change:1; 1006 uint32_t gamut_remap_change:1; 1007 1008 /* Full updates */ 1009 uint32_t new_plane:1; 1010 uint32_t bpp_change:1; 1011 uint32_t gamma_change:1; 1012 uint32_t bandwidth_change:1; 1013 uint32_t clock_change:1; 1014 uint32_t stereo_format_change:1; 1015 uint32_t lut_3d:1; 1016 uint32_t full_update:1; 1017 } bits; 1018 1019 uint32_t raw; 1020 }; 1021 1022 struct dc_plane_state { 1023 struct dc_plane_address address; 1024 struct dc_plane_flip_time time; 1025 bool triplebuffer_flips; 1026 struct scaling_taps scaling_quality; 1027 struct rect src_rect; 1028 struct rect dst_rect; 1029 struct rect clip_rect; 1030 1031 struct plane_size plane_size; 1032 union dc_tiling_info tiling_info; 1033 1034 struct dc_plane_dcc_param dcc; 1035 1036 struct dc_gamma *gamma_correction; 1037 struct dc_transfer_func *in_transfer_func; 1038 struct dc_bias_and_scale *bias_and_scale; 1039 struct dc_csc_transform input_csc_color_matrix; 1040 struct fixed31_32 coeff_reduction_factor; 1041 struct fixed31_32 hdr_mult; 1042 struct colorspace_transform gamut_remap_matrix; 1043 1044 // TODO: No longer used, remove 1045 struct dc_hdr_static_metadata hdr_static_ctx; 1046 1047 enum dc_color_space color_space; 1048 1049 struct dc_3dlut *lut3d_func; 1050 struct dc_transfer_func *in_shaper_func; 1051 struct dc_transfer_func *blend_tf; 1052 1053 struct dc_transfer_func *gamcor_tf; 1054 enum surface_pixel_format format; 1055 enum dc_rotation_angle rotation; 1056 enum plane_stereo_format stereo_format; 1057 1058 bool is_tiling_rotated; 1059 bool per_pixel_alpha; 1060 bool pre_multiplied_alpha; 1061 bool global_alpha; 1062 int global_alpha_value; 1063 bool visible; 1064 bool flip_immediate; 1065 bool horizontal_mirror; 1066 int layer_index; 1067 1068 union surface_update_flags update_flags; 1069 bool flip_int_enabled; 1070 bool skip_manual_trigger; 1071 1072 /* private to DC core */ 1073 struct dc_plane_status status; 1074 struct dc_context *ctx; 1075 1076 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1077 bool force_full_update; 1078 1079 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1080 1081 /* private to dc_surface.c */ 1082 enum dc_irq_source irq_source; 1083 struct kref refcount; 1084 }; 1085 1086 struct dc_plane_info { 1087 struct plane_size plane_size; 1088 union dc_tiling_info tiling_info; 1089 struct dc_plane_dcc_param dcc; 1090 enum surface_pixel_format format; 1091 enum dc_rotation_angle rotation; 1092 enum plane_stereo_format stereo_format; 1093 enum dc_color_space color_space; 1094 bool horizontal_mirror; 1095 bool visible; 1096 bool per_pixel_alpha; 1097 bool pre_multiplied_alpha; 1098 bool global_alpha; 1099 int global_alpha_value; 1100 bool input_csc_enabled; 1101 int layer_index; 1102 }; 1103 1104 struct dc_scaling_info { 1105 struct rect src_rect; 1106 struct rect dst_rect; 1107 struct rect clip_rect; 1108 struct scaling_taps scaling_quality; 1109 }; 1110 1111 struct dc_surface_update { 1112 struct dc_plane_state *surface; 1113 1114 /* isr safe update parameters. null means no updates */ 1115 const struct dc_flip_addrs *flip_addr; 1116 const struct dc_plane_info *plane_info; 1117 const struct dc_scaling_info *scaling_info; 1118 struct fixed31_32 hdr_mult; 1119 /* following updates require alloc/sleep/spin that is not isr safe, 1120 * null means no updates 1121 */ 1122 const struct dc_gamma *gamma; 1123 const struct dc_transfer_func *in_transfer_func; 1124 1125 const struct dc_csc_transform *input_csc_color_matrix; 1126 const struct fixed31_32 *coeff_reduction_factor; 1127 const struct dc_transfer_func *func_shaper; 1128 const struct dc_3dlut *lut3d_func; 1129 const struct dc_transfer_func *blend_tf; 1130 const struct colorspace_transform *gamut_remap_matrix; 1131 }; 1132 1133 /* 1134 * Create a new surface with default parameters; 1135 */ 1136 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1137 const struct dc_plane_status *dc_plane_get_status( 1138 const struct dc_plane_state *plane_state); 1139 1140 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1141 void dc_plane_state_release(struct dc_plane_state *plane_state); 1142 1143 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1144 void dc_gamma_release(struct dc_gamma **dc_gamma); 1145 struct dc_gamma *dc_create_gamma(void); 1146 1147 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1148 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1149 struct dc_transfer_func *dc_create_transfer_func(void); 1150 1151 struct dc_3dlut *dc_create_3dlut_func(void); 1152 void dc_3dlut_func_release(struct dc_3dlut *lut); 1153 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1154 1155 void dc_post_update_surfaces_to_stream( 1156 struct dc *dc); 1157 1158 #include "dc_stream.h" 1159 1160 /* 1161 * Structure to store surface/stream associations for validation 1162 */ 1163 struct dc_validation_set { 1164 struct dc_stream_state *stream; 1165 struct dc_plane_state *plane_states[MAX_SURFACES]; 1166 uint8_t plane_count; 1167 }; 1168 1169 bool dc_validate_boot_timing(const struct dc *dc, 1170 const struct dc_sink *sink, 1171 struct dc_crtc_timing *crtc_timing); 1172 1173 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1174 1175 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1176 1177 bool dc_set_generic_gpio_for_stereo(bool enable, 1178 struct gpio_service *gpio_service); 1179 1180 /* 1181 * fast_validate: we return after determining if we can support the new state, 1182 * but before we populate the programming info 1183 */ 1184 enum dc_status dc_validate_global_state( 1185 struct dc *dc, 1186 struct dc_state *new_ctx, 1187 bool fast_validate); 1188 1189 1190 void dc_resource_state_construct( 1191 const struct dc *dc, 1192 struct dc_state *dst_ctx); 1193 1194 bool dc_acquire_release_mpc_3dlut( 1195 struct dc *dc, bool acquire, 1196 struct dc_stream_state *stream, 1197 struct dc_3dlut **lut, 1198 struct dc_transfer_func **shaper); 1199 1200 void dc_resource_state_copy_construct( 1201 const struct dc_state *src_ctx, 1202 struct dc_state *dst_ctx); 1203 1204 void dc_resource_state_copy_construct_current( 1205 const struct dc *dc, 1206 struct dc_state *dst_ctx); 1207 1208 void dc_resource_state_destruct(struct dc_state *context); 1209 1210 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1211 1212 /* 1213 * TODO update to make it about validation sets 1214 * Set up streams and links associated to drive sinks 1215 * The streams parameter is an absolute set of all active streams. 1216 * 1217 * After this call: 1218 * Phy, Encoder, Timing Generator are programmed and enabled. 1219 * New streams are enabled with blank stream; no memory read. 1220 */ 1221 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1222 1223 struct dc_state *dc_create_state(struct dc *dc); 1224 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1225 void dc_retain_state(struct dc_state *context); 1226 void dc_release_state(struct dc_state *context); 1227 1228 /******************************************************************************* 1229 * Link Interfaces 1230 ******************************************************************************/ 1231 1232 struct dpcd_caps { 1233 union dpcd_rev dpcd_rev; 1234 union max_lane_count max_ln_count; 1235 union max_down_spread max_down_spread; 1236 union dprx_feature dprx_feature; 1237 1238 /* valid only for eDP v1.4 or higher*/ 1239 uint8_t edp_supported_link_rates_count; 1240 enum dc_link_rate edp_supported_link_rates[8]; 1241 1242 /* dongle type (DP converter, CV smart dongle) */ 1243 enum display_dongle_type dongle_type; 1244 bool is_dongle_type_one; 1245 /* branch device or sink device */ 1246 bool is_branch_dev; 1247 /* Dongle's downstream count. */ 1248 union sink_count sink_count; 1249 bool is_mst_capable; 1250 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1251 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1252 struct dc_dongle_caps dongle_caps; 1253 1254 uint32_t sink_dev_id; 1255 int8_t sink_dev_id_str[6]; 1256 int8_t sink_hw_revision; 1257 int8_t sink_fw_revision[2]; 1258 1259 uint32_t branch_dev_id; 1260 int8_t branch_dev_name[6]; 1261 int8_t branch_hw_revision; 1262 int8_t branch_fw_revision[2]; 1263 1264 bool allow_invalid_MSA_timing_param; 1265 bool panel_mode_edp; 1266 bool dpcd_display_control_capable; 1267 bool ext_receiver_cap_field_present; 1268 bool set_power_state_capable_edp; 1269 bool dynamic_backlight_capable_edp; 1270 union dpcd_fec_capability fec_cap; 1271 struct dpcd_dsc_capabilities dsc_caps; 1272 struct dc_lttpr_caps lttpr_caps; 1273 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1274 1275 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1276 union dp_main_line_channel_coding_cap channel_coding_cap; 1277 union dp_sink_video_fallback_formats fallback_formats; 1278 union dp_fec_capability1 fec_cap1; 1279 union dp_cable_id cable_id; 1280 uint8_t edp_rev; 1281 union edp_alpm_caps alpm_caps; 1282 struct edp_psr_info psr_info; 1283 }; 1284 1285 union dpcd_sink_ext_caps { 1286 struct { 1287 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1288 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1289 */ 1290 uint8_t sdr_aux_backlight_control : 1; 1291 uint8_t hdr_aux_backlight_control : 1; 1292 uint8_t reserved_1 : 2; 1293 uint8_t oled : 1; 1294 uint8_t reserved : 3; 1295 } bits; 1296 uint8_t raw; 1297 }; 1298 1299 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1300 union hdcp_rx_caps { 1301 struct { 1302 uint8_t version; 1303 uint8_t reserved; 1304 struct { 1305 uint8_t repeater : 1; 1306 uint8_t hdcp_capable : 1; 1307 uint8_t reserved : 6; 1308 } byte0; 1309 } fields; 1310 uint8_t raw[3]; 1311 }; 1312 1313 union hdcp_bcaps { 1314 struct { 1315 uint8_t HDCP_CAPABLE:1; 1316 uint8_t REPEATER:1; 1317 uint8_t RESERVED:6; 1318 } bits; 1319 uint8_t raw; 1320 }; 1321 1322 struct hdcp_caps { 1323 union hdcp_rx_caps rx_caps; 1324 union hdcp_bcaps bcaps; 1325 }; 1326 #endif 1327 1328 #include "dc_link.h" 1329 1330 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1331 1332 /******************************************************************************* 1333 * Sink Interfaces - A sink corresponds to a display output device 1334 ******************************************************************************/ 1335 1336 struct dc_container_id { 1337 // 128bit GUID in binary form 1338 unsigned char guid[16]; 1339 // 8 byte port ID -> ELD.PortID 1340 unsigned int portId[2]; 1341 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1342 unsigned short manufacturerName; 1343 // 2 byte product code -> ELD.ProductCode 1344 unsigned short productCode; 1345 }; 1346 1347 1348 struct dc_sink_dsc_caps { 1349 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1350 // 'false' if they are sink's DSC caps 1351 bool is_virtual_dpcd_dsc; 1352 #if defined(CONFIG_DRM_AMD_DC_DCN) 1353 // 'true' if MST topology supports DSC passthrough for sink 1354 // 'false' if MST topology does not support DSC passthrough 1355 bool is_dsc_passthrough_supported; 1356 #endif 1357 struct dsc_dec_dpcd_caps dsc_dec_caps; 1358 }; 1359 1360 struct dc_sink_fec_caps { 1361 bool is_rx_fec_supported; 1362 bool is_topology_fec_supported; 1363 }; 1364 1365 /* 1366 * The sink structure contains EDID and other display device properties 1367 */ 1368 struct dc_sink { 1369 enum signal_type sink_signal; 1370 struct dc_edid dc_edid; /* raw edid */ 1371 struct dc_edid_caps edid_caps; /* parse display caps */ 1372 struct dc_container_id *dc_container_id; 1373 uint32_t dongle_max_pix_clk; 1374 void *priv; 1375 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1376 bool converter_disable_audio; 1377 1378 struct dc_sink_dsc_caps dsc_caps; 1379 struct dc_sink_fec_caps fec_caps; 1380 1381 bool is_vsc_sdp_colorimetry_supported; 1382 1383 /* private to DC core */ 1384 struct dc_link *link; 1385 struct dc_context *ctx; 1386 1387 uint32_t sink_id; 1388 1389 /* private to dc_sink.c */ 1390 // refcount must be the last member in dc_sink, since we want the 1391 // sink structure to be logically cloneable up to (but not including) 1392 // refcount 1393 struct kref refcount; 1394 }; 1395 1396 void dc_sink_retain(struct dc_sink *sink); 1397 void dc_sink_release(struct dc_sink *sink); 1398 1399 struct dc_sink_init_data { 1400 enum signal_type sink_signal; 1401 struct dc_link *link; 1402 uint32_t dongle_max_pix_clk; 1403 bool converter_disable_audio; 1404 }; 1405 1406 bool dc_extended_blank_supported(struct dc *dc); 1407 1408 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1409 1410 /* Newer interfaces */ 1411 struct dc_cursor { 1412 struct dc_plane_address address; 1413 struct dc_cursor_attributes attributes; 1414 }; 1415 1416 1417 /******************************************************************************* 1418 * Interrupt interfaces 1419 ******************************************************************************/ 1420 enum dc_irq_source dc_interrupt_to_irq_source( 1421 struct dc *dc, 1422 uint32_t src_id, 1423 uint32_t ext_id); 1424 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1425 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1426 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1427 struct dc *dc, uint32_t link_index); 1428 1429 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1430 1431 /******************************************************************************* 1432 * Power Interfaces 1433 ******************************************************************************/ 1434 1435 void dc_set_power_state( 1436 struct dc *dc, 1437 enum dc_acpi_cm_power_state power_state); 1438 void dc_resume(struct dc *dc); 1439 1440 void dc_power_down_on_boot(struct dc *dc); 1441 1442 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1443 /* 1444 * HDCP Interfaces 1445 */ 1446 enum hdcp_message_status dc_process_hdcp_msg( 1447 enum signal_type signal, 1448 struct dc_link *link, 1449 struct hdcp_protection_message *message_info); 1450 #endif 1451 bool dc_is_dmcu_initialized(struct dc *dc); 1452 1453 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1454 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1455 1456 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1457 struct dc_cursor_attributes *cursor_attr); 1458 1459 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1460 1461 /* set min and max memory clock to lowest and highest DPM level, respectively */ 1462 void dc_unlock_memory_clock_frequency(struct dc *dc); 1463 1464 /* set min memory clock to the min required for current mode, max to maxDPM */ 1465 void dc_lock_memory_clock_frequency(struct dc *dc); 1466 1467 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1468 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1469 1470 /* cleanup on driver unload */ 1471 void dc_hardware_release(struct dc *dc); 1472 1473 /* disables fw based mclk switch */ 1474 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 1475 1476 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1477 void dc_z10_restore(const struct dc *dc); 1478 void dc_z10_save_init(struct dc *dc); 1479 1480 bool dc_is_dmub_outbox_supported(struct dc *dc); 1481 bool dc_enable_dmub_notifications(struct dc *dc); 1482 1483 void dc_enable_dmub_outbox(struct dc *dc); 1484 1485 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1486 uint32_t link_index, 1487 struct aux_payload *payload); 1488 1489 /* Get dc link index from dpia port index */ 1490 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1491 uint8_t dpia_port_index); 1492 1493 bool dc_process_dmub_set_config_async(struct dc *dc, 1494 uint32_t link_index, 1495 struct set_config_cmd_payload *payload, 1496 struct dmub_notification *notify); 1497 1498 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1499 uint32_t link_index, 1500 uint8_t mst_alloc_slots, 1501 uint8_t *mst_slots_in_use); 1502 1503 /******************************************************************************* 1504 * DSC Interfaces 1505 ******************************************************************************/ 1506 #include "dc_dsc.h" 1507 1508 /******************************************************************************* 1509 * Disable acc mode Interfaces 1510 ******************************************************************************/ 1511 void dc_disable_accelerated_mode(struct dc *dc); 1512 1513 #endif /* DC_INTERFACE_H_ */ 1514