1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.222" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /* Display Core Interfaces */ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 // Sizes defined as multiples of 64KB 77 enum det_size { 78 DET_SIZE_DEFAULT = 0, 79 DET_SIZE_192KB = 3, 80 DET_SIZE_256KB = 4, 81 DET_SIZE_320KB = 5, 82 DET_SIZE_384KB = 6 83 }; 84 85 86 struct dc_plane_cap { 87 enum dc_plane_type type; 88 uint32_t blends_with_above : 1; 89 uint32_t blends_with_below : 1; 90 uint32_t per_pixel_alpha : 1; 91 struct { 92 uint32_t argb8888 : 1; 93 uint32_t nv12 : 1; 94 uint32_t fp16 : 1; 95 uint32_t p010 : 1; 96 uint32_t ayuv : 1; 97 } pixel_format_support; 98 // max upscaling factor x1000 99 // upscaling factors are always >= 1 100 // for example, 1080p -> 8K is 4.0, or 4000 raw value 101 struct { 102 uint32_t argb8888; 103 uint32_t nv12; 104 uint32_t fp16; 105 } max_upscale_factor; 106 // max downscale factor x1000 107 // downscale factors are always <= 1 108 // for example, 8K -> 1080p is 0.25, or 250 raw value 109 struct { 110 uint32_t argb8888; 111 uint32_t nv12; 112 uint32_t fp16; 113 } max_downscale_factor; 114 // minimal width/height 115 uint32_t min_width; 116 uint32_t min_height; 117 }; 118 119 /** 120 * DOC: color-management-caps 121 * 122 * **Color management caps (DPP and MPC)** 123 * 124 * Modules/color calculates various color operations which are translated to 125 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 126 * DCN1, every new generation comes with fairly major differences in color 127 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 128 * decide mapping to HW block based on logical capabilities. 129 */ 130 131 /** 132 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 133 * @srgb: RGB color space transfer func 134 * @bt2020: BT.2020 transfer func 135 * @gamma2_2: standard gamma 136 * @pq: perceptual quantizer transfer function 137 * @hlg: hybrid log–gamma transfer function 138 */ 139 struct rom_curve_caps { 140 uint16_t srgb : 1; 141 uint16_t bt2020 : 1; 142 uint16_t gamma2_2 : 1; 143 uint16_t pq : 1; 144 uint16_t hlg : 1; 145 }; 146 147 /** 148 * struct dpp_color_caps - color pipeline capabilities for display pipe and 149 * plane blocks 150 * 151 * @dcn_arch: all DCE generations treated the same 152 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 153 * just plain 256-entry lookup 154 * @icsc: input color space conversion 155 * @dgam_ram: programmable degamma LUT 156 * @post_csc: post color space conversion, before gamut remap 157 * @gamma_corr: degamma correction 158 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 159 * with MPC by setting mpc:shared_3d_lut flag 160 * @ogam_ram: programmable out/blend gamma LUT 161 * @ocsc: output color space conversion 162 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 163 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 164 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 165 * 166 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 167 */ 168 struct dpp_color_caps { 169 uint16_t dcn_arch : 1; 170 uint16_t input_lut_shared : 1; 171 uint16_t icsc : 1; 172 uint16_t dgam_ram : 1; 173 uint16_t post_csc : 1; 174 uint16_t gamma_corr : 1; 175 uint16_t hw_3d_lut : 1; 176 uint16_t ogam_ram : 1; 177 uint16_t ocsc : 1; 178 uint16_t dgam_rom_for_yuv : 1; 179 struct rom_curve_caps dgam_rom_caps; 180 struct rom_curve_caps ogam_rom_caps; 181 }; 182 183 /** 184 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 185 * plane combined blocks 186 * 187 * @gamut_remap: color transformation matrix 188 * @ogam_ram: programmable out gamma LUT 189 * @ocsc: output color space conversion matrix 190 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 191 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 192 * instance 193 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 194 */ 195 struct mpc_color_caps { 196 uint16_t gamut_remap : 1; 197 uint16_t ogam_ram : 1; 198 uint16_t ocsc : 1; 199 uint16_t num_3dluts : 3; 200 uint16_t shared_3d_lut:1; 201 struct rom_curve_caps ogam_rom_caps; 202 }; 203 204 /** 205 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 206 * @dpp: color pipes caps for DPP 207 * @mpc: color pipes caps for MPC 208 */ 209 struct dc_color_caps { 210 struct dpp_color_caps dpp; 211 struct mpc_color_caps mpc; 212 }; 213 214 struct dc_dmub_caps { 215 bool psr; 216 bool mclk_sw; 217 }; 218 219 struct dc_caps { 220 uint32_t max_streams; 221 uint32_t max_links; 222 uint32_t max_audios; 223 uint32_t max_slave_planes; 224 uint32_t max_slave_yuv_planes; 225 uint32_t max_slave_rgb_planes; 226 uint32_t max_planes; 227 uint32_t max_downscale_ratio; 228 uint32_t i2c_speed_in_khz; 229 uint32_t i2c_speed_in_khz_hdcp; 230 uint32_t dmdata_alloc_size; 231 unsigned int max_cursor_size; 232 unsigned int max_video_width; 233 unsigned int min_horizontal_blanking_period; 234 int linear_pitch_alignment; 235 bool dcc_const_color; 236 bool dynamic_audio; 237 bool is_apu; 238 bool dual_link_dvi; 239 bool post_blend_color_processing; 240 bool force_dp_tps4_for_cp2520; 241 bool disable_dp_clk_share; 242 bool psp_setup_panel_mode; 243 bool extended_aux_timeout_support; 244 bool dmcub_support; 245 bool zstate_support; 246 uint32_t num_of_internal_disp; 247 enum dp_protocol_version max_dp_protocol_version; 248 unsigned int mall_size_per_mem_channel; 249 unsigned int mall_size_total; 250 unsigned int cursor_cache_size; 251 struct dc_plane_cap planes[MAX_PLANES]; 252 struct dc_color_caps color; 253 struct dc_dmub_caps dmub_caps; 254 bool dp_hpo; 255 bool dp_hdmi21_pcon_support; 256 bool edp_dsc_support; 257 bool vbios_lttpr_aware; 258 bool vbios_lttpr_enable; 259 uint32_t max_otg_num; 260 uint32_t max_cab_allocation_bytes; 261 uint32_t cache_line_size; 262 uint32_t cache_num_ways; 263 uint16_t subvp_fw_processing_delay_us; 264 uint8_t subvp_drr_max_vblank_margin_us; 265 uint16_t subvp_prefetch_end_to_mall_start_us; 266 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 267 uint16_t subvp_pstate_allow_width_us; 268 uint16_t subvp_vertical_int_margin_us; 269 bool seamless_odm; 270 uint8_t subvp_drr_vblank_start_margin_us; 271 }; 272 273 struct dc_bug_wa { 274 bool no_connect_phy_config; 275 bool dedcn20_305_wa; 276 bool skip_clock_update; 277 bool lt_early_cr_pattern; 278 }; 279 280 struct dc_dcc_surface_param { 281 struct dc_size surface_size; 282 enum surface_pixel_format format; 283 enum swizzle_mode_values swizzle_mode; 284 enum dc_scan_direction scan; 285 }; 286 287 struct dc_dcc_setting { 288 unsigned int max_compressed_blk_size; 289 unsigned int max_uncompressed_blk_size; 290 bool independent_64b_blks; 291 //These bitfields to be used starting with DCN 292 struct { 293 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 294 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 295 uint32_t dcc_256_128_128 : 1; //available starting with DCN 296 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 297 } dcc_controls; 298 }; 299 300 struct dc_surface_dcc_cap { 301 union { 302 struct { 303 struct dc_dcc_setting rgb; 304 } grph; 305 306 struct { 307 struct dc_dcc_setting luma; 308 struct dc_dcc_setting chroma; 309 } video; 310 }; 311 312 bool capable; 313 bool const_color_support; 314 }; 315 316 struct dc_static_screen_params { 317 struct { 318 bool force_trigger; 319 bool cursor_update; 320 bool surface_update; 321 bool overlay_update; 322 } triggers; 323 unsigned int num_frames; 324 }; 325 326 327 /* Surface update type is used by dc_update_surfaces_and_stream 328 * The update type is determined at the very beginning of the function based 329 * on parameters passed in and decides how much programming (or updating) is 330 * going to be done during the call. 331 * 332 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 333 * logical calculations or hardware register programming. This update MUST be 334 * ISR safe on windows. Currently fast update will only be used to flip surface 335 * address. 336 * 337 * UPDATE_TYPE_MED is used for slower updates which require significant hw 338 * re-programming however do not affect bandwidth consumption or clock 339 * requirements. At present, this is the level at which front end updates 340 * that do not require us to run bw_calcs happen. These are in/out transfer func 341 * updates, viewport offset changes, recout size changes and pixel depth changes. 342 * This update can be done at ISR, but we want to minimize how often this happens. 343 * 344 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 345 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 346 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 347 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 348 * a full update. This cannot be done at ISR level and should be a rare event. 349 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 350 * underscan we don't expect to see this call at all. 351 */ 352 353 enum surface_update_type { 354 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 355 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 356 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 357 }; 358 359 /* Forward declaration*/ 360 struct dc; 361 struct dc_plane_state; 362 struct dc_state; 363 364 365 struct dc_cap_funcs { 366 bool (*get_dcc_compression_cap)(const struct dc *dc, 367 const struct dc_dcc_surface_param *input, 368 struct dc_surface_dcc_cap *output); 369 }; 370 371 struct link_training_settings; 372 373 union allow_lttpr_non_transparent_mode { 374 struct { 375 bool DP1_4A : 1; 376 bool DP2_0 : 1; 377 } bits; 378 unsigned char raw; 379 }; 380 381 /* Structure to hold configuration flags set by dm at dc creation. */ 382 struct dc_config { 383 bool gpu_vm_support; 384 bool disable_disp_pll_sharing; 385 bool fbc_support; 386 bool disable_fractional_pwm; 387 bool allow_seamless_boot_optimization; 388 bool seamless_boot_edp_requested; 389 bool edp_not_connected; 390 bool edp_no_power_sequencing; 391 bool force_enum_edp; 392 bool forced_clocks; 393 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 394 bool multi_mon_pp_mclk_switch; 395 bool disable_dmcu; 396 bool enable_4to1MPC; 397 bool enable_windowed_mpo_odm; 398 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 399 uint32_t allow_edp_hotplug_detection; 400 bool clamp_min_dcfclk; 401 uint64_t vblank_alignment_dto_params; 402 uint8_t vblank_alignment_max_frame_time_diff; 403 bool is_asymmetric_memory; 404 bool is_single_rank_dimm; 405 bool is_vmin_only_asic; 406 bool use_pipe_ctx_sync_logic; 407 bool ignore_dpref_ss; 408 bool enable_mipi_converter_optimization; 409 bool use_default_clock_table; 410 bool force_bios_enable_lttpr; 411 uint8_t force_bios_fixed_vs; 412 int sdpif_request_limit_words_per_umc; 413 414 }; 415 416 enum visual_confirm { 417 VISUAL_CONFIRM_DISABLE = 0, 418 VISUAL_CONFIRM_SURFACE = 1, 419 VISUAL_CONFIRM_HDR = 2, 420 VISUAL_CONFIRM_MPCTREE = 4, 421 VISUAL_CONFIRM_PSR = 5, 422 VISUAL_CONFIRM_SWAPCHAIN = 6, 423 VISUAL_CONFIRM_FAMS = 7, 424 VISUAL_CONFIRM_SWIZZLE = 9, 425 VISUAL_CONFIRM_SUBVP = 14, 426 }; 427 428 enum dc_psr_power_opts { 429 psr_power_opt_invalid = 0x0, 430 psr_power_opt_smu_opt_static_screen = 0x1, 431 psr_power_opt_z10_static_screen = 0x10, 432 psr_power_opt_ds_disable_allow = 0x100, 433 }; 434 435 enum dml_hostvm_override_opts { 436 DML_HOSTVM_NO_OVERRIDE = 0x0, 437 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 438 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 439 }; 440 441 enum dcc_option { 442 DCC_ENABLE = 0, 443 DCC_DISABLE = 1, 444 DCC_HALF_REQ_DISALBE = 2, 445 }; 446 447 /** 448 * enum pipe_split_policy - Pipe split strategy supported by DCN 449 * 450 * This enum is used to define the pipe split policy supported by DCN. By 451 * default, DC favors MPC_SPLIT_DYNAMIC. 452 */ 453 enum pipe_split_policy { 454 /** 455 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 456 * pipe in order to bring the best trade-off between performance and 457 * power consumption. This is the recommended option. 458 */ 459 MPC_SPLIT_DYNAMIC = 0, 460 461 /** 462 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 463 * try any sort of split optimization. 464 */ 465 MPC_SPLIT_AVOID = 1, 466 467 /** 468 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 469 * optimize the pipe utilization when using a single display; if the 470 * user connects to a second display, DC will avoid pipe split. 471 */ 472 MPC_SPLIT_AVOID_MULT_DISP = 2, 473 }; 474 475 enum wm_report_mode { 476 WM_REPORT_DEFAULT = 0, 477 WM_REPORT_OVERRIDE = 1, 478 }; 479 enum dtm_pstate{ 480 dtm_level_p0 = 0,/*highest voltage*/ 481 dtm_level_p1, 482 dtm_level_p2, 483 dtm_level_p3, 484 dtm_level_p4,/*when active_display_count = 0*/ 485 }; 486 487 enum dcn_pwr_state { 488 DCN_PWR_STATE_UNKNOWN = -1, 489 DCN_PWR_STATE_MISSION_MODE = 0, 490 DCN_PWR_STATE_LOW_POWER = 3, 491 }; 492 493 enum dcn_zstate_support_state { 494 DCN_ZSTATE_SUPPORT_UNKNOWN, 495 DCN_ZSTATE_SUPPORT_ALLOW, 496 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 497 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 498 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 499 DCN_ZSTATE_SUPPORT_DISALLOW, 500 }; 501 502 /** 503 * struct dc_clocks - DC pipe clocks 504 * 505 * For any clocks that may differ per pipe only the max is stored in this 506 * structure 507 */ 508 struct dc_clocks { 509 int dispclk_khz; 510 int actual_dispclk_khz; 511 int dppclk_khz; 512 int actual_dppclk_khz; 513 int disp_dpp_voltage_level_khz; 514 int dcfclk_khz; 515 int socclk_khz; 516 int dcfclk_deep_sleep_khz; 517 int fclk_khz; 518 int phyclk_khz; 519 int dramclk_khz; 520 bool p_state_change_support; 521 enum dcn_zstate_support_state zstate_support; 522 bool dtbclk_en; 523 int ref_dtbclk_khz; 524 bool fclk_p_state_change_support; 525 enum dcn_pwr_state pwr_state; 526 /* 527 * Elements below are not compared for the purposes of 528 * optimization required 529 */ 530 bool prev_p_state_change_support; 531 bool fclk_prev_p_state_change_support; 532 int num_ways; 533 534 /* 535 * @fw_based_mclk_switching 536 * 537 * DC has a mechanism that leverage the variable refresh rate to switch 538 * memory clock in cases that we have a large latency to achieve the 539 * memory clock change and a short vblank window. DC has some 540 * requirements to enable this feature, and this field describes if the 541 * system support or not such a feature. 542 */ 543 bool fw_based_mclk_switching; 544 bool fw_based_mclk_switching_shut_down; 545 int prev_num_ways; 546 enum dtm_pstate dtm_level; 547 int max_supported_dppclk_khz; 548 int max_supported_dispclk_khz; 549 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 550 int bw_dispclk_khz; 551 }; 552 553 struct dc_bw_validation_profile { 554 bool enable; 555 556 unsigned long long total_ticks; 557 unsigned long long voltage_level_ticks; 558 unsigned long long watermark_ticks; 559 unsigned long long rq_dlg_ticks; 560 561 unsigned long long total_count; 562 unsigned long long skip_fast_count; 563 unsigned long long skip_pass_count; 564 unsigned long long skip_fail_count; 565 }; 566 567 #define BW_VAL_TRACE_SETUP() \ 568 unsigned long long end_tick = 0; \ 569 unsigned long long voltage_level_tick = 0; \ 570 unsigned long long watermark_tick = 0; \ 571 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 572 dm_get_timestamp(dc->ctx) : 0 573 574 #define BW_VAL_TRACE_COUNT() \ 575 if (dc->debug.bw_val_profile.enable) \ 576 dc->debug.bw_val_profile.total_count++ 577 578 #define BW_VAL_TRACE_SKIP(status) \ 579 if (dc->debug.bw_val_profile.enable) { \ 580 if (!voltage_level_tick) \ 581 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 582 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 583 } 584 585 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 586 if (dc->debug.bw_val_profile.enable) \ 587 voltage_level_tick = dm_get_timestamp(dc->ctx) 588 589 #define BW_VAL_TRACE_END_WATERMARKS() \ 590 if (dc->debug.bw_val_profile.enable) \ 591 watermark_tick = dm_get_timestamp(dc->ctx) 592 593 #define BW_VAL_TRACE_FINISH() \ 594 if (dc->debug.bw_val_profile.enable) { \ 595 end_tick = dm_get_timestamp(dc->ctx); \ 596 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 597 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 598 if (watermark_tick) { \ 599 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 600 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 601 } \ 602 } 603 604 union mem_low_power_enable_options { 605 struct { 606 bool vga: 1; 607 bool i2c: 1; 608 bool dmcu: 1; 609 bool dscl: 1; 610 bool cm: 1; 611 bool mpc: 1; 612 bool optc: 1; 613 bool vpg: 1; 614 bool afmt: 1; 615 } bits; 616 uint32_t u32All; 617 }; 618 619 union root_clock_optimization_options { 620 struct { 621 bool dpp: 1; 622 bool dsc: 1; 623 bool hdmistream: 1; 624 bool hdmichar: 1; 625 bool dpstream: 1; 626 bool symclk32_se: 1; 627 bool symclk32_le: 1; 628 bool symclk_fe: 1; 629 bool physymclk: 1; 630 bool dpiasymclk: 1; 631 uint32_t reserved: 22; 632 } bits; 633 uint32_t u32All; 634 }; 635 636 union dpia_debug_options { 637 struct { 638 uint32_t disable_dpia:1; /* bit 0 */ 639 uint32_t force_non_lttpr:1; /* bit 1 */ 640 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 641 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 642 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 643 uint32_t reserved:27; 644 } bits; 645 uint32_t raw; 646 }; 647 648 /* AUX wake work around options 649 * 0: enable/disable work around 650 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 651 * 15-2: reserved 652 * 31-16: timeout in ms 653 */ 654 union aux_wake_wa_options { 655 struct { 656 uint32_t enable_wa : 1; 657 uint32_t use_default_timeout : 1; 658 uint32_t rsvd: 14; 659 uint32_t timeout_ms : 16; 660 } bits; 661 uint32_t raw; 662 }; 663 664 struct dc_debug_data { 665 uint32_t ltFailCount; 666 uint32_t i2cErrorCount; 667 uint32_t auxErrorCount; 668 }; 669 670 struct dc_phy_addr_space_config { 671 struct { 672 uint64_t start_addr; 673 uint64_t end_addr; 674 uint64_t fb_top; 675 uint64_t fb_offset; 676 uint64_t fb_base; 677 uint64_t agp_top; 678 uint64_t agp_bot; 679 uint64_t agp_base; 680 } system_aperture; 681 682 struct { 683 uint64_t page_table_start_addr; 684 uint64_t page_table_end_addr; 685 uint64_t page_table_base_addr; 686 bool base_addr_is_mc_addr; 687 } gart_config; 688 689 bool valid; 690 bool is_hvm_enabled; 691 uint64_t page_table_default_page_addr; 692 }; 693 694 struct dc_virtual_addr_space_config { 695 uint64_t page_table_base_addr; 696 uint64_t page_table_start_addr; 697 uint64_t page_table_end_addr; 698 uint32_t page_table_block_size_in_bytes; 699 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 700 }; 701 702 struct dc_bounding_box_overrides { 703 int sr_exit_time_ns; 704 int sr_enter_plus_exit_time_ns; 705 int urgent_latency_ns; 706 int percent_of_ideal_drambw; 707 int dram_clock_change_latency_ns; 708 int dummy_clock_change_latency_ns; 709 int fclk_clock_change_latency_ns; 710 /* This forces a hard min on the DCFCLK we use 711 * for DML. Unlike the debug option for forcing 712 * DCFCLK, this override affects watermark calculations 713 */ 714 int min_dcfclk_mhz; 715 }; 716 717 struct dc_state; 718 struct resource_pool; 719 struct dce_hwseq; 720 721 /** 722 * struct dc_debug_options - DC debug struct 723 * 724 * This struct provides a simple mechanism for developers to change some 725 * configurations, enable/disable features, and activate extra debug options. 726 * This can be very handy to narrow down whether some specific feature is 727 * causing an issue or not. 728 */ 729 struct dc_debug_options { 730 bool native422_support; 731 bool disable_dsc; 732 enum visual_confirm visual_confirm; 733 int visual_confirm_rect_height; 734 735 bool sanity_checks; 736 bool max_disp_clk; 737 bool surface_trace; 738 bool timing_trace; 739 bool clock_trace; 740 bool validation_trace; 741 bool bandwidth_calcs_trace; 742 int max_downscale_src_width; 743 744 /* stutter efficiency related */ 745 bool disable_stutter; 746 bool use_max_lb; 747 enum dcc_option disable_dcc; 748 749 /** 750 * @pipe_split_policy: Define which pipe split policy is used by the 751 * display core. 752 */ 753 enum pipe_split_policy pipe_split_policy; 754 bool force_single_disp_pipe_split; 755 bool voltage_align_fclk; 756 bool disable_min_fclk; 757 758 bool disable_dfs_bypass; 759 bool disable_dpp_power_gate; 760 bool disable_hubp_power_gate; 761 bool disable_dsc_power_gate; 762 int dsc_min_slice_height_override; 763 int dsc_bpp_increment_div; 764 bool disable_pplib_wm_range; 765 enum wm_report_mode pplib_wm_report_mode; 766 unsigned int min_disp_clk_khz; 767 unsigned int min_dpp_clk_khz; 768 unsigned int min_dram_clk_khz; 769 int sr_exit_time_dpm0_ns; 770 int sr_enter_plus_exit_time_dpm0_ns; 771 int sr_exit_time_ns; 772 int sr_enter_plus_exit_time_ns; 773 int urgent_latency_ns; 774 uint32_t underflow_assert_delay_us; 775 int percent_of_ideal_drambw; 776 int dram_clock_change_latency_ns; 777 bool optimized_watermark; 778 int always_scale; 779 bool disable_pplib_clock_request; 780 bool disable_clock_gate; 781 bool disable_mem_low_power; 782 bool pstate_enabled; 783 bool disable_dmcu; 784 bool force_abm_enable; 785 bool disable_stereo_support; 786 bool vsr_support; 787 bool performance_trace; 788 bool az_endpoint_mute_only; 789 bool always_use_regamma; 790 bool recovery_enabled; 791 bool avoid_vbios_exec_table; 792 bool scl_reset_length10; 793 bool hdmi20_disable; 794 bool skip_detection_link_training; 795 uint32_t edid_read_retry_times; 796 unsigned int force_odm_combine; //bit vector based on otg inst 797 unsigned int seamless_boot_odm_combine; 798 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 799 bool disable_z9_mpc; 800 unsigned int force_fclk_khz; 801 bool enable_tri_buf; 802 bool dmub_offload_enabled; 803 bool dmcub_emulation; 804 bool disable_idle_power_optimizations; 805 unsigned int mall_size_override; 806 unsigned int mall_additional_timer_percent; 807 bool mall_error_as_fatal; 808 bool dmub_command_table; /* for testing only */ 809 struct dc_bw_validation_profile bw_val_profile; 810 bool disable_fec; 811 bool disable_48mhz_pwrdwn; 812 /* This forces a hard min on the DCFCLK requested to SMU/PP 813 * watermarks are not affected. 814 */ 815 unsigned int force_min_dcfclk_mhz; 816 int dwb_fi_phase; 817 bool disable_timing_sync; 818 bool cm_in_bypass; 819 int force_clock_mode;/*every mode change.*/ 820 821 bool disable_dram_clock_change_vactive_support; 822 bool validate_dml_output; 823 bool enable_dmcub_surface_flip; 824 bool usbc_combo_phy_reset_wa; 825 bool enable_dram_clock_change_one_display_vactive; 826 /* TODO - remove once tested */ 827 bool legacy_dp2_lt; 828 bool set_mst_en_for_sst; 829 bool disable_uhbr; 830 bool force_dp2_lt_fallback_method; 831 bool ignore_cable_id; 832 union mem_low_power_enable_options enable_mem_low_power; 833 union root_clock_optimization_options root_clock_optimization; 834 bool hpo_optimization; 835 bool force_vblank_alignment; 836 837 /* Enable dmub aux for legacy ddc */ 838 bool enable_dmub_aux_for_legacy_ddc; 839 bool disable_fams; 840 /* FEC/PSR1 sequence enable delay in 100us */ 841 uint8_t fec_enable_delay_in100us; 842 bool enable_driver_sequence_debug; 843 enum det_size crb_alloc_policy; 844 int crb_alloc_policy_min_disp_count; 845 bool disable_z10; 846 bool enable_z9_disable_interface; 847 bool psr_skip_crtc_disable; 848 union dpia_debug_options dpia_debug; 849 bool disable_fixed_vs_aux_timeout_wa; 850 bool force_disable_subvp; 851 bool force_subvp_mclk_switch; 852 bool allow_sw_cursor_fallback; 853 unsigned int force_subvp_num_ways; 854 unsigned int force_mall_ss_num_ways; 855 bool alloc_extra_way_for_cursor; 856 uint32_t subvp_extra_lines; 857 bool force_usr_allow; 858 /* uses value at boot and disables switch */ 859 bool disable_dtb_ref_clk_switch; 860 uint32_t fixed_vs_aux_delay_config_wa; 861 bool extended_blank_optimization; 862 union aux_wake_wa_options aux_wake_wa; 863 uint32_t mst_start_top_delay; 864 uint8_t psr_power_use_phy_fsm; 865 enum dml_hostvm_override_opts dml_hostvm_override; 866 bool dml_disallow_alternate_prefetch_modes; 867 bool use_legacy_soc_bb_mechanism; 868 bool exit_idle_opt_for_cursor_updates; 869 bool enable_single_display_2to1_odm_policy; 870 bool enable_double_buffered_dsc_pg_support; 871 bool enable_dp_dig_pixel_rate_div_policy; 872 enum lttpr_mode lttpr_mode_override; 873 unsigned int dsc_delay_factor_wa_x1000; 874 unsigned int min_prefetch_in_strobe_ns; 875 bool disable_unbounded_requesting; 876 bool dig_fifo_off_in_blank; 877 bool temp_mst_deallocation_sequence; 878 }; 879 880 struct gpu_info_soc_bounding_box_v1_0; 881 struct dc { 882 struct dc_debug_options debug; 883 struct dc_versions versions; 884 struct dc_caps caps; 885 struct dc_cap_funcs cap_funcs; 886 struct dc_config config; 887 struct dc_bounding_box_overrides bb_overrides; 888 struct dc_bug_wa work_arounds; 889 struct dc_context *ctx; 890 struct dc_phy_addr_space_config vm_pa_config; 891 892 uint8_t link_count; 893 struct dc_link *links[MAX_PIPES * 2]; 894 895 struct dc_state *current_state; 896 struct resource_pool *res_pool; 897 898 struct clk_mgr *clk_mgr; 899 900 /* Display Engine Clock levels */ 901 struct dm_pp_clock_levels sclk_lvls; 902 903 /* Inputs into BW and WM calculations. */ 904 struct bw_calcs_dceip *bw_dceip; 905 struct bw_calcs_vbios *bw_vbios; 906 struct dcn_soc_bounding_box *dcn_soc; 907 struct dcn_ip_params *dcn_ip; 908 struct display_mode_lib dml; 909 910 /* HW functions */ 911 struct hw_sequencer_funcs hwss; 912 struct dce_hwseq *hwseq; 913 914 /* Require to optimize clocks and bandwidth for added/removed planes */ 915 bool optimized_required; 916 bool wm_optimized_required; 917 bool idle_optimizations_allowed; 918 bool enable_c20_dtm_b0; 919 920 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 921 922 /* FBC compressor */ 923 struct compressor *fbc_compressor; 924 925 struct dc_debug_data debug_data; 926 struct dpcd_vendor_signature vendor_signature; 927 928 const char *build_id; 929 struct vm_helper *vm_helper; 930 931 uint32_t *dcn_reg_offsets; 932 uint32_t *nbio_reg_offsets; 933 934 /* Scratch memory */ 935 struct { 936 struct { 937 /* 938 * For matching clock_limits table in driver with table 939 * from PMFW. 940 */ 941 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 942 } update_bw_bounding_box; 943 } scratch; 944 }; 945 946 enum frame_buffer_mode { 947 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 948 FRAME_BUFFER_MODE_ZFB_ONLY, 949 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 950 } ; 951 952 struct dchub_init_data { 953 int64_t zfb_phys_addr_base; 954 int64_t zfb_mc_base_addr; 955 uint64_t zfb_size_in_byte; 956 enum frame_buffer_mode fb_mode; 957 bool dchub_initialzied; 958 bool dchub_info_valid; 959 }; 960 961 struct dc_init_data { 962 struct hw_asic_id asic_id; 963 void *driver; /* ctx */ 964 struct cgs_device *cgs_device; 965 struct dc_bounding_box_overrides bb_overrides; 966 967 int num_virtual_links; 968 /* 969 * If 'vbios_override' not NULL, it will be called instead 970 * of the real VBIOS. Intended use is Diagnostics on FPGA. 971 */ 972 struct dc_bios *vbios_override; 973 enum dce_environment dce_environment; 974 975 struct dmub_offload_funcs *dmub_if; 976 struct dc_reg_helper_state *dmub_offload; 977 978 struct dc_config flags; 979 uint64_t log_mask; 980 981 struct dpcd_vendor_signature vendor_signature; 982 bool force_smu_not_present; 983 /* 984 * IP offset for run time initializaion of register addresses 985 * 986 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 987 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 988 * before them. 989 */ 990 uint32_t *dcn_reg_offsets; 991 uint32_t *nbio_reg_offsets; 992 }; 993 994 struct dc_callback_init { 995 #ifdef CONFIG_DRM_AMD_DC_HDCP 996 struct cp_psp cp_psp; 997 #else 998 uint8_t reserved; 999 #endif 1000 }; 1001 1002 struct dc *dc_create(const struct dc_init_data *init_params); 1003 void dc_hardware_init(struct dc *dc); 1004 1005 int dc_get_vmid_use_vector(struct dc *dc); 1006 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1007 /* Returns the number of vmids supported */ 1008 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1009 void dc_init_callbacks(struct dc *dc, 1010 const struct dc_callback_init *init_params); 1011 void dc_deinit_callbacks(struct dc *dc); 1012 void dc_destroy(struct dc **dc); 1013 1014 /* Surface Interfaces */ 1015 1016 enum { 1017 TRANSFER_FUNC_POINTS = 1025 1018 }; 1019 1020 struct dc_hdr_static_metadata { 1021 /* display chromaticities and white point in units of 0.00001 */ 1022 unsigned int chromaticity_green_x; 1023 unsigned int chromaticity_green_y; 1024 unsigned int chromaticity_blue_x; 1025 unsigned int chromaticity_blue_y; 1026 unsigned int chromaticity_red_x; 1027 unsigned int chromaticity_red_y; 1028 unsigned int chromaticity_white_point_x; 1029 unsigned int chromaticity_white_point_y; 1030 1031 uint32_t min_luminance; 1032 uint32_t max_luminance; 1033 uint32_t maximum_content_light_level; 1034 uint32_t maximum_frame_average_light_level; 1035 }; 1036 1037 enum dc_transfer_func_type { 1038 TF_TYPE_PREDEFINED, 1039 TF_TYPE_DISTRIBUTED_POINTS, 1040 TF_TYPE_BYPASS, 1041 TF_TYPE_HWPWL 1042 }; 1043 1044 struct dc_transfer_func_distributed_points { 1045 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1046 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1047 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1048 1049 uint16_t end_exponent; 1050 uint16_t x_point_at_y1_red; 1051 uint16_t x_point_at_y1_green; 1052 uint16_t x_point_at_y1_blue; 1053 }; 1054 1055 enum dc_transfer_func_predefined { 1056 TRANSFER_FUNCTION_SRGB, 1057 TRANSFER_FUNCTION_BT709, 1058 TRANSFER_FUNCTION_PQ, 1059 TRANSFER_FUNCTION_LINEAR, 1060 TRANSFER_FUNCTION_UNITY, 1061 TRANSFER_FUNCTION_HLG, 1062 TRANSFER_FUNCTION_HLG12, 1063 TRANSFER_FUNCTION_GAMMA22, 1064 TRANSFER_FUNCTION_GAMMA24, 1065 TRANSFER_FUNCTION_GAMMA26 1066 }; 1067 1068 1069 struct dc_transfer_func { 1070 struct kref refcount; 1071 enum dc_transfer_func_type type; 1072 enum dc_transfer_func_predefined tf; 1073 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1074 uint32_t sdr_ref_white_level; 1075 union { 1076 struct pwl_params pwl; 1077 struct dc_transfer_func_distributed_points tf_pts; 1078 }; 1079 }; 1080 1081 1082 union dc_3dlut_state { 1083 struct { 1084 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1085 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1086 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1087 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1088 uint32_t mpc_rmu1_mux:4; 1089 uint32_t mpc_rmu2_mux:4; 1090 uint32_t reserved:15; 1091 } bits; 1092 uint32_t raw; 1093 }; 1094 1095 1096 struct dc_3dlut { 1097 struct kref refcount; 1098 struct tetrahedral_params lut_3d; 1099 struct fixed31_32 hdr_multiplier; 1100 union dc_3dlut_state state; 1101 }; 1102 /* 1103 * This structure is filled in by dc_surface_get_status and contains 1104 * the last requested address and the currently active address so the called 1105 * can determine if there are any outstanding flips 1106 */ 1107 struct dc_plane_status { 1108 struct dc_plane_address requested_address; 1109 struct dc_plane_address current_address; 1110 bool is_flip_pending; 1111 bool is_right_eye; 1112 }; 1113 1114 union surface_update_flags { 1115 1116 struct { 1117 uint32_t addr_update:1; 1118 /* Medium updates */ 1119 uint32_t dcc_change:1; 1120 uint32_t color_space_change:1; 1121 uint32_t horizontal_mirror_change:1; 1122 uint32_t per_pixel_alpha_change:1; 1123 uint32_t global_alpha_change:1; 1124 uint32_t hdr_mult:1; 1125 uint32_t rotation_change:1; 1126 uint32_t swizzle_change:1; 1127 uint32_t scaling_change:1; 1128 uint32_t position_change:1; 1129 uint32_t in_transfer_func_change:1; 1130 uint32_t input_csc_change:1; 1131 uint32_t coeff_reduction_change:1; 1132 uint32_t output_tf_change:1; 1133 uint32_t pixel_format_change:1; 1134 uint32_t plane_size_change:1; 1135 uint32_t gamut_remap_change:1; 1136 1137 /* Full updates */ 1138 uint32_t new_plane:1; 1139 uint32_t bpp_change:1; 1140 uint32_t gamma_change:1; 1141 uint32_t bandwidth_change:1; 1142 uint32_t clock_change:1; 1143 uint32_t stereo_format_change:1; 1144 uint32_t lut_3d:1; 1145 uint32_t tmz_changed:1; 1146 uint32_t full_update:1; 1147 } bits; 1148 1149 uint32_t raw; 1150 }; 1151 1152 struct dc_plane_state { 1153 struct dc_plane_address address; 1154 struct dc_plane_flip_time time; 1155 bool triplebuffer_flips; 1156 struct scaling_taps scaling_quality; 1157 struct rect src_rect; 1158 struct rect dst_rect; 1159 struct rect clip_rect; 1160 1161 struct plane_size plane_size; 1162 union dc_tiling_info tiling_info; 1163 1164 struct dc_plane_dcc_param dcc; 1165 1166 struct dc_gamma *gamma_correction; 1167 struct dc_transfer_func *in_transfer_func; 1168 struct dc_bias_and_scale *bias_and_scale; 1169 struct dc_csc_transform input_csc_color_matrix; 1170 struct fixed31_32 coeff_reduction_factor; 1171 struct fixed31_32 hdr_mult; 1172 struct colorspace_transform gamut_remap_matrix; 1173 1174 // TODO: No longer used, remove 1175 struct dc_hdr_static_metadata hdr_static_ctx; 1176 1177 enum dc_color_space color_space; 1178 1179 struct dc_3dlut *lut3d_func; 1180 struct dc_transfer_func *in_shaper_func; 1181 struct dc_transfer_func *blend_tf; 1182 1183 struct dc_transfer_func *gamcor_tf; 1184 enum surface_pixel_format format; 1185 enum dc_rotation_angle rotation; 1186 enum plane_stereo_format stereo_format; 1187 1188 bool is_tiling_rotated; 1189 bool per_pixel_alpha; 1190 bool pre_multiplied_alpha; 1191 bool global_alpha; 1192 int global_alpha_value; 1193 bool visible; 1194 bool flip_immediate; 1195 bool horizontal_mirror; 1196 int layer_index; 1197 1198 union surface_update_flags update_flags; 1199 bool flip_int_enabled; 1200 bool skip_manual_trigger; 1201 1202 /* private to DC core */ 1203 struct dc_plane_status status; 1204 struct dc_context *ctx; 1205 1206 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1207 bool force_full_update; 1208 1209 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1210 1211 /* private to dc_surface.c */ 1212 enum dc_irq_source irq_source; 1213 struct kref refcount; 1214 struct tg_color visual_confirm_color; 1215 1216 bool is_statically_allocated; 1217 }; 1218 1219 struct dc_plane_info { 1220 struct plane_size plane_size; 1221 union dc_tiling_info tiling_info; 1222 struct dc_plane_dcc_param dcc; 1223 enum surface_pixel_format format; 1224 enum dc_rotation_angle rotation; 1225 enum plane_stereo_format stereo_format; 1226 enum dc_color_space color_space; 1227 bool horizontal_mirror; 1228 bool visible; 1229 bool per_pixel_alpha; 1230 bool pre_multiplied_alpha; 1231 bool global_alpha; 1232 int global_alpha_value; 1233 bool input_csc_enabled; 1234 int layer_index; 1235 }; 1236 1237 struct dc_scaling_info { 1238 struct rect src_rect; 1239 struct rect dst_rect; 1240 struct rect clip_rect; 1241 struct scaling_taps scaling_quality; 1242 }; 1243 1244 struct dc_surface_update { 1245 struct dc_plane_state *surface; 1246 1247 /* isr safe update parameters. null means no updates */ 1248 const struct dc_flip_addrs *flip_addr; 1249 const struct dc_plane_info *plane_info; 1250 const struct dc_scaling_info *scaling_info; 1251 struct fixed31_32 hdr_mult; 1252 /* following updates require alloc/sleep/spin that is not isr safe, 1253 * null means no updates 1254 */ 1255 const struct dc_gamma *gamma; 1256 const struct dc_transfer_func *in_transfer_func; 1257 1258 const struct dc_csc_transform *input_csc_color_matrix; 1259 const struct fixed31_32 *coeff_reduction_factor; 1260 const struct dc_transfer_func *func_shaper; 1261 const struct dc_3dlut *lut3d_func; 1262 const struct dc_transfer_func *blend_tf; 1263 const struct colorspace_transform *gamut_remap_matrix; 1264 }; 1265 1266 /* 1267 * Create a new surface with default parameters; 1268 */ 1269 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1270 const struct dc_plane_status *dc_plane_get_status( 1271 const struct dc_plane_state *plane_state); 1272 1273 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1274 void dc_plane_state_release(struct dc_plane_state *plane_state); 1275 1276 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1277 void dc_gamma_release(struct dc_gamma **dc_gamma); 1278 struct dc_gamma *dc_create_gamma(void); 1279 1280 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1281 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1282 struct dc_transfer_func *dc_create_transfer_func(void); 1283 1284 struct dc_3dlut *dc_create_3dlut_func(void); 1285 void dc_3dlut_func_release(struct dc_3dlut *lut); 1286 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1287 1288 void dc_post_update_surfaces_to_stream( 1289 struct dc *dc); 1290 1291 #include "dc_stream.h" 1292 1293 /** 1294 * struct dc_validation_set - Struct to store surface/stream associations for validation 1295 */ 1296 struct dc_validation_set { 1297 /** 1298 * @stream: Stream state properties 1299 */ 1300 struct dc_stream_state *stream; 1301 1302 /** 1303 * @plane_state: Surface state 1304 */ 1305 struct dc_plane_state *plane_states[MAX_SURFACES]; 1306 1307 /** 1308 * @plane_count: Total of active planes 1309 */ 1310 uint8_t plane_count; 1311 }; 1312 1313 bool dc_validate_boot_timing(const struct dc *dc, 1314 const struct dc_sink *sink, 1315 struct dc_crtc_timing *crtc_timing); 1316 1317 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1318 1319 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1320 1321 enum dc_status dc_validate_with_context(struct dc *dc, 1322 const struct dc_validation_set set[], 1323 int set_count, 1324 struct dc_state *context, 1325 bool fast_validate); 1326 1327 bool dc_set_generic_gpio_for_stereo(bool enable, 1328 struct gpio_service *gpio_service); 1329 1330 /* 1331 * fast_validate: we return after determining if we can support the new state, 1332 * but before we populate the programming info 1333 */ 1334 enum dc_status dc_validate_global_state( 1335 struct dc *dc, 1336 struct dc_state *new_ctx, 1337 bool fast_validate); 1338 1339 1340 void dc_resource_state_construct( 1341 const struct dc *dc, 1342 struct dc_state *dst_ctx); 1343 1344 bool dc_acquire_release_mpc_3dlut( 1345 struct dc *dc, bool acquire, 1346 struct dc_stream_state *stream, 1347 struct dc_3dlut **lut, 1348 struct dc_transfer_func **shaper); 1349 1350 void dc_resource_state_copy_construct( 1351 const struct dc_state *src_ctx, 1352 struct dc_state *dst_ctx); 1353 1354 void dc_resource_state_copy_construct_current( 1355 const struct dc *dc, 1356 struct dc_state *dst_ctx); 1357 1358 void dc_resource_state_destruct(struct dc_state *context); 1359 1360 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1361 1362 enum dc_status dc_commit_streams(struct dc *dc, 1363 struct dc_stream_state *streams[], 1364 uint8_t stream_count); 1365 1366 /* TODO: When the transition to the new commit sequence is done, remove this 1367 * function in favor of dc_commit_streams. */ 1368 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1369 1370 struct dc_state *dc_create_state(struct dc *dc); 1371 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1372 void dc_retain_state(struct dc_state *context); 1373 void dc_release_state(struct dc_state *context); 1374 1375 /* Link Interfaces */ 1376 1377 struct dpcd_caps { 1378 union dpcd_rev dpcd_rev; 1379 union max_lane_count max_ln_count; 1380 union max_down_spread max_down_spread; 1381 union dprx_feature dprx_feature; 1382 1383 /* valid only for eDP v1.4 or higher*/ 1384 uint8_t edp_supported_link_rates_count; 1385 enum dc_link_rate edp_supported_link_rates[8]; 1386 1387 /* dongle type (DP converter, CV smart dongle) */ 1388 enum display_dongle_type dongle_type; 1389 bool is_dongle_type_one; 1390 /* branch device or sink device */ 1391 bool is_branch_dev; 1392 /* Dongle's downstream count. */ 1393 union sink_count sink_count; 1394 bool is_mst_capable; 1395 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1396 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1397 struct dc_dongle_caps dongle_caps; 1398 1399 uint32_t sink_dev_id; 1400 int8_t sink_dev_id_str[6]; 1401 int8_t sink_hw_revision; 1402 int8_t sink_fw_revision[2]; 1403 1404 uint32_t branch_dev_id; 1405 int8_t branch_dev_name[6]; 1406 int8_t branch_hw_revision; 1407 int8_t branch_fw_revision[2]; 1408 1409 bool allow_invalid_MSA_timing_param; 1410 bool panel_mode_edp; 1411 bool dpcd_display_control_capable; 1412 bool ext_receiver_cap_field_present; 1413 bool set_power_state_capable_edp; 1414 bool dynamic_backlight_capable_edp; 1415 union dpcd_fec_capability fec_cap; 1416 struct dpcd_dsc_capabilities dsc_caps; 1417 struct dc_lttpr_caps lttpr_caps; 1418 struct adaptive_sync_caps adaptive_sync_caps; 1419 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1420 1421 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1422 union dp_main_line_channel_coding_cap channel_coding_cap; 1423 union dp_sink_video_fallback_formats fallback_formats; 1424 union dp_fec_capability1 fec_cap1; 1425 union dp_cable_id cable_id; 1426 uint8_t edp_rev; 1427 union edp_alpm_caps alpm_caps; 1428 struct edp_psr_info psr_info; 1429 }; 1430 1431 union dpcd_sink_ext_caps { 1432 struct { 1433 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1434 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1435 */ 1436 uint8_t sdr_aux_backlight_control : 1; 1437 uint8_t hdr_aux_backlight_control : 1; 1438 uint8_t reserved_1 : 2; 1439 uint8_t oled : 1; 1440 uint8_t reserved : 3; 1441 } bits; 1442 uint8_t raw; 1443 }; 1444 1445 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1446 union hdcp_rx_caps { 1447 struct { 1448 uint8_t version; 1449 uint8_t reserved; 1450 struct { 1451 uint8_t repeater : 1; 1452 uint8_t hdcp_capable : 1; 1453 uint8_t reserved : 6; 1454 } byte0; 1455 } fields; 1456 uint8_t raw[3]; 1457 }; 1458 1459 union hdcp_bcaps { 1460 struct { 1461 uint8_t HDCP_CAPABLE:1; 1462 uint8_t REPEATER:1; 1463 uint8_t RESERVED:6; 1464 } bits; 1465 uint8_t raw; 1466 }; 1467 1468 struct hdcp_caps { 1469 union hdcp_rx_caps rx_caps; 1470 union hdcp_bcaps bcaps; 1471 }; 1472 #endif 1473 1474 #include "dc_link.h" 1475 1476 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1477 1478 /* Sink Interfaces - A sink corresponds to a display output device */ 1479 1480 struct dc_container_id { 1481 // 128bit GUID in binary form 1482 unsigned char guid[16]; 1483 // 8 byte port ID -> ELD.PortID 1484 unsigned int portId[2]; 1485 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1486 unsigned short manufacturerName; 1487 // 2 byte product code -> ELD.ProductCode 1488 unsigned short productCode; 1489 }; 1490 1491 1492 struct dc_sink_dsc_caps { 1493 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1494 // 'false' if they are sink's DSC caps 1495 bool is_virtual_dpcd_dsc; 1496 #if defined(CONFIG_DRM_AMD_DC_DCN) 1497 // 'true' if MST topology supports DSC passthrough for sink 1498 // 'false' if MST topology does not support DSC passthrough 1499 bool is_dsc_passthrough_supported; 1500 #endif 1501 struct dsc_dec_dpcd_caps dsc_dec_caps; 1502 }; 1503 1504 struct dc_sink_fec_caps { 1505 bool is_rx_fec_supported; 1506 bool is_topology_fec_supported; 1507 }; 1508 1509 struct scdc_caps { 1510 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 1511 union hdmi_scdc_device_id_data device_id; 1512 }; 1513 1514 /* 1515 * The sink structure contains EDID and other display device properties 1516 */ 1517 struct dc_sink { 1518 enum signal_type sink_signal; 1519 struct dc_edid dc_edid; /* raw edid */ 1520 struct dc_edid_caps edid_caps; /* parse display caps */ 1521 struct dc_container_id *dc_container_id; 1522 uint32_t dongle_max_pix_clk; 1523 void *priv; 1524 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1525 bool converter_disable_audio; 1526 1527 struct scdc_caps scdc_caps; 1528 struct dc_sink_dsc_caps dsc_caps; 1529 struct dc_sink_fec_caps fec_caps; 1530 1531 bool is_vsc_sdp_colorimetry_supported; 1532 1533 /* private to DC core */ 1534 struct dc_link *link; 1535 struct dc_context *ctx; 1536 1537 uint32_t sink_id; 1538 1539 /* private to dc_sink.c */ 1540 // refcount must be the last member in dc_sink, since we want the 1541 // sink structure to be logically cloneable up to (but not including) 1542 // refcount 1543 struct kref refcount; 1544 }; 1545 1546 void dc_sink_retain(struct dc_sink *sink); 1547 void dc_sink_release(struct dc_sink *sink); 1548 1549 struct dc_sink_init_data { 1550 enum signal_type sink_signal; 1551 struct dc_link *link; 1552 uint32_t dongle_max_pix_clk; 1553 bool converter_disable_audio; 1554 }; 1555 1556 bool dc_extended_blank_supported(struct dc *dc); 1557 1558 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1559 1560 /* Newer interfaces */ 1561 struct dc_cursor { 1562 struct dc_plane_address address; 1563 struct dc_cursor_attributes attributes; 1564 }; 1565 1566 1567 /* Interrupt interfaces */ 1568 enum dc_irq_source dc_interrupt_to_irq_source( 1569 struct dc *dc, 1570 uint32_t src_id, 1571 uint32_t ext_id); 1572 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1573 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1574 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1575 struct dc *dc, uint32_t link_index); 1576 1577 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1578 1579 /* Power Interfaces */ 1580 1581 void dc_set_power_state( 1582 struct dc *dc, 1583 enum dc_acpi_cm_power_state power_state); 1584 void dc_resume(struct dc *dc); 1585 1586 void dc_power_down_on_boot(struct dc *dc); 1587 1588 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1589 /* 1590 * HDCP Interfaces 1591 */ 1592 enum hdcp_message_status dc_process_hdcp_msg( 1593 enum signal_type signal, 1594 struct dc_link *link, 1595 struct hdcp_protection_message *message_info); 1596 #endif 1597 bool dc_is_dmcu_initialized(struct dc *dc); 1598 1599 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1600 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1601 1602 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1603 struct dc_cursor_attributes *cursor_attr); 1604 1605 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1606 1607 /* set min and max memory clock to lowest and highest DPM level, respectively */ 1608 void dc_unlock_memory_clock_frequency(struct dc *dc); 1609 1610 /* set min memory clock to the min required for current mode, max to maxDPM */ 1611 void dc_lock_memory_clock_frequency(struct dc *dc); 1612 1613 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1614 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1615 1616 /* cleanup on driver unload */ 1617 void dc_hardware_release(struct dc *dc); 1618 1619 /* disables fw based mclk switch */ 1620 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 1621 1622 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1623 void dc_z10_restore(const struct dc *dc); 1624 void dc_z10_save_init(struct dc *dc); 1625 1626 bool dc_is_dmub_outbox_supported(struct dc *dc); 1627 bool dc_enable_dmub_notifications(struct dc *dc); 1628 1629 void dc_enable_dmub_outbox(struct dc *dc); 1630 1631 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1632 uint32_t link_index, 1633 struct aux_payload *payload); 1634 1635 /* Get dc link index from dpia port index */ 1636 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1637 uint8_t dpia_port_index); 1638 1639 bool dc_process_dmub_set_config_async(struct dc *dc, 1640 uint32_t link_index, 1641 struct set_config_cmd_payload *payload, 1642 struct dmub_notification *notify); 1643 1644 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1645 uint32_t link_index, 1646 uint8_t mst_alloc_slots, 1647 uint8_t *mst_slots_in_use); 1648 1649 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 1650 uint32_t hpd_int_enable); 1651 1652 /* DSC Interfaces */ 1653 #include "dc_dsc.h" 1654 1655 /* Disable acc mode Interfaces */ 1656 void dc_disable_accelerated_mode(struct dc *dc); 1657 1658 #endif /* DC_INTERFACE_H_ */ 1659