1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.177" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 // Sizes defined as multiples of 64KB 79 enum det_size { 80 DET_SIZE_DEFAULT = 0, 81 DET_SIZE_192KB = 3, 82 DET_SIZE_256KB = 4, 83 DET_SIZE_320KB = 5, 84 DET_SIZE_384KB = 6 85 }; 86 87 88 struct dc_plane_cap { 89 enum dc_plane_type type; 90 uint32_t blends_with_above : 1; 91 uint32_t blends_with_below : 1; 92 uint32_t per_pixel_alpha : 1; 93 struct { 94 uint32_t argb8888 : 1; 95 uint32_t nv12 : 1; 96 uint32_t fp16 : 1; 97 uint32_t p010 : 1; 98 uint32_t ayuv : 1; 99 } pixel_format_support; 100 // max upscaling factor x1000 101 // upscaling factors are always >= 1 102 // for example, 1080p -> 8K is 4.0, or 4000 raw value 103 struct { 104 uint32_t argb8888; 105 uint32_t nv12; 106 uint32_t fp16; 107 } max_upscale_factor; 108 // max downscale factor x1000 109 // downscale factors are always <= 1 110 // for example, 8K -> 1080p is 0.25, or 250 raw value 111 struct { 112 uint32_t argb8888; 113 uint32_t nv12; 114 uint32_t fp16; 115 } max_downscale_factor; 116 // minimal width/height 117 uint32_t min_width; 118 uint32_t min_height; 119 }; 120 121 // Color management caps (DPP and MPC) 122 struct rom_curve_caps { 123 uint16_t srgb : 1; 124 uint16_t bt2020 : 1; 125 uint16_t gamma2_2 : 1; 126 uint16_t pq : 1; 127 uint16_t hlg : 1; 128 }; 129 130 struct dpp_color_caps { 131 uint16_t dcn_arch : 1; // all DCE generations treated the same 132 // input lut is different than most LUTs, just plain 256-entry lookup 133 uint16_t input_lut_shared : 1; // shared with DGAM 134 uint16_t icsc : 1; 135 uint16_t dgam_ram : 1; 136 uint16_t post_csc : 1; // before gamut remap 137 uint16_t gamma_corr : 1; 138 139 // hdr_mult and gamut remap always available in DPP (in that order) 140 // 3d lut implies shaper LUT, 141 // it may be shared with MPC - check MPC:shared_3d_lut flag 142 uint16_t hw_3d_lut : 1; 143 uint16_t ogam_ram : 1; // blnd gam 144 uint16_t ocsc : 1; 145 uint16_t dgam_rom_for_yuv : 1; 146 struct rom_curve_caps dgam_rom_caps; 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct mpc_color_caps { 151 uint16_t gamut_remap : 1; 152 uint16_t ogam_ram : 1; 153 uint16_t ocsc : 1; 154 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 155 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 156 157 struct rom_curve_caps ogam_rom_caps; 158 }; 159 160 struct dc_color_caps { 161 struct dpp_color_caps dpp; 162 struct mpc_color_caps mpc; 163 }; 164 165 struct dc_caps { 166 uint32_t max_streams; 167 uint32_t max_links; 168 uint32_t max_audios; 169 uint32_t max_slave_planes; 170 uint32_t max_slave_yuv_planes; 171 uint32_t max_slave_rgb_planes; 172 uint32_t max_planes; 173 uint32_t max_downscale_ratio; 174 uint32_t i2c_speed_in_khz; 175 uint32_t i2c_speed_in_khz_hdcp; 176 uint32_t dmdata_alloc_size; 177 unsigned int max_cursor_size; 178 unsigned int max_video_width; 179 unsigned int min_horizontal_blanking_period; 180 int linear_pitch_alignment; 181 bool dcc_const_color; 182 bool dynamic_audio; 183 bool is_apu; 184 bool dual_link_dvi; 185 bool post_blend_color_processing; 186 bool force_dp_tps4_for_cp2520; 187 bool disable_dp_clk_share; 188 bool psp_setup_panel_mode; 189 bool extended_aux_timeout_support; 190 bool dmcub_support; 191 bool zstate_support; 192 uint32_t num_of_internal_disp; 193 enum dp_protocol_version max_dp_protocol_version; 194 unsigned int mall_size_per_mem_channel; 195 unsigned int mall_size_total; 196 unsigned int cursor_cache_size; 197 struct dc_plane_cap planes[MAX_PLANES]; 198 struct dc_color_caps color; 199 bool dp_hpo; 200 bool hdmi_frl_pcon_support; 201 bool edp_dsc_support; 202 bool vbios_lttpr_aware; 203 bool vbios_lttpr_enable; 204 uint32_t max_otg_num; 205 }; 206 207 struct dc_bug_wa { 208 bool no_connect_phy_config; 209 bool dedcn20_305_wa; 210 bool skip_clock_update; 211 bool lt_early_cr_pattern; 212 }; 213 214 struct dc_dcc_surface_param { 215 struct dc_size surface_size; 216 enum surface_pixel_format format; 217 enum swizzle_mode_values swizzle_mode; 218 enum dc_scan_direction scan; 219 }; 220 221 struct dc_dcc_setting { 222 unsigned int max_compressed_blk_size; 223 unsigned int max_uncompressed_blk_size; 224 bool independent_64b_blks; 225 #if defined(CONFIG_DRM_AMD_DC_DCN) 226 //These bitfields to be used starting with DCN 227 struct { 228 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 229 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 230 uint32_t dcc_256_128_128 : 1; //available starting with DCN 231 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 232 } dcc_controls; 233 #endif 234 }; 235 236 struct dc_surface_dcc_cap { 237 union { 238 struct { 239 struct dc_dcc_setting rgb; 240 } grph; 241 242 struct { 243 struct dc_dcc_setting luma; 244 struct dc_dcc_setting chroma; 245 } video; 246 }; 247 248 bool capable; 249 bool const_color_support; 250 }; 251 252 struct dc_static_screen_params { 253 struct { 254 bool force_trigger; 255 bool cursor_update; 256 bool surface_update; 257 bool overlay_update; 258 } triggers; 259 unsigned int num_frames; 260 }; 261 262 263 /* Surface update type is used by dc_update_surfaces_and_stream 264 * The update type is determined at the very beginning of the function based 265 * on parameters passed in and decides how much programming (or updating) is 266 * going to be done during the call. 267 * 268 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 269 * logical calculations or hardware register programming. This update MUST be 270 * ISR safe on windows. Currently fast update will only be used to flip surface 271 * address. 272 * 273 * UPDATE_TYPE_MED is used for slower updates which require significant hw 274 * re-programming however do not affect bandwidth consumption or clock 275 * requirements. At present, this is the level at which front end updates 276 * that do not require us to run bw_calcs happen. These are in/out transfer func 277 * updates, viewport offset changes, recout size changes and pixel depth changes. 278 * This update can be done at ISR, but we want to minimize how often this happens. 279 * 280 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 281 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 282 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 283 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 284 * a full update. This cannot be done at ISR level and should be a rare event. 285 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 286 * underscan we don't expect to see this call at all. 287 */ 288 289 enum surface_update_type { 290 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 291 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 292 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 293 }; 294 295 /* Forward declaration*/ 296 struct dc; 297 struct dc_plane_state; 298 struct dc_state; 299 300 301 struct dc_cap_funcs { 302 bool (*get_dcc_compression_cap)(const struct dc *dc, 303 const struct dc_dcc_surface_param *input, 304 struct dc_surface_dcc_cap *output); 305 }; 306 307 struct link_training_settings; 308 309 union allow_lttpr_non_transparent_mode { 310 struct { 311 bool DP1_4A : 1; 312 bool DP2_0 : 1; 313 } bits; 314 unsigned char raw; 315 }; 316 317 /* Structure to hold configuration flags set by dm at dc creation. */ 318 struct dc_config { 319 bool gpu_vm_support; 320 bool disable_disp_pll_sharing; 321 bool fbc_support; 322 bool disable_fractional_pwm; 323 bool allow_seamless_boot_optimization; 324 bool seamless_boot_edp_requested; 325 bool edp_not_connected; 326 bool edp_no_power_sequencing; 327 bool force_enum_edp; 328 bool forced_clocks; 329 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 330 bool multi_mon_pp_mclk_switch; 331 bool disable_dmcu; 332 bool enable_4to1MPC; 333 bool enable_windowed_mpo_odm; 334 bool allow_edp_hotplug_detection; 335 #if defined(CONFIG_DRM_AMD_DC_DCN) 336 bool clamp_min_dcfclk; 337 #endif 338 uint64_t vblank_alignment_dto_params; 339 uint8_t vblank_alignment_max_frame_time_diff; 340 bool is_asymmetric_memory; 341 bool is_single_rank_dimm; 342 bool use_pipe_ctx_sync_logic; 343 }; 344 345 enum visual_confirm { 346 VISUAL_CONFIRM_DISABLE = 0, 347 VISUAL_CONFIRM_SURFACE = 1, 348 VISUAL_CONFIRM_HDR = 2, 349 VISUAL_CONFIRM_MPCTREE = 4, 350 VISUAL_CONFIRM_PSR = 5, 351 VISUAL_CONFIRM_SWIZZLE = 9, 352 }; 353 354 enum dc_psr_power_opts { 355 psr_power_opt_invalid = 0x0, 356 psr_power_opt_smu_opt_static_screen = 0x1, 357 psr_power_opt_z10_static_screen = 0x10, 358 psr_power_opt_ds_disable_allow = 0x100, 359 }; 360 361 enum dcc_option { 362 DCC_ENABLE = 0, 363 DCC_DISABLE = 1, 364 DCC_HALF_REQ_DISALBE = 2, 365 }; 366 367 enum pipe_split_policy { 368 MPC_SPLIT_DYNAMIC = 0, 369 MPC_SPLIT_AVOID = 1, 370 MPC_SPLIT_AVOID_MULT_DISP = 2, 371 }; 372 373 enum wm_report_mode { 374 WM_REPORT_DEFAULT = 0, 375 WM_REPORT_OVERRIDE = 1, 376 }; 377 enum dtm_pstate{ 378 dtm_level_p0 = 0,/*highest voltage*/ 379 dtm_level_p1, 380 dtm_level_p2, 381 dtm_level_p3, 382 dtm_level_p4,/*when active_display_count = 0*/ 383 }; 384 385 enum dcn_pwr_state { 386 DCN_PWR_STATE_UNKNOWN = -1, 387 DCN_PWR_STATE_MISSION_MODE = 0, 388 DCN_PWR_STATE_LOW_POWER = 3, 389 }; 390 391 #if defined(CONFIG_DRM_AMD_DC_DCN) 392 enum dcn_zstate_support_state { 393 DCN_ZSTATE_SUPPORT_UNKNOWN, 394 DCN_ZSTATE_SUPPORT_ALLOW, 395 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 396 DCN_ZSTATE_SUPPORT_DISALLOW, 397 }; 398 #endif 399 /* 400 * For any clocks that may differ per pipe 401 * only the max is stored in this structure 402 */ 403 struct dc_clocks { 404 int dispclk_khz; 405 int actual_dispclk_khz; 406 int dppclk_khz; 407 int actual_dppclk_khz; 408 int disp_dpp_voltage_level_khz; 409 int dcfclk_khz; 410 int socclk_khz; 411 int dcfclk_deep_sleep_khz; 412 int fclk_khz; 413 int phyclk_khz; 414 int dramclk_khz; 415 bool p_state_change_support; 416 #if defined(CONFIG_DRM_AMD_DC_DCN) 417 enum dcn_zstate_support_state zstate_support; 418 bool dtbclk_en; 419 #endif 420 enum dcn_pwr_state pwr_state; 421 /* 422 * Elements below are not compared for the purposes of 423 * optimization required 424 */ 425 bool prev_p_state_change_support; 426 enum dtm_pstate dtm_level; 427 int max_supported_dppclk_khz; 428 int max_supported_dispclk_khz; 429 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 430 int bw_dispclk_khz; 431 }; 432 433 struct dc_bw_validation_profile { 434 bool enable; 435 436 unsigned long long total_ticks; 437 unsigned long long voltage_level_ticks; 438 unsigned long long watermark_ticks; 439 unsigned long long rq_dlg_ticks; 440 441 unsigned long long total_count; 442 unsigned long long skip_fast_count; 443 unsigned long long skip_pass_count; 444 unsigned long long skip_fail_count; 445 }; 446 447 #define BW_VAL_TRACE_SETUP() \ 448 unsigned long long end_tick = 0; \ 449 unsigned long long voltage_level_tick = 0; \ 450 unsigned long long watermark_tick = 0; \ 451 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 452 dm_get_timestamp(dc->ctx) : 0 453 454 #define BW_VAL_TRACE_COUNT() \ 455 if (dc->debug.bw_val_profile.enable) \ 456 dc->debug.bw_val_profile.total_count++ 457 458 #define BW_VAL_TRACE_SKIP(status) \ 459 if (dc->debug.bw_val_profile.enable) { \ 460 if (!voltage_level_tick) \ 461 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 462 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 463 } 464 465 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 466 if (dc->debug.bw_val_profile.enable) \ 467 voltage_level_tick = dm_get_timestamp(dc->ctx) 468 469 #define BW_VAL_TRACE_END_WATERMARKS() \ 470 if (dc->debug.bw_val_profile.enable) \ 471 watermark_tick = dm_get_timestamp(dc->ctx) 472 473 #define BW_VAL_TRACE_FINISH() \ 474 if (dc->debug.bw_val_profile.enable) { \ 475 end_tick = dm_get_timestamp(dc->ctx); \ 476 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 477 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 478 if (watermark_tick) { \ 479 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 480 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 481 } \ 482 } 483 484 union mem_low_power_enable_options { 485 struct { 486 bool vga: 1; 487 bool i2c: 1; 488 bool dmcu: 1; 489 bool dscl: 1; 490 bool cm: 1; 491 bool mpc: 1; 492 bool optc: 1; 493 bool vpg: 1; 494 bool afmt: 1; 495 } bits; 496 uint32_t u32All; 497 }; 498 499 union root_clock_optimization_options { 500 struct { 501 bool dpp: 1; 502 bool dsc: 1; 503 bool hdmistream: 1; 504 bool hdmichar: 1; 505 bool dpstream: 1; 506 bool symclk32_se: 1; 507 bool symclk32_le: 1; 508 bool symclk_fe: 1; 509 bool physymclk: 1; 510 bool dpiasymclk: 1; 511 uint32_t reserved: 22; 512 } bits; 513 uint32_t u32All; 514 }; 515 516 union dpia_debug_options { 517 struct { 518 uint32_t disable_dpia:1; /* bit 0 */ 519 uint32_t force_non_lttpr:1; /* bit 1 */ 520 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 521 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 522 uint32_t hpd_delay_in_ms:12; /* bits 4-15 */ 523 uint32_t disable_force_tbt3_work_around:1; /* bit 16 */ 524 uint32_t reserved:15; 525 } bits; 526 uint32_t raw; 527 }; 528 529 /* AUX wake work around options 530 * 0: enable/disable work around 531 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 532 * 15-2: reserved 533 * 31-16: timeout in ms 534 */ 535 union aux_wake_wa_options { 536 struct { 537 uint32_t enable_wa : 1; 538 uint32_t use_default_timeout : 1; 539 uint32_t rsvd: 14; 540 uint32_t timeout_ms : 16; 541 } bits; 542 uint32_t raw; 543 }; 544 545 struct dc_debug_data { 546 uint32_t ltFailCount; 547 uint32_t i2cErrorCount; 548 uint32_t auxErrorCount; 549 }; 550 551 struct dc_phy_addr_space_config { 552 struct { 553 uint64_t start_addr; 554 uint64_t end_addr; 555 uint64_t fb_top; 556 uint64_t fb_offset; 557 uint64_t fb_base; 558 uint64_t agp_top; 559 uint64_t agp_bot; 560 uint64_t agp_base; 561 } system_aperture; 562 563 struct { 564 uint64_t page_table_start_addr; 565 uint64_t page_table_end_addr; 566 uint64_t page_table_base_addr; 567 bool base_addr_is_mc_addr; 568 } gart_config; 569 570 bool valid; 571 bool is_hvm_enabled; 572 uint64_t page_table_default_page_addr; 573 }; 574 575 struct dc_virtual_addr_space_config { 576 uint64_t page_table_base_addr; 577 uint64_t page_table_start_addr; 578 uint64_t page_table_end_addr; 579 uint32_t page_table_block_size_in_bytes; 580 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 581 }; 582 583 struct dc_bounding_box_overrides { 584 int sr_exit_time_ns; 585 int sr_enter_plus_exit_time_ns; 586 int urgent_latency_ns; 587 int percent_of_ideal_drambw; 588 int dram_clock_change_latency_ns; 589 int dummy_clock_change_latency_ns; 590 /* This forces a hard min on the DCFCLK we use 591 * for DML. Unlike the debug option for forcing 592 * DCFCLK, this override affects watermark calculations 593 */ 594 int min_dcfclk_mhz; 595 }; 596 597 struct dc_state; 598 struct resource_pool; 599 struct dce_hwseq; 600 601 struct dc_debug_options { 602 bool native422_support; 603 bool disable_dsc; 604 enum visual_confirm visual_confirm; 605 int visual_confirm_rect_height; 606 607 bool sanity_checks; 608 bool max_disp_clk; 609 bool surface_trace; 610 bool timing_trace; 611 bool clock_trace; 612 bool validation_trace; 613 bool bandwidth_calcs_trace; 614 int max_downscale_src_width; 615 616 /* stutter efficiency related */ 617 bool disable_stutter; 618 bool use_max_lb; 619 enum dcc_option disable_dcc; 620 enum pipe_split_policy pipe_split_policy; 621 bool force_single_disp_pipe_split; 622 bool voltage_align_fclk; 623 bool disable_min_fclk; 624 625 bool disable_dfs_bypass; 626 bool disable_dpp_power_gate; 627 bool disable_hubp_power_gate; 628 bool disable_dsc_power_gate; 629 int dsc_min_slice_height_override; 630 int dsc_bpp_increment_div; 631 bool disable_pplib_wm_range; 632 enum wm_report_mode pplib_wm_report_mode; 633 unsigned int min_disp_clk_khz; 634 unsigned int min_dpp_clk_khz; 635 unsigned int min_dram_clk_khz; 636 int sr_exit_time_dpm0_ns; 637 int sr_enter_plus_exit_time_dpm0_ns; 638 int sr_exit_time_ns; 639 int sr_enter_plus_exit_time_ns; 640 int urgent_latency_ns; 641 uint32_t underflow_assert_delay_us; 642 int percent_of_ideal_drambw; 643 int dram_clock_change_latency_ns; 644 bool optimized_watermark; 645 int always_scale; 646 bool disable_pplib_clock_request; 647 bool disable_clock_gate; 648 bool disable_mem_low_power; 649 #if defined(CONFIG_DRM_AMD_DC_DCN) 650 bool pstate_enabled; 651 #endif 652 bool disable_dmcu; 653 bool disable_psr; 654 bool force_abm_enable; 655 bool disable_stereo_support; 656 bool vsr_support; 657 bool performance_trace; 658 bool az_endpoint_mute_only; 659 bool always_use_regamma; 660 bool recovery_enabled; 661 bool avoid_vbios_exec_table; 662 bool scl_reset_length10; 663 bool hdmi20_disable; 664 bool skip_detection_link_training; 665 uint32_t edid_read_retry_times; 666 bool remove_disconnect_edp; 667 unsigned int force_odm_combine; //bit vector based on otg inst 668 #if defined(CONFIG_DRM_AMD_DC_DCN) 669 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 670 bool disable_z9_mpc; 671 #endif 672 unsigned int force_fclk_khz; 673 bool enable_tri_buf; 674 bool dmub_offload_enabled; 675 bool dmcub_emulation; 676 #if defined(CONFIG_DRM_AMD_DC_DCN) 677 bool disable_idle_power_optimizations; 678 unsigned int mall_size_override; 679 unsigned int mall_additional_timer_percent; 680 bool mall_error_as_fatal; 681 #endif 682 bool dmub_command_table; /* for testing only */ 683 struct dc_bw_validation_profile bw_val_profile; 684 bool disable_fec; 685 bool disable_48mhz_pwrdwn; 686 /* This forces a hard min on the DCFCLK requested to SMU/PP 687 * watermarks are not affected. 688 */ 689 unsigned int force_min_dcfclk_mhz; 690 #if defined(CONFIG_DRM_AMD_DC_DCN) 691 int dwb_fi_phase; 692 #endif 693 bool disable_timing_sync; 694 bool cm_in_bypass; 695 int force_clock_mode;/*every mode change.*/ 696 697 bool disable_dram_clock_change_vactive_support; 698 bool validate_dml_output; 699 bool enable_dmcub_surface_flip; 700 bool usbc_combo_phy_reset_wa; 701 bool disable_dsc_edp; 702 unsigned int force_dsc_edp_policy; 703 bool enable_dram_clock_change_one_display_vactive; 704 /* TODO - remove once tested */ 705 bool legacy_dp2_lt; 706 bool set_mst_en_for_sst; 707 bool disable_uhbr; 708 bool force_dp2_lt_fallback_method; 709 bool ignore_cable_id; 710 union mem_low_power_enable_options enable_mem_low_power; 711 union root_clock_optimization_options root_clock_optimization; 712 bool hpo_optimization; 713 bool force_vblank_alignment; 714 715 /* Enable dmub aux for legacy ddc */ 716 bool enable_dmub_aux_for_legacy_ddc; 717 bool optimize_edp_link_rate; /* eDP ILR */ 718 /* FEC/PSR1 sequence enable delay in 100us */ 719 uint8_t fec_enable_delay_in100us; 720 bool enable_driver_sequence_debug; 721 enum det_size crb_alloc_policy; 722 int crb_alloc_policy_min_disp_count; 723 bool disable_z10; 724 #if defined(CONFIG_DRM_AMD_DC_DCN) 725 bool enable_z9_disable_interface; 726 bool enable_sw_cntl_psr; 727 union dpia_debug_options dpia_debug; 728 #endif 729 bool apply_vendor_specific_lttpr_wa; 730 bool extended_blank_optimization; 731 union aux_wake_wa_options aux_wake_wa; 732 bool ignore_dpref_ss; 733 uint8_t psr_power_use_phy_fsm; 734 }; 735 736 struct gpu_info_soc_bounding_box_v1_0; 737 struct dc { 738 struct dc_debug_options debug; 739 struct dc_versions versions; 740 struct dc_caps caps; 741 struct dc_cap_funcs cap_funcs; 742 struct dc_config config; 743 struct dc_bounding_box_overrides bb_overrides; 744 struct dc_bug_wa work_arounds; 745 struct dc_context *ctx; 746 struct dc_phy_addr_space_config vm_pa_config; 747 748 uint8_t link_count; 749 struct dc_link *links[MAX_PIPES * 2]; 750 751 struct dc_state *current_state; 752 struct resource_pool *res_pool; 753 754 struct clk_mgr *clk_mgr; 755 756 /* Display Engine Clock levels */ 757 struct dm_pp_clock_levels sclk_lvls; 758 759 /* Inputs into BW and WM calculations. */ 760 struct bw_calcs_dceip *bw_dceip; 761 struct bw_calcs_vbios *bw_vbios; 762 #ifdef CONFIG_DRM_AMD_DC_DCN 763 struct dcn_soc_bounding_box *dcn_soc; 764 struct dcn_ip_params *dcn_ip; 765 struct display_mode_lib dml; 766 #endif 767 768 /* HW functions */ 769 struct hw_sequencer_funcs hwss; 770 struct dce_hwseq *hwseq; 771 772 /* Require to optimize clocks and bandwidth for added/removed planes */ 773 bool optimized_required; 774 bool wm_optimized_required; 775 #if defined(CONFIG_DRM_AMD_DC_DCN) 776 bool idle_optimizations_allowed; 777 #endif 778 #if defined(CONFIG_DRM_AMD_DC_DCN) 779 bool enable_c20_dtm_b0; 780 #endif 781 782 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 783 784 /* FBC compressor */ 785 struct compressor *fbc_compressor; 786 787 struct dc_debug_data debug_data; 788 struct dpcd_vendor_signature vendor_signature; 789 790 const char *build_id; 791 struct vm_helper *vm_helper; 792 }; 793 794 enum frame_buffer_mode { 795 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 796 FRAME_BUFFER_MODE_ZFB_ONLY, 797 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 798 } ; 799 800 struct dchub_init_data { 801 int64_t zfb_phys_addr_base; 802 int64_t zfb_mc_base_addr; 803 uint64_t zfb_size_in_byte; 804 enum frame_buffer_mode fb_mode; 805 bool dchub_initialzied; 806 bool dchub_info_valid; 807 }; 808 809 struct dc_init_data { 810 struct hw_asic_id asic_id; 811 void *driver; /* ctx */ 812 struct cgs_device *cgs_device; 813 struct dc_bounding_box_overrides bb_overrides; 814 815 int num_virtual_links; 816 /* 817 * If 'vbios_override' not NULL, it will be called instead 818 * of the real VBIOS. Intended use is Diagnostics on FPGA. 819 */ 820 struct dc_bios *vbios_override; 821 enum dce_environment dce_environment; 822 823 struct dmub_offload_funcs *dmub_if; 824 struct dc_reg_helper_state *dmub_offload; 825 826 struct dc_config flags; 827 uint64_t log_mask; 828 829 struct dpcd_vendor_signature vendor_signature; 830 #if defined(CONFIG_DRM_AMD_DC_DCN) 831 bool force_smu_not_present; 832 #endif 833 }; 834 835 struct dc_callback_init { 836 #ifdef CONFIG_DRM_AMD_DC_HDCP 837 struct cp_psp cp_psp; 838 #else 839 uint8_t reserved; 840 #endif 841 }; 842 843 struct dc *dc_create(const struct dc_init_data *init_params); 844 void dc_hardware_init(struct dc *dc); 845 846 int dc_get_vmid_use_vector(struct dc *dc); 847 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 848 /* Returns the number of vmids supported */ 849 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 850 void dc_init_callbacks(struct dc *dc, 851 const struct dc_callback_init *init_params); 852 void dc_deinit_callbacks(struct dc *dc); 853 void dc_destroy(struct dc **dc); 854 855 /******************************************************************************* 856 * Surface Interfaces 857 ******************************************************************************/ 858 859 enum { 860 TRANSFER_FUNC_POINTS = 1025 861 }; 862 863 struct dc_hdr_static_metadata { 864 /* display chromaticities and white point in units of 0.00001 */ 865 unsigned int chromaticity_green_x; 866 unsigned int chromaticity_green_y; 867 unsigned int chromaticity_blue_x; 868 unsigned int chromaticity_blue_y; 869 unsigned int chromaticity_red_x; 870 unsigned int chromaticity_red_y; 871 unsigned int chromaticity_white_point_x; 872 unsigned int chromaticity_white_point_y; 873 874 uint32_t min_luminance; 875 uint32_t max_luminance; 876 uint32_t maximum_content_light_level; 877 uint32_t maximum_frame_average_light_level; 878 }; 879 880 enum dc_transfer_func_type { 881 TF_TYPE_PREDEFINED, 882 TF_TYPE_DISTRIBUTED_POINTS, 883 TF_TYPE_BYPASS, 884 TF_TYPE_HWPWL 885 }; 886 887 struct dc_transfer_func_distributed_points { 888 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 889 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 890 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 891 892 uint16_t end_exponent; 893 uint16_t x_point_at_y1_red; 894 uint16_t x_point_at_y1_green; 895 uint16_t x_point_at_y1_blue; 896 }; 897 898 enum dc_transfer_func_predefined { 899 TRANSFER_FUNCTION_SRGB, 900 TRANSFER_FUNCTION_BT709, 901 TRANSFER_FUNCTION_PQ, 902 TRANSFER_FUNCTION_LINEAR, 903 TRANSFER_FUNCTION_UNITY, 904 TRANSFER_FUNCTION_HLG, 905 TRANSFER_FUNCTION_HLG12, 906 TRANSFER_FUNCTION_GAMMA22, 907 TRANSFER_FUNCTION_GAMMA24, 908 TRANSFER_FUNCTION_GAMMA26 909 }; 910 911 912 struct dc_transfer_func { 913 struct kref refcount; 914 enum dc_transfer_func_type type; 915 enum dc_transfer_func_predefined tf; 916 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 917 uint32_t sdr_ref_white_level; 918 union { 919 struct pwl_params pwl; 920 struct dc_transfer_func_distributed_points tf_pts; 921 }; 922 }; 923 924 925 union dc_3dlut_state { 926 struct { 927 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 928 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 929 uint32_t rmu_mux_num:3; /*index of mux to use*/ 930 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 931 uint32_t mpc_rmu1_mux:4; 932 uint32_t mpc_rmu2_mux:4; 933 uint32_t reserved:15; 934 } bits; 935 uint32_t raw; 936 }; 937 938 939 struct dc_3dlut { 940 struct kref refcount; 941 struct tetrahedral_params lut_3d; 942 struct fixed31_32 hdr_multiplier; 943 union dc_3dlut_state state; 944 }; 945 /* 946 * This structure is filled in by dc_surface_get_status and contains 947 * the last requested address and the currently active address so the called 948 * can determine if there are any outstanding flips 949 */ 950 struct dc_plane_status { 951 struct dc_plane_address requested_address; 952 struct dc_plane_address current_address; 953 bool is_flip_pending; 954 bool is_right_eye; 955 }; 956 957 union surface_update_flags { 958 959 struct { 960 uint32_t addr_update:1; 961 /* Medium updates */ 962 uint32_t dcc_change:1; 963 uint32_t color_space_change:1; 964 uint32_t horizontal_mirror_change:1; 965 uint32_t per_pixel_alpha_change:1; 966 uint32_t global_alpha_change:1; 967 uint32_t hdr_mult:1; 968 uint32_t rotation_change:1; 969 uint32_t swizzle_change:1; 970 uint32_t scaling_change:1; 971 uint32_t position_change:1; 972 uint32_t in_transfer_func_change:1; 973 uint32_t input_csc_change:1; 974 uint32_t coeff_reduction_change:1; 975 uint32_t output_tf_change:1; 976 uint32_t pixel_format_change:1; 977 uint32_t plane_size_change:1; 978 uint32_t gamut_remap_change:1; 979 980 /* Full updates */ 981 uint32_t new_plane:1; 982 uint32_t bpp_change:1; 983 uint32_t gamma_change:1; 984 uint32_t bandwidth_change:1; 985 uint32_t clock_change:1; 986 uint32_t stereo_format_change:1; 987 uint32_t lut_3d:1; 988 uint32_t full_update:1; 989 } bits; 990 991 uint32_t raw; 992 }; 993 994 struct dc_plane_state { 995 struct dc_plane_address address; 996 struct dc_plane_flip_time time; 997 bool triplebuffer_flips; 998 struct scaling_taps scaling_quality; 999 struct rect src_rect; 1000 struct rect dst_rect; 1001 struct rect clip_rect; 1002 1003 struct plane_size plane_size; 1004 union dc_tiling_info tiling_info; 1005 1006 struct dc_plane_dcc_param dcc; 1007 1008 struct dc_gamma *gamma_correction; 1009 struct dc_transfer_func *in_transfer_func; 1010 struct dc_bias_and_scale *bias_and_scale; 1011 struct dc_csc_transform input_csc_color_matrix; 1012 struct fixed31_32 coeff_reduction_factor; 1013 struct fixed31_32 hdr_mult; 1014 struct colorspace_transform gamut_remap_matrix; 1015 1016 // TODO: No longer used, remove 1017 struct dc_hdr_static_metadata hdr_static_ctx; 1018 1019 enum dc_color_space color_space; 1020 1021 struct dc_3dlut *lut3d_func; 1022 struct dc_transfer_func *in_shaper_func; 1023 struct dc_transfer_func *blend_tf; 1024 1025 #if defined(CONFIG_DRM_AMD_DC_DCN) 1026 struct dc_transfer_func *gamcor_tf; 1027 #endif 1028 enum surface_pixel_format format; 1029 enum dc_rotation_angle rotation; 1030 enum plane_stereo_format stereo_format; 1031 1032 bool is_tiling_rotated; 1033 bool per_pixel_alpha; 1034 bool global_alpha; 1035 int global_alpha_value; 1036 bool visible; 1037 bool flip_immediate; 1038 bool horizontal_mirror; 1039 int layer_index; 1040 1041 union surface_update_flags update_flags; 1042 bool flip_int_enabled; 1043 bool skip_manual_trigger; 1044 1045 /* private to DC core */ 1046 struct dc_plane_status status; 1047 struct dc_context *ctx; 1048 1049 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1050 bool force_full_update; 1051 1052 /* private to dc_surface.c */ 1053 enum dc_irq_source irq_source; 1054 struct kref refcount; 1055 }; 1056 1057 struct dc_plane_info { 1058 struct plane_size plane_size; 1059 union dc_tiling_info tiling_info; 1060 struct dc_plane_dcc_param dcc; 1061 enum surface_pixel_format format; 1062 enum dc_rotation_angle rotation; 1063 enum plane_stereo_format stereo_format; 1064 enum dc_color_space color_space; 1065 bool horizontal_mirror; 1066 bool visible; 1067 bool per_pixel_alpha; 1068 bool global_alpha; 1069 int global_alpha_value; 1070 bool input_csc_enabled; 1071 int layer_index; 1072 }; 1073 1074 struct dc_scaling_info { 1075 struct rect src_rect; 1076 struct rect dst_rect; 1077 struct rect clip_rect; 1078 struct scaling_taps scaling_quality; 1079 }; 1080 1081 struct dc_surface_update { 1082 struct dc_plane_state *surface; 1083 1084 /* isr safe update parameters. null means no updates */ 1085 const struct dc_flip_addrs *flip_addr; 1086 const struct dc_plane_info *plane_info; 1087 const struct dc_scaling_info *scaling_info; 1088 struct fixed31_32 hdr_mult; 1089 /* following updates require alloc/sleep/spin that is not isr safe, 1090 * null means no updates 1091 */ 1092 const struct dc_gamma *gamma; 1093 const struct dc_transfer_func *in_transfer_func; 1094 1095 const struct dc_csc_transform *input_csc_color_matrix; 1096 const struct fixed31_32 *coeff_reduction_factor; 1097 const struct dc_transfer_func *func_shaper; 1098 const struct dc_3dlut *lut3d_func; 1099 const struct dc_transfer_func *blend_tf; 1100 const struct colorspace_transform *gamut_remap_matrix; 1101 }; 1102 1103 /* 1104 * Create a new surface with default parameters; 1105 */ 1106 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1107 const struct dc_plane_status *dc_plane_get_status( 1108 const struct dc_plane_state *plane_state); 1109 1110 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1111 void dc_plane_state_release(struct dc_plane_state *plane_state); 1112 1113 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1114 void dc_gamma_release(struct dc_gamma **dc_gamma); 1115 struct dc_gamma *dc_create_gamma(void); 1116 1117 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1118 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1119 struct dc_transfer_func *dc_create_transfer_func(void); 1120 1121 struct dc_3dlut *dc_create_3dlut_func(void); 1122 void dc_3dlut_func_release(struct dc_3dlut *lut); 1123 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1124 /* 1125 * This structure holds a surface address. There could be multiple addresses 1126 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1127 * as frame durations and DCC format can also be set. 1128 */ 1129 struct dc_flip_addrs { 1130 struct dc_plane_address address; 1131 unsigned int flip_timestamp_in_us; 1132 bool flip_immediate; 1133 /* TODO: add flip duration for FreeSync */ 1134 bool triplebuffer_flips; 1135 }; 1136 1137 void dc_post_update_surfaces_to_stream( 1138 struct dc *dc); 1139 1140 #include "dc_stream.h" 1141 1142 /* 1143 * Structure to store surface/stream associations for validation 1144 */ 1145 struct dc_validation_set { 1146 struct dc_stream_state *stream; 1147 struct dc_plane_state *plane_states[MAX_SURFACES]; 1148 uint8_t plane_count; 1149 }; 1150 1151 bool dc_validate_boot_timing(const struct dc *dc, 1152 const struct dc_sink *sink, 1153 struct dc_crtc_timing *crtc_timing); 1154 1155 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1156 1157 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1158 1159 bool dc_set_generic_gpio_for_stereo(bool enable, 1160 struct gpio_service *gpio_service); 1161 1162 /* 1163 * fast_validate: we return after determining if we can support the new state, 1164 * but before we populate the programming info 1165 */ 1166 enum dc_status dc_validate_global_state( 1167 struct dc *dc, 1168 struct dc_state *new_ctx, 1169 bool fast_validate); 1170 1171 1172 void dc_resource_state_construct( 1173 const struct dc *dc, 1174 struct dc_state *dst_ctx); 1175 1176 #if defined(CONFIG_DRM_AMD_DC_DCN) 1177 bool dc_acquire_release_mpc_3dlut( 1178 struct dc *dc, bool acquire, 1179 struct dc_stream_state *stream, 1180 struct dc_3dlut **lut, 1181 struct dc_transfer_func **shaper); 1182 #endif 1183 1184 void dc_resource_state_copy_construct( 1185 const struct dc_state *src_ctx, 1186 struct dc_state *dst_ctx); 1187 1188 void dc_resource_state_copy_construct_current( 1189 const struct dc *dc, 1190 struct dc_state *dst_ctx); 1191 1192 void dc_resource_state_destruct(struct dc_state *context); 1193 1194 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1195 1196 /* 1197 * TODO update to make it about validation sets 1198 * Set up streams and links associated to drive sinks 1199 * The streams parameter is an absolute set of all active streams. 1200 * 1201 * After this call: 1202 * Phy, Encoder, Timing Generator are programmed and enabled. 1203 * New streams are enabled with blank stream; no memory read. 1204 */ 1205 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1206 1207 struct dc_state *dc_create_state(struct dc *dc); 1208 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1209 void dc_retain_state(struct dc_state *context); 1210 void dc_release_state(struct dc_state *context); 1211 1212 /******************************************************************************* 1213 * Link Interfaces 1214 ******************************************************************************/ 1215 1216 struct dpcd_caps { 1217 union dpcd_rev dpcd_rev; 1218 union max_lane_count max_ln_count; 1219 union max_down_spread max_down_spread; 1220 union dprx_feature dprx_feature; 1221 1222 /* valid only for eDP v1.4 or higher*/ 1223 uint8_t edp_supported_link_rates_count; 1224 enum dc_link_rate edp_supported_link_rates[8]; 1225 1226 /* dongle type (DP converter, CV smart dongle) */ 1227 enum display_dongle_type dongle_type; 1228 bool is_dongle_type_one; 1229 /* branch device or sink device */ 1230 bool is_branch_dev; 1231 /* Dongle's downstream count. */ 1232 union sink_count sink_count; 1233 bool is_mst_capable; 1234 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1235 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1236 struct dc_dongle_caps dongle_caps; 1237 1238 uint32_t sink_dev_id; 1239 int8_t sink_dev_id_str[6]; 1240 int8_t sink_hw_revision; 1241 int8_t sink_fw_revision[2]; 1242 1243 uint32_t branch_dev_id; 1244 int8_t branch_dev_name[6]; 1245 int8_t branch_hw_revision; 1246 int8_t branch_fw_revision[2]; 1247 1248 bool allow_invalid_MSA_timing_param; 1249 bool panel_mode_edp; 1250 bool dpcd_display_control_capable; 1251 bool ext_receiver_cap_field_present; 1252 bool dynamic_backlight_capable_edp; 1253 union dpcd_fec_capability fec_cap; 1254 struct dpcd_dsc_capabilities dsc_caps; 1255 struct dc_lttpr_caps lttpr_caps; 1256 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1257 1258 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1259 union dp_main_line_channel_coding_cap channel_coding_cap; 1260 union dp_sink_video_fallback_formats fallback_formats; 1261 union dp_fec_capability1 fec_cap1; 1262 union dp_cable_id cable_id; 1263 uint8_t edp_rev; 1264 union edp_alpm_caps alpm_caps; 1265 struct edp_psr_info psr_info; 1266 }; 1267 1268 union dpcd_sink_ext_caps { 1269 struct { 1270 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1271 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1272 */ 1273 uint8_t sdr_aux_backlight_control : 1; 1274 uint8_t hdr_aux_backlight_control : 1; 1275 uint8_t reserved_1 : 2; 1276 uint8_t oled : 1; 1277 uint8_t reserved : 3; 1278 } bits; 1279 uint8_t raw; 1280 }; 1281 1282 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1283 union hdcp_rx_caps { 1284 struct { 1285 uint8_t version; 1286 uint8_t reserved; 1287 struct { 1288 uint8_t repeater : 1; 1289 uint8_t hdcp_capable : 1; 1290 uint8_t reserved : 6; 1291 } byte0; 1292 } fields; 1293 uint8_t raw[3]; 1294 }; 1295 1296 union hdcp_bcaps { 1297 struct { 1298 uint8_t HDCP_CAPABLE:1; 1299 uint8_t REPEATER:1; 1300 uint8_t RESERVED:6; 1301 } bits; 1302 uint8_t raw; 1303 }; 1304 1305 struct hdcp_caps { 1306 union hdcp_rx_caps rx_caps; 1307 union hdcp_bcaps bcaps; 1308 }; 1309 #endif 1310 1311 #include "dc_link.h" 1312 1313 #if defined(CONFIG_DRM_AMD_DC_DCN) 1314 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1315 1316 #endif 1317 /******************************************************************************* 1318 * Sink Interfaces - A sink corresponds to a display output device 1319 ******************************************************************************/ 1320 1321 struct dc_container_id { 1322 // 128bit GUID in binary form 1323 unsigned char guid[16]; 1324 // 8 byte port ID -> ELD.PortID 1325 unsigned int portId[2]; 1326 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1327 unsigned short manufacturerName; 1328 // 2 byte product code -> ELD.ProductCode 1329 unsigned short productCode; 1330 }; 1331 1332 1333 struct dc_sink_dsc_caps { 1334 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1335 // 'false' if they are sink's DSC caps 1336 bool is_virtual_dpcd_dsc; 1337 #if defined(CONFIG_DRM_AMD_DC_DCN) 1338 // 'true' if MST topology supports DSC passthrough for sink 1339 // 'false' if MST topology does not support DSC passthrough 1340 bool is_dsc_passthrough_supported; 1341 #endif 1342 struct dsc_dec_dpcd_caps dsc_dec_caps; 1343 }; 1344 1345 struct dc_sink_fec_caps { 1346 bool is_rx_fec_supported; 1347 bool is_topology_fec_supported; 1348 }; 1349 1350 /* 1351 * The sink structure contains EDID and other display device properties 1352 */ 1353 struct dc_sink { 1354 enum signal_type sink_signal; 1355 struct dc_edid dc_edid; /* raw edid */ 1356 struct dc_edid_caps edid_caps; /* parse display caps */ 1357 struct dc_container_id *dc_container_id; 1358 uint32_t dongle_max_pix_clk; 1359 void *priv; 1360 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1361 bool converter_disable_audio; 1362 1363 struct dc_sink_dsc_caps dsc_caps; 1364 struct dc_sink_fec_caps fec_caps; 1365 1366 bool is_vsc_sdp_colorimetry_supported; 1367 1368 /* private to DC core */ 1369 struct dc_link *link; 1370 struct dc_context *ctx; 1371 1372 uint32_t sink_id; 1373 1374 /* private to dc_sink.c */ 1375 // refcount must be the last member in dc_sink, since we want the 1376 // sink structure to be logically cloneable up to (but not including) 1377 // refcount 1378 struct kref refcount; 1379 }; 1380 1381 void dc_sink_retain(struct dc_sink *sink); 1382 void dc_sink_release(struct dc_sink *sink); 1383 1384 struct dc_sink_init_data { 1385 enum signal_type sink_signal; 1386 struct dc_link *link; 1387 uint32_t dongle_max_pix_clk; 1388 bool converter_disable_audio; 1389 }; 1390 1391 bool dc_extended_blank_supported(struct dc *dc); 1392 1393 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1394 1395 /* Newer interfaces */ 1396 struct dc_cursor { 1397 struct dc_plane_address address; 1398 struct dc_cursor_attributes attributes; 1399 }; 1400 1401 1402 /******************************************************************************* 1403 * Interrupt interfaces 1404 ******************************************************************************/ 1405 enum dc_irq_source dc_interrupt_to_irq_source( 1406 struct dc *dc, 1407 uint32_t src_id, 1408 uint32_t ext_id); 1409 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1410 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1411 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1412 struct dc *dc, uint32_t link_index); 1413 1414 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1415 1416 /******************************************************************************* 1417 * Power Interfaces 1418 ******************************************************************************/ 1419 1420 void dc_set_power_state( 1421 struct dc *dc, 1422 enum dc_acpi_cm_power_state power_state); 1423 void dc_resume(struct dc *dc); 1424 1425 void dc_power_down_on_boot(struct dc *dc); 1426 1427 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1428 /* 1429 * HDCP Interfaces 1430 */ 1431 enum hdcp_message_status dc_process_hdcp_msg( 1432 enum signal_type signal, 1433 struct dc_link *link, 1434 struct hdcp_protection_message *message_info); 1435 #endif 1436 bool dc_is_dmcu_initialized(struct dc *dc); 1437 1438 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1439 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1440 #if defined(CONFIG_DRM_AMD_DC_DCN) 1441 1442 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1443 struct dc_cursor_attributes *cursor_attr); 1444 1445 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1446 1447 /* 1448 * blank all streams, and set min and max memory clock to 1449 * lowest and highest DPM level, respectively 1450 */ 1451 void dc_unlock_memory_clock_frequency(struct dc *dc); 1452 1453 /* 1454 * set min memory clock to the min required for current mode, 1455 * max to maxDPM, and unblank streams 1456 */ 1457 void dc_lock_memory_clock_frequency(struct dc *dc); 1458 1459 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1460 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1461 1462 /* cleanup on driver unload */ 1463 void dc_hardware_release(struct dc *dc); 1464 1465 #endif 1466 1467 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1468 #if defined(CONFIG_DRM_AMD_DC_DCN) 1469 void dc_z10_restore(const struct dc *dc); 1470 void dc_z10_save_init(struct dc *dc); 1471 #endif 1472 1473 bool dc_is_dmub_outbox_supported(struct dc *dc); 1474 bool dc_enable_dmub_notifications(struct dc *dc); 1475 1476 void dc_enable_dmub_outbox(struct dc *dc); 1477 1478 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1479 uint32_t link_index, 1480 struct aux_payload *payload); 1481 1482 /* Get dc link index from dpia port index */ 1483 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1484 uint8_t dpia_port_index); 1485 1486 bool dc_process_dmub_set_config_async(struct dc *dc, 1487 uint32_t link_index, 1488 struct set_config_cmd_payload *payload, 1489 struct dmub_notification *notify); 1490 1491 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1492 uint32_t link_index, 1493 uint8_t mst_alloc_slots, 1494 uint8_t *mst_slots_in_use); 1495 1496 /******************************************************************************* 1497 * DSC Interfaces 1498 ******************************************************************************/ 1499 #include "dc_dsc.h" 1500 1501 /******************************************************************************* 1502 * Disable acc mode Interfaces 1503 ******************************************************************************/ 1504 void dc_disable_accelerated_mode(struct dc *dc); 1505 1506 #endif /* DC_INTERFACE_H_ */ 1507