1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.160" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 struct dc_plane_cap { 79 enum dc_plane_type type; 80 uint32_t blends_with_above : 1; 81 uint32_t blends_with_below : 1; 82 uint32_t per_pixel_alpha : 1; 83 struct { 84 uint32_t argb8888 : 1; 85 uint32_t nv12 : 1; 86 uint32_t fp16 : 1; 87 uint32_t p010 : 1; 88 uint32_t ayuv : 1; 89 } pixel_format_support; 90 // max upscaling factor x1000 91 // upscaling factors are always >= 1 92 // for example, 1080p -> 8K is 4.0, or 4000 raw value 93 struct { 94 uint32_t argb8888; 95 uint32_t nv12; 96 uint32_t fp16; 97 } max_upscale_factor; 98 // max downscale factor x1000 99 // downscale factors are always <= 1 100 // for example, 8K -> 1080p is 0.25, or 250 raw value 101 struct { 102 uint32_t argb8888; 103 uint32_t nv12; 104 uint32_t fp16; 105 } max_downscale_factor; 106 // minimal width/height 107 uint32_t min_width; 108 uint32_t min_height; 109 }; 110 111 // Color management caps (DPP and MPC) 112 struct rom_curve_caps { 113 uint16_t srgb : 1; 114 uint16_t bt2020 : 1; 115 uint16_t gamma2_2 : 1; 116 uint16_t pq : 1; 117 uint16_t hlg : 1; 118 }; 119 120 struct dpp_color_caps { 121 uint16_t dcn_arch : 1; // all DCE generations treated the same 122 // input lut is different than most LUTs, just plain 256-entry lookup 123 uint16_t input_lut_shared : 1; // shared with DGAM 124 uint16_t icsc : 1; 125 uint16_t dgam_ram : 1; 126 uint16_t post_csc : 1; // before gamut remap 127 uint16_t gamma_corr : 1; 128 129 // hdr_mult and gamut remap always available in DPP (in that order) 130 // 3d lut implies shaper LUT, 131 // it may be shared with MPC - check MPC:shared_3d_lut flag 132 uint16_t hw_3d_lut : 1; 133 uint16_t ogam_ram : 1; // blnd gam 134 uint16_t ocsc : 1; 135 uint16_t dgam_rom_for_yuv : 1; 136 struct rom_curve_caps dgam_rom_caps; 137 struct rom_curve_caps ogam_rom_caps; 138 }; 139 140 struct mpc_color_caps { 141 uint16_t gamut_remap : 1; 142 uint16_t ogam_ram : 1; 143 uint16_t ocsc : 1; 144 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 145 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 146 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct dc_color_caps { 151 struct dpp_color_caps dpp; 152 struct mpc_color_caps mpc; 153 }; 154 155 struct dc_caps { 156 uint32_t max_streams; 157 uint32_t max_links; 158 uint32_t max_audios; 159 uint32_t max_slave_planes; 160 uint32_t max_slave_yuv_planes; 161 uint32_t max_slave_rgb_planes; 162 uint32_t max_planes; 163 uint32_t max_downscale_ratio; 164 uint32_t i2c_speed_in_khz; 165 uint32_t i2c_speed_in_khz_hdcp; 166 uint32_t dmdata_alloc_size; 167 unsigned int max_cursor_size; 168 unsigned int max_video_width; 169 unsigned int min_horizontal_blanking_period; 170 int linear_pitch_alignment; 171 bool dcc_const_color; 172 bool dynamic_audio; 173 bool is_apu; 174 bool dual_link_dvi; 175 bool post_blend_color_processing; 176 bool force_dp_tps4_for_cp2520; 177 bool disable_dp_clk_share; 178 bool psp_setup_panel_mode; 179 bool extended_aux_timeout_support; 180 bool dmcub_support; 181 uint32_t num_of_internal_disp; 182 enum dp_protocol_version max_dp_protocol_version; 183 unsigned int mall_size_per_mem_channel; 184 unsigned int mall_size_total; 185 unsigned int cursor_cache_size; 186 struct dc_plane_cap planes[MAX_PLANES]; 187 struct dc_color_caps color; 188 #if defined(CONFIG_DRM_AMD_DC_DCN) 189 bool dp_hpo; 190 #endif 191 bool vbios_lttpr_aware; 192 bool vbios_lttpr_enable; 193 }; 194 195 struct dc_bug_wa { 196 bool no_connect_phy_config; 197 bool dedcn20_305_wa; 198 bool skip_clock_update; 199 bool lt_early_cr_pattern; 200 }; 201 202 struct dc_dcc_surface_param { 203 struct dc_size surface_size; 204 enum surface_pixel_format format; 205 enum swizzle_mode_values swizzle_mode; 206 enum dc_scan_direction scan; 207 }; 208 209 struct dc_dcc_setting { 210 unsigned int max_compressed_blk_size; 211 unsigned int max_uncompressed_blk_size; 212 bool independent_64b_blks; 213 #if defined(CONFIG_DRM_AMD_DC_DCN) 214 //These bitfields to be used starting with DCN 215 struct { 216 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 217 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 218 uint32_t dcc_256_128_128 : 1; //available starting with DCN 219 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 220 } dcc_controls; 221 #endif 222 }; 223 224 struct dc_surface_dcc_cap { 225 union { 226 struct { 227 struct dc_dcc_setting rgb; 228 } grph; 229 230 struct { 231 struct dc_dcc_setting luma; 232 struct dc_dcc_setting chroma; 233 } video; 234 }; 235 236 bool capable; 237 bool const_color_support; 238 }; 239 240 struct dc_static_screen_params { 241 struct { 242 bool force_trigger; 243 bool cursor_update; 244 bool surface_update; 245 bool overlay_update; 246 } triggers; 247 unsigned int num_frames; 248 }; 249 250 251 /* Surface update type is used by dc_update_surfaces_and_stream 252 * The update type is determined at the very beginning of the function based 253 * on parameters passed in and decides how much programming (or updating) is 254 * going to be done during the call. 255 * 256 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 257 * logical calculations or hardware register programming. This update MUST be 258 * ISR safe on windows. Currently fast update will only be used to flip surface 259 * address. 260 * 261 * UPDATE_TYPE_MED is used for slower updates which require significant hw 262 * re-programming however do not affect bandwidth consumption or clock 263 * requirements. At present, this is the level at which front end updates 264 * that do not require us to run bw_calcs happen. These are in/out transfer func 265 * updates, viewport offset changes, recout size changes and pixel depth changes. 266 * This update can be done at ISR, but we want to minimize how often this happens. 267 * 268 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 269 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 270 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 271 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 272 * a full update. This cannot be done at ISR level and should be a rare event. 273 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 274 * underscan we don't expect to see this call at all. 275 */ 276 277 enum surface_update_type { 278 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 279 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 280 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 281 }; 282 283 /* Forward declaration*/ 284 struct dc; 285 struct dc_plane_state; 286 struct dc_state; 287 288 289 struct dc_cap_funcs { 290 bool (*get_dcc_compression_cap)(const struct dc *dc, 291 const struct dc_dcc_surface_param *input, 292 struct dc_surface_dcc_cap *output); 293 }; 294 295 struct link_training_settings; 296 297 #if defined(CONFIG_DRM_AMD_DC_DCN) 298 union allow_lttpr_non_transparent_mode { 299 struct { 300 bool DP1_4A : 1; 301 bool DP2_0 : 1; 302 } bits; 303 unsigned char raw; 304 }; 305 #endif 306 /* Structure to hold configuration flags set by dm at dc creation. */ 307 struct dc_config { 308 bool gpu_vm_support; 309 bool disable_disp_pll_sharing; 310 bool fbc_support; 311 bool disable_fractional_pwm; 312 bool allow_seamless_boot_optimization; 313 bool power_down_display_on_boot; 314 bool edp_not_connected; 315 bool edp_no_power_sequencing; 316 bool force_enum_edp; 317 bool forced_clocks; 318 #if defined(CONFIG_DRM_AMD_DC_DCN) 319 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 320 #else 321 bool allow_lttpr_non_transparent_mode; 322 #endif 323 bool multi_mon_pp_mclk_switch; 324 bool disable_dmcu; 325 bool enable_4to1MPC; 326 bool enable_windowed_mpo_odm; 327 bool allow_edp_hotplug_detection; 328 #if defined(CONFIG_DRM_AMD_DC_DCN) 329 bool clamp_min_dcfclk; 330 #endif 331 uint64_t vblank_alignment_dto_params; 332 uint8_t vblank_alignment_max_frame_time_diff; 333 bool is_asymmetric_memory; 334 bool is_single_rank_dimm; 335 }; 336 337 enum visual_confirm { 338 VISUAL_CONFIRM_DISABLE = 0, 339 VISUAL_CONFIRM_SURFACE = 1, 340 VISUAL_CONFIRM_HDR = 2, 341 VISUAL_CONFIRM_MPCTREE = 4, 342 VISUAL_CONFIRM_PSR = 5, 343 VISUAL_CONFIRM_SWIZZLE = 9, 344 }; 345 346 enum dc_psr_power_opts { 347 psr_power_opt_invalid = 0x0, 348 psr_power_opt_smu_opt_static_screen = 0x1, 349 psr_power_opt_z10_static_screen = 0x10, 350 }; 351 352 enum dcc_option { 353 DCC_ENABLE = 0, 354 DCC_DISABLE = 1, 355 DCC_HALF_REQ_DISALBE = 2, 356 }; 357 358 enum pipe_split_policy { 359 MPC_SPLIT_DYNAMIC = 0, 360 MPC_SPLIT_AVOID = 1, 361 MPC_SPLIT_AVOID_MULT_DISP = 2, 362 }; 363 364 enum wm_report_mode { 365 WM_REPORT_DEFAULT = 0, 366 WM_REPORT_OVERRIDE = 1, 367 }; 368 enum dtm_pstate{ 369 dtm_level_p0 = 0,/*highest voltage*/ 370 dtm_level_p1, 371 dtm_level_p2, 372 dtm_level_p3, 373 dtm_level_p4,/*when active_display_count = 0*/ 374 }; 375 376 enum dcn_pwr_state { 377 DCN_PWR_STATE_UNKNOWN = -1, 378 DCN_PWR_STATE_MISSION_MODE = 0, 379 DCN_PWR_STATE_LOW_POWER = 3, 380 }; 381 382 #if defined(CONFIG_DRM_AMD_DC_DCN) 383 enum dcn_zstate_support_state { 384 DCN_ZSTATE_SUPPORT_UNKNOWN, 385 DCN_ZSTATE_SUPPORT_ALLOW, 386 DCN_ZSTATE_SUPPORT_DISALLOW, 387 }; 388 #endif 389 /* 390 * For any clocks that may differ per pipe 391 * only the max is stored in this structure 392 */ 393 struct dc_clocks { 394 int dispclk_khz; 395 int actual_dispclk_khz; 396 int dppclk_khz; 397 int actual_dppclk_khz; 398 int disp_dpp_voltage_level_khz; 399 int dcfclk_khz; 400 int socclk_khz; 401 int dcfclk_deep_sleep_khz; 402 int fclk_khz; 403 int phyclk_khz; 404 int dramclk_khz; 405 bool p_state_change_support; 406 #if defined(CONFIG_DRM_AMD_DC_DCN) 407 enum dcn_zstate_support_state zstate_support; 408 bool dtbclk_en; 409 #endif 410 enum dcn_pwr_state pwr_state; 411 /* 412 * Elements below are not compared for the purposes of 413 * optimization required 414 */ 415 bool prev_p_state_change_support; 416 enum dtm_pstate dtm_level; 417 int max_supported_dppclk_khz; 418 int max_supported_dispclk_khz; 419 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 420 int bw_dispclk_khz; 421 }; 422 423 struct dc_bw_validation_profile { 424 bool enable; 425 426 unsigned long long total_ticks; 427 unsigned long long voltage_level_ticks; 428 unsigned long long watermark_ticks; 429 unsigned long long rq_dlg_ticks; 430 431 unsigned long long total_count; 432 unsigned long long skip_fast_count; 433 unsigned long long skip_pass_count; 434 unsigned long long skip_fail_count; 435 }; 436 437 #define BW_VAL_TRACE_SETUP() \ 438 unsigned long long end_tick = 0; \ 439 unsigned long long voltage_level_tick = 0; \ 440 unsigned long long watermark_tick = 0; \ 441 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 442 dm_get_timestamp(dc->ctx) : 0 443 444 #define BW_VAL_TRACE_COUNT() \ 445 if (dc->debug.bw_val_profile.enable) \ 446 dc->debug.bw_val_profile.total_count++ 447 448 #define BW_VAL_TRACE_SKIP(status) \ 449 if (dc->debug.bw_val_profile.enable) { \ 450 if (!voltage_level_tick) \ 451 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 452 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 453 } 454 455 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 456 if (dc->debug.bw_val_profile.enable) \ 457 voltage_level_tick = dm_get_timestamp(dc->ctx) 458 459 #define BW_VAL_TRACE_END_WATERMARKS() \ 460 if (dc->debug.bw_val_profile.enable) \ 461 watermark_tick = dm_get_timestamp(dc->ctx) 462 463 #define BW_VAL_TRACE_FINISH() \ 464 if (dc->debug.bw_val_profile.enable) { \ 465 end_tick = dm_get_timestamp(dc->ctx); \ 466 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 467 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 468 if (watermark_tick) { \ 469 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 470 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 471 } \ 472 } 473 474 union mem_low_power_enable_options { 475 struct { 476 bool vga: 1; 477 bool i2c: 1; 478 bool dmcu: 1; 479 bool dscl: 1; 480 bool cm: 1; 481 bool mpc: 1; 482 bool optc: 1; 483 bool vpg: 1; 484 bool afmt: 1; 485 } bits; 486 uint32_t u32All; 487 }; 488 489 union root_clock_optimization_options { 490 struct { 491 bool dpp: 1; 492 bool dsc: 1; 493 bool hdmistream: 1; 494 bool hdmichar: 1; 495 bool dpstream: 1; 496 bool symclk32_se: 1; 497 bool symclk32_le: 1; 498 bool symclk_fe: 1; 499 bool physymclk: 1; 500 bool dpiasymclk: 1; 501 uint32_t reserved: 22; 502 } bits; 503 uint32_t u32All; 504 }; 505 506 union dpia_debug_options { 507 struct { 508 uint32_t disable_dpia:1; 509 uint32_t force_non_lttpr:1; 510 uint32_t extend_aux_rd_interval:1; 511 uint32_t reserved:29; 512 } bits; 513 uint32_t raw; 514 }; 515 516 struct dc_debug_data { 517 uint32_t ltFailCount; 518 uint32_t i2cErrorCount; 519 uint32_t auxErrorCount; 520 }; 521 522 struct dc_phy_addr_space_config { 523 struct { 524 uint64_t start_addr; 525 uint64_t end_addr; 526 uint64_t fb_top; 527 uint64_t fb_offset; 528 uint64_t fb_base; 529 uint64_t agp_top; 530 uint64_t agp_bot; 531 uint64_t agp_base; 532 } system_aperture; 533 534 struct { 535 uint64_t page_table_start_addr; 536 uint64_t page_table_end_addr; 537 uint64_t page_table_base_addr; 538 bool base_addr_is_mc_addr; 539 } gart_config; 540 541 bool valid; 542 bool is_hvm_enabled; 543 uint64_t page_table_default_page_addr; 544 }; 545 546 struct dc_virtual_addr_space_config { 547 uint64_t page_table_base_addr; 548 uint64_t page_table_start_addr; 549 uint64_t page_table_end_addr; 550 uint32_t page_table_block_size_in_bytes; 551 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 552 }; 553 554 struct dc_bounding_box_overrides { 555 int sr_exit_time_ns; 556 int sr_enter_plus_exit_time_ns; 557 int urgent_latency_ns; 558 int percent_of_ideal_drambw; 559 int dram_clock_change_latency_ns; 560 int dummy_clock_change_latency_ns; 561 /* This forces a hard min on the DCFCLK we use 562 * for DML. Unlike the debug option for forcing 563 * DCFCLK, this override affects watermark calculations 564 */ 565 int min_dcfclk_mhz; 566 }; 567 568 struct dc_state; 569 struct resource_pool; 570 struct dce_hwseq; 571 572 struct dc_debug_options { 573 bool native422_support; 574 bool disable_dsc; 575 enum visual_confirm visual_confirm; 576 bool sanity_checks; 577 bool max_disp_clk; 578 bool surface_trace; 579 bool timing_trace; 580 bool clock_trace; 581 bool validation_trace; 582 bool bandwidth_calcs_trace; 583 int max_downscale_src_width; 584 585 /* stutter efficiency related */ 586 bool disable_stutter; 587 bool use_max_lb; 588 enum dcc_option disable_dcc; 589 enum pipe_split_policy pipe_split_policy; 590 bool force_single_disp_pipe_split; 591 bool voltage_align_fclk; 592 bool disable_min_fclk; 593 594 bool disable_dfs_bypass; 595 bool disable_dpp_power_gate; 596 bool disable_hubp_power_gate; 597 bool disable_dsc_power_gate; 598 int dsc_min_slice_height_override; 599 int dsc_bpp_increment_div; 600 bool disable_pplib_wm_range; 601 enum wm_report_mode pplib_wm_report_mode; 602 unsigned int min_disp_clk_khz; 603 unsigned int min_dpp_clk_khz; 604 unsigned int min_dram_clk_khz; 605 int sr_exit_time_dpm0_ns; 606 int sr_enter_plus_exit_time_dpm0_ns; 607 int sr_exit_time_ns; 608 int sr_enter_plus_exit_time_ns; 609 int urgent_latency_ns; 610 uint32_t underflow_assert_delay_us; 611 int percent_of_ideal_drambw; 612 int dram_clock_change_latency_ns; 613 bool optimized_watermark; 614 int always_scale; 615 bool disable_pplib_clock_request; 616 bool disable_clock_gate; 617 bool disable_mem_low_power; 618 #if defined(CONFIG_DRM_AMD_DC_DCN) 619 bool pstate_enabled; 620 #endif 621 bool disable_dmcu; 622 bool disable_psr; 623 bool force_abm_enable; 624 bool disable_stereo_support; 625 bool vsr_support; 626 bool performance_trace; 627 bool az_endpoint_mute_only; 628 bool always_use_regamma; 629 bool recovery_enabled; 630 bool avoid_vbios_exec_table; 631 bool scl_reset_length10; 632 bool hdmi20_disable; 633 bool skip_detection_link_training; 634 uint32_t edid_read_retry_times; 635 bool remove_disconnect_edp; 636 unsigned int force_odm_combine; //bit vector based on otg inst 637 #if defined(CONFIG_DRM_AMD_DC_DCN) 638 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 639 bool disable_z9_mpc; 640 #endif 641 unsigned int force_fclk_khz; 642 bool enable_tri_buf; 643 bool dmub_offload_enabled; 644 bool dmcub_emulation; 645 #if defined(CONFIG_DRM_AMD_DC_DCN) 646 bool disable_idle_power_optimizations; 647 unsigned int mall_size_override; 648 unsigned int mall_additional_timer_percent; 649 bool mall_error_as_fatal; 650 #endif 651 bool dmub_command_table; /* for testing only */ 652 struct dc_bw_validation_profile bw_val_profile; 653 bool disable_fec; 654 bool disable_48mhz_pwrdwn; 655 /* This forces a hard min on the DCFCLK requested to SMU/PP 656 * watermarks are not affected. 657 */ 658 unsigned int force_min_dcfclk_mhz; 659 #if defined(CONFIG_DRM_AMD_DC_DCN) 660 int dwb_fi_phase; 661 #endif 662 bool disable_timing_sync; 663 bool cm_in_bypass; 664 int force_clock_mode;/*every mode change.*/ 665 666 bool disable_dram_clock_change_vactive_support; 667 bool validate_dml_output; 668 bool enable_dmcub_surface_flip; 669 bool usbc_combo_phy_reset_wa; 670 bool enable_dram_clock_change_one_display_vactive; 671 #if defined(CONFIG_DRM_AMD_DC_DCN) 672 /* TODO - remove once tested */ 673 bool legacy_dp2_lt; 674 bool set_mst_en_for_sst; 675 #endif 676 union mem_low_power_enable_options enable_mem_low_power; 677 union root_clock_optimization_options root_clock_optimization; 678 bool hpo_optimization; 679 bool force_vblank_alignment; 680 681 /* Enable dmub aux for legacy ddc */ 682 bool enable_dmub_aux_for_legacy_ddc; 683 bool optimize_edp_link_rate; /* eDP ILR */ 684 /* FEC/PSR1 sequence enable delay in 100us */ 685 uint8_t fec_enable_delay_in100us; 686 bool enable_driver_sequence_debug; 687 #if defined(CONFIG_DRM_AMD_DC_DCN) 688 bool disable_z10; 689 bool enable_sw_cntl_psr; 690 union dpia_debug_options dpia_debug; 691 #endif 692 }; 693 694 struct gpu_info_soc_bounding_box_v1_0; 695 struct dc { 696 struct dc_debug_options debug; 697 struct dc_versions versions; 698 struct dc_caps caps; 699 struct dc_cap_funcs cap_funcs; 700 struct dc_config config; 701 struct dc_bounding_box_overrides bb_overrides; 702 struct dc_bug_wa work_arounds; 703 struct dc_context *ctx; 704 struct dc_phy_addr_space_config vm_pa_config; 705 706 uint8_t link_count; 707 struct dc_link *links[MAX_PIPES * 2]; 708 709 struct dc_state *current_state; 710 struct resource_pool *res_pool; 711 712 struct clk_mgr *clk_mgr; 713 714 /* Display Engine Clock levels */ 715 struct dm_pp_clock_levels sclk_lvls; 716 717 /* Inputs into BW and WM calculations. */ 718 struct bw_calcs_dceip *bw_dceip; 719 struct bw_calcs_vbios *bw_vbios; 720 #ifdef CONFIG_DRM_AMD_DC_DCN 721 struct dcn_soc_bounding_box *dcn_soc; 722 struct dcn_ip_params *dcn_ip; 723 struct display_mode_lib dml; 724 #endif 725 726 /* HW functions */ 727 struct hw_sequencer_funcs hwss; 728 struct dce_hwseq *hwseq; 729 730 /* Require to optimize clocks and bandwidth for added/removed planes */ 731 bool optimized_required; 732 bool wm_optimized_required; 733 #if defined(CONFIG_DRM_AMD_DC_DCN) 734 bool idle_optimizations_allowed; 735 #endif 736 #if defined(CONFIG_DRM_AMD_DC_DCN) 737 bool enable_c20_dtm_b0; 738 #endif 739 740 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 741 742 /* FBC compressor */ 743 struct compressor *fbc_compressor; 744 745 struct dc_debug_data debug_data; 746 struct dpcd_vendor_signature vendor_signature; 747 748 const char *build_id; 749 struct vm_helper *vm_helper; 750 }; 751 752 enum frame_buffer_mode { 753 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 754 FRAME_BUFFER_MODE_ZFB_ONLY, 755 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 756 } ; 757 758 struct dchub_init_data { 759 int64_t zfb_phys_addr_base; 760 int64_t zfb_mc_base_addr; 761 uint64_t zfb_size_in_byte; 762 enum frame_buffer_mode fb_mode; 763 bool dchub_initialzied; 764 bool dchub_info_valid; 765 }; 766 767 struct dc_init_data { 768 struct hw_asic_id asic_id; 769 void *driver; /* ctx */ 770 struct cgs_device *cgs_device; 771 struct dc_bounding_box_overrides bb_overrides; 772 773 int num_virtual_links; 774 /* 775 * If 'vbios_override' not NULL, it will be called instead 776 * of the real VBIOS. Intended use is Diagnostics on FPGA. 777 */ 778 struct dc_bios *vbios_override; 779 enum dce_environment dce_environment; 780 781 struct dmub_offload_funcs *dmub_if; 782 struct dc_reg_helper_state *dmub_offload; 783 784 struct dc_config flags; 785 uint64_t log_mask; 786 787 struct dpcd_vendor_signature vendor_signature; 788 #if defined(CONFIG_DRM_AMD_DC_DCN) 789 bool force_smu_not_present; 790 #endif 791 }; 792 793 struct dc_callback_init { 794 #ifdef CONFIG_DRM_AMD_DC_HDCP 795 struct cp_psp cp_psp; 796 #else 797 uint8_t reserved; 798 #endif 799 }; 800 801 struct dc *dc_create(const struct dc_init_data *init_params); 802 void dc_hardware_init(struct dc *dc); 803 804 int dc_get_vmid_use_vector(struct dc *dc); 805 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 806 /* Returns the number of vmids supported */ 807 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 808 void dc_init_callbacks(struct dc *dc, 809 const struct dc_callback_init *init_params); 810 void dc_deinit_callbacks(struct dc *dc); 811 void dc_destroy(struct dc **dc); 812 813 /******************************************************************************* 814 * Surface Interfaces 815 ******************************************************************************/ 816 817 enum { 818 TRANSFER_FUNC_POINTS = 1025 819 }; 820 821 struct dc_hdr_static_metadata { 822 /* display chromaticities and white point in units of 0.00001 */ 823 unsigned int chromaticity_green_x; 824 unsigned int chromaticity_green_y; 825 unsigned int chromaticity_blue_x; 826 unsigned int chromaticity_blue_y; 827 unsigned int chromaticity_red_x; 828 unsigned int chromaticity_red_y; 829 unsigned int chromaticity_white_point_x; 830 unsigned int chromaticity_white_point_y; 831 832 uint32_t min_luminance; 833 uint32_t max_luminance; 834 uint32_t maximum_content_light_level; 835 uint32_t maximum_frame_average_light_level; 836 }; 837 838 enum dc_transfer_func_type { 839 TF_TYPE_PREDEFINED, 840 TF_TYPE_DISTRIBUTED_POINTS, 841 TF_TYPE_BYPASS, 842 TF_TYPE_HWPWL 843 }; 844 845 struct dc_transfer_func_distributed_points { 846 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 847 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 848 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 849 850 uint16_t end_exponent; 851 uint16_t x_point_at_y1_red; 852 uint16_t x_point_at_y1_green; 853 uint16_t x_point_at_y1_blue; 854 }; 855 856 enum dc_transfer_func_predefined { 857 TRANSFER_FUNCTION_SRGB, 858 TRANSFER_FUNCTION_BT709, 859 TRANSFER_FUNCTION_PQ, 860 TRANSFER_FUNCTION_LINEAR, 861 TRANSFER_FUNCTION_UNITY, 862 TRANSFER_FUNCTION_HLG, 863 TRANSFER_FUNCTION_HLG12, 864 TRANSFER_FUNCTION_GAMMA22, 865 TRANSFER_FUNCTION_GAMMA24, 866 TRANSFER_FUNCTION_GAMMA26 867 }; 868 869 870 struct dc_transfer_func { 871 struct kref refcount; 872 enum dc_transfer_func_type type; 873 enum dc_transfer_func_predefined tf; 874 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 875 uint32_t sdr_ref_white_level; 876 union { 877 struct pwl_params pwl; 878 struct dc_transfer_func_distributed_points tf_pts; 879 }; 880 }; 881 882 883 union dc_3dlut_state { 884 struct { 885 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 886 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 887 uint32_t rmu_mux_num:3; /*index of mux to use*/ 888 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 889 uint32_t mpc_rmu1_mux:4; 890 uint32_t mpc_rmu2_mux:4; 891 uint32_t reserved:15; 892 } bits; 893 uint32_t raw; 894 }; 895 896 897 struct dc_3dlut { 898 struct kref refcount; 899 struct tetrahedral_params lut_3d; 900 struct fixed31_32 hdr_multiplier; 901 union dc_3dlut_state state; 902 }; 903 /* 904 * This structure is filled in by dc_surface_get_status and contains 905 * the last requested address and the currently active address so the called 906 * can determine if there are any outstanding flips 907 */ 908 struct dc_plane_status { 909 struct dc_plane_address requested_address; 910 struct dc_plane_address current_address; 911 bool is_flip_pending; 912 bool is_right_eye; 913 }; 914 915 union surface_update_flags { 916 917 struct { 918 uint32_t addr_update:1; 919 /* Medium updates */ 920 uint32_t dcc_change:1; 921 uint32_t color_space_change:1; 922 uint32_t horizontal_mirror_change:1; 923 uint32_t per_pixel_alpha_change:1; 924 uint32_t global_alpha_change:1; 925 uint32_t hdr_mult:1; 926 uint32_t rotation_change:1; 927 uint32_t swizzle_change:1; 928 uint32_t scaling_change:1; 929 uint32_t position_change:1; 930 uint32_t in_transfer_func_change:1; 931 uint32_t input_csc_change:1; 932 uint32_t coeff_reduction_change:1; 933 uint32_t output_tf_change:1; 934 uint32_t pixel_format_change:1; 935 uint32_t plane_size_change:1; 936 uint32_t gamut_remap_change:1; 937 938 /* Full updates */ 939 uint32_t new_plane:1; 940 uint32_t bpp_change:1; 941 uint32_t gamma_change:1; 942 uint32_t bandwidth_change:1; 943 uint32_t clock_change:1; 944 uint32_t stereo_format_change:1; 945 uint32_t lut_3d:1; 946 uint32_t full_update:1; 947 } bits; 948 949 uint32_t raw; 950 }; 951 952 struct dc_plane_state { 953 struct dc_plane_address address; 954 struct dc_plane_flip_time time; 955 bool triplebuffer_flips; 956 struct scaling_taps scaling_quality; 957 struct rect src_rect; 958 struct rect dst_rect; 959 struct rect clip_rect; 960 961 struct plane_size plane_size; 962 union dc_tiling_info tiling_info; 963 964 struct dc_plane_dcc_param dcc; 965 966 struct dc_gamma *gamma_correction; 967 struct dc_transfer_func *in_transfer_func; 968 struct dc_bias_and_scale *bias_and_scale; 969 struct dc_csc_transform input_csc_color_matrix; 970 struct fixed31_32 coeff_reduction_factor; 971 struct fixed31_32 hdr_mult; 972 struct colorspace_transform gamut_remap_matrix; 973 974 // TODO: No longer used, remove 975 struct dc_hdr_static_metadata hdr_static_ctx; 976 977 enum dc_color_space color_space; 978 979 struct dc_3dlut *lut3d_func; 980 struct dc_transfer_func *in_shaper_func; 981 struct dc_transfer_func *blend_tf; 982 983 #if defined(CONFIG_DRM_AMD_DC_DCN) 984 struct dc_transfer_func *gamcor_tf; 985 #endif 986 enum surface_pixel_format format; 987 enum dc_rotation_angle rotation; 988 enum plane_stereo_format stereo_format; 989 990 bool is_tiling_rotated; 991 bool per_pixel_alpha; 992 bool global_alpha; 993 int global_alpha_value; 994 bool visible; 995 bool flip_immediate; 996 bool horizontal_mirror; 997 int layer_index; 998 999 union surface_update_flags update_flags; 1000 bool flip_int_enabled; 1001 bool skip_manual_trigger; 1002 1003 /* private to DC core */ 1004 struct dc_plane_status status; 1005 struct dc_context *ctx; 1006 1007 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1008 bool force_full_update; 1009 1010 /* private to dc_surface.c */ 1011 enum dc_irq_source irq_source; 1012 struct kref refcount; 1013 }; 1014 1015 struct dc_plane_info { 1016 struct plane_size plane_size; 1017 union dc_tiling_info tiling_info; 1018 struct dc_plane_dcc_param dcc; 1019 enum surface_pixel_format format; 1020 enum dc_rotation_angle rotation; 1021 enum plane_stereo_format stereo_format; 1022 enum dc_color_space color_space; 1023 bool horizontal_mirror; 1024 bool visible; 1025 bool per_pixel_alpha; 1026 bool global_alpha; 1027 int global_alpha_value; 1028 bool input_csc_enabled; 1029 int layer_index; 1030 }; 1031 1032 struct dc_scaling_info { 1033 struct rect src_rect; 1034 struct rect dst_rect; 1035 struct rect clip_rect; 1036 struct scaling_taps scaling_quality; 1037 }; 1038 1039 struct dc_surface_update { 1040 struct dc_plane_state *surface; 1041 1042 /* isr safe update parameters. null means no updates */ 1043 const struct dc_flip_addrs *flip_addr; 1044 const struct dc_plane_info *plane_info; 1045 const struct dc_scaling_info *scaling_info; 1046 struct fixed31_32 hdr_mult; 1047 /* following updates require alloc/sleep/spin that is not isr safe, 1048 * null means no updates 1049 */ 1050 const struct dc_gamma *gamma; 1051 const struct dc_transfer_func *in_transfer_func; 1052 1053 const struct dc_csc_transform *input_csc_color_matrix; 1054 const struct fixed31_32 *coeff_reduction_factor; 1055 const struct dc_transfer_func *func_shaper; 1056 const struct dc_3dlut *lut3d_func; 1057 const struct dc_transfer_func *blend_tf; 1058 const struct colorspace_transform *gamut_remap_matrix; 1059 }; 1060 1061 /* 1062 * Create a new surface with default parameters; 1063 */ 1064 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1065 const struct dc_plane_status *dc_plane_get_status( 1066 const struct dc_plane_state *plane_state); 1067 1068 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1069 void dc_plane_state_release(struct dc_plane_state *plane_state); 1070 1071 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1072 void dc_gamma_release(struct dc_gamma **dc_gamma); 1073 struct dc_gamma *dc_create_gamma(void); 1074 1075 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1076 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1077 struct dc_transfer_func *dc_create_transfer_func(void); 1078 1079 struct dc_3dlut *dc_create_3dlut_func(void); 1080 void dc_3dlut_func_release(struct dc_3dlut *lut); 1081 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1082 /* 1083 * This structure holds a surface address. There could be multiple addresses 1084 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1085 * as frame durations and DCC format can also be set. 1086 */ 1087 struct dc_flip_addrs { 1088 struct dc_plane_address address; 1089 unsigned int flip_timestamp_in_us; 1090 bool flip_immediate; 1091 /* TODO: add flip duration for FreeSync */ 1092 bool triplebuffer_flips; 1093 }; 1094 1095 void dc_post_update_surfaces_to_stream( 1096 struct dc *dc); 1097 1098 #include "dc_stream.h" 1099 1100 /* 1101 * Structure to store surface/stream associations for validation 1102 */ 1103 struct dc_validation_set { 1104 struct dc_stream_state *stream; 1105 struct dc_plane_state *plane_states[MAX_SURFACES]; 1106 uint8_t plane_count; 1107 }; 1108 1109 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1110 const struct dc_sink *sink, 1111 struct dc_crtc_timing *crtc_timing); 1112 1113 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1114 1115 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1116 1117 bool dc_set_generic_gpio_for_stereo(bool enable, 1118 struct gpio_service *gpio_service); 1119 1120 /* 1121 * fast_validate: we return after determining if we can support the new state, 1122 * but before we populate the programming info 1123 */ 1124 enum dc_status dc_validate_global_state( 1125 struct dc *dc, 1126 struct dc_state *new_ctx, 1127 bool fast_validate); 1128 1129 1130 void dc_resource_state_construct( 1131 const struct dc *dc, 1132 struct dc_state *dst_ctx); 1133 1134 #if defined(CONFIG_DRM_AMD_DC_DCN) 1135 bool dc_acquire_release_mpc_3dlut( 1136 struct dc *dc, bool acquire, 1137 struct dc_stream_state *stream, 1138 struct dc_3dlut **lut, 1139 struct dc_transfer_func **shaper); 1140 #endif 1141 1142 void dc_resource_state_copy_construct( 1143 const struct dc_state *src_ctx, 1144 struct dc_state *dst_ctx); 1145 1146 void dc_resource_state_copy_construct_current( 1147 const struct dc *dc, 1148 struct dc_state *dst_ctx); 1149 1150 void dc_resource_state_destruct(struct dc_state *context); 1151 1152 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1153 1154 /* 1155 * TODO update to make it about validation sets 1156 * Set up streams and links associated to drive sinks 1157 * The streams parameter is an absolute set of all active streams. 1158 * 1159 * After this call: 1160 * Phy, Encoder, Timing Generator are programmed and enabled. 1161 * New streams are enabled with blank stream; no memory read. 1162 */ 1163 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1164 1165 struct dc_state *dc_create_state(struct dc *dc); 1166 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1167 void dc_retain_state(struct dc_state *context); 1168 void dc_release_state(struct dc_state *context); 1169 1170 /******************************************************************************* 1171 * Link Interfaces 1172 ******************************************************************************/ 1173 1174 struct dpcd_caps { 1175 union dpcd_rev dpcd_rev; 1176 union max_lane_count max_ln_count; 1177 union max_down_spread max_down_spread; 1178 union dprx_feature dprx_feature; 1179 1180 /* valid only for eDP v1.4 or higher*/ 1181 uint8_t edp_supported_link_rates_count; 1182 enum dc_link_rate edp_supported_link_rates[8]; 1183 1184 /* dongle type (DP converter, CV smart dongle) */ 1185 enum display_dongle_type dongle_type; 1186 /* branch device or sink device */ 1187 bool is_branch_dev; 1188 /* Dongle's downstream count. */ 1189 union sink_count sink_count; 1190 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1191 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1192 struct dc_dongle_caps dongle_caps; 1193 1194 uint32_t sink_dev_id; 1195 int8_t sink_dev_id_str[6]; 1196 int8_t sink_hw_revision; 1197 int8_t sink_fw_revision[2]; 1198 1199 uint32_t branch_dev_id; 1200 int8_t branch_dev_name[6]; 1201 int8_t branch_hw_revision; 1202 int8_t branch_fw_revision[2]; 1203 1204 bool allow_invalid_MSA_timing_param; 1205 bool panel_mode_edp; 1206 bool dpcd_display_control_capable; 1207 bool ext_receiver_cap_field_present; 1208 bool dynamic_backlight_capable_edp; 1209 union dpcd_fec_capability fec_cap; 1210 struct dpcd_dsc_capabilities dsc_caps; 1211 struct dc_lttpr_caps lttpr_caps; 1212 struct psr_caps psr_caps; 1213 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1214 1215 #if defined(CONFIG_DRM_AMD_DC_DCN) 1216 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1217 union dp_main_line_channel_coding_cap channel_coding_cap; 1218 union dp_sink_video_fallback_formats fallback_formats; 1219 union dp_fec_capability1 fec_cap1; 1220 #endif 1221 }; 1222 1223 union dpcd_sink_ext_caps { 1224 struct { 1225 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1226 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1227 */ 1228 uint8_t sdr_aux_backlight_control : 1; 1229 uint8_t hdr_aux_backlight_control : 1; 1230 uint8_t reserved_1 : 2; 1231 uint8_t oled : 1; 1232 uint8_t reserved : 3; 1233 } bits; 1234 uint8_t raw; 1235 }; 1236 1237 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1238 union hdcp_rx_caps { 1239 struct { 1240 uint8_t version; 1241 uint8_t reserved; 1242 struct { 1243 uint8_t repeater : 1; 1244 uint8_t hdcp_capable : 1; 1245 uint8_t reserved : 6; 1246 } byte0; 1247 } fields; 1248 uint8_t raw[3]; 1249 }; 1250 1251 union hdcp_bcaps { 1252 struct { 1253 uint8_t HDCP_CAPABLE:1; 1254 uint8_t REPEATER:1; 1255 uint8_t RESERVED:6; 1256 } bits; 1257 uint8_t raw; 1258 }; 1259 1260 struct hdcp_caps { 1261 union hdcp_rx_caps rx_caps; 1262 union hdcp_bcaps bcaps; 1263 }; 1264 #endif 1265 1266 #include "dc_link.h" 1267 1268 #if defined(CONFIG_DRM_AMD_DC_DCN) 1269 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1270 1271 #endif 1272 /******************************************************************************* 1273 * Sink Interfaces - A sink corresponds to a display output device 1274 ******************************************************************************/ 1275 1276 struct dc_container_id { 1277 // 128bit GUID in binary form 1278 unsigned char guid[16]; 1279 // 8 byte port ID -> ELD.PortID 1280 unsigned int portId[2]; 1281 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1282 unsigned short manufacturerName; 1283 // 2 byte product code -> ELD.ProductCode 1284 unsigned short productCode; 1285 }; 1286 1287 1288 struct dc_sink_dsc_caps { 1289 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1290 // 'false' if they are sink's DSC caps 1291 bool is_virtual_dpcd_dsc; 1292 struct dsc_dec_dpcd_caps dsc_dec_caps; 1293 }; 1294 1295 struct dc_sink_fec_caps { 1296 bool is_rx_fec_supported; 1297 bool is_topology_fec_supported; 1298 }; 1299 1300 /* 1301 * The sink structure contains EDID and other display device properties 1302 */ 1303 struct dc_sink { 1304 enum signal_type sink_signal; 1305 struct dc_edid dc_edid; /* raw edid */ 1306 struct dc_edid_caps edid_caps; /* parse display caps */ 1307 struct dc_container_id *dc_container_id; 1308 uint32_t dongle_max_pix_clk; 1309 void *priv; 1310 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1311 bool converter_disable_audio; 1312 1313 struct dc_sink_dsc_caps dsc_caps; 1314 struct dc_sink_fec_caps fec_caps; 1315 1316 bool is_vsc_sdp_colorimetry_supported; 1317 1318 /* private to DC core */ 1319 struct dc_link *link; 1320 struct dc_context *ctx; 1321 1322 uint32_t sink_id; 1323 1324 /* private to dc_sink.c */ 1325 // refcount must be the last member in dc_sink, since we want the 1326 // sink structure to be logically cloneable up to (but not including) 1327 // refcount 1328 struct kref refcount; 1329 }; 1330 1331 void dc_sink_retain(struct dc_sink *sink); 1332 void dc_sink_release(struct dc_sink *sink); 1333 1334 struct dc_sink_init_data { 1335 enum signal_type sink_signal; 1336 struct dc_link *link; 1337 uint32_t dongle_max_pix_clk; 1338 bool converter_disable_audio; 1339 }; 1340 1341 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1342 1343 /* Newer interfaces */ 1344 struct dc_cursor { 1345 struct dc_plane_address address; 1346 struct dc_cursor_attributes attributes; 1347 }; 1348 1349 1350 /******************************************************************************* 1351 * Interrupt interfaces 1352 ******************************************************************************/ 1353 enum dc_irq_source dc_interrupt_to_irq_source( 1354 struct dc *dc, 1355 uint32_t src_id, 1356 uint32_t ext_id); 1357 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1358 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1359 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1360 struct dc *dc, uint32_t link_index); 1361 1362 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1363 1364 /******************************************************************************* 1365 * Power Interfaces 1366 ******************************************************************************/ 1367 1368 void dc_set_power_state( 1369 struct dc *dc, 1370 enum dc_acpi_cm_power_state power_state); 1371 void dc_resume(struct dc *dc); 1372 1373 void dc_power_down_on_boot(struct dc *dc); 1374 1375 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1376 /* 1377 * HDCP Interfaces 1378 */ 1379 enum hdcp_message_status dc_process_hdcp_msg( 1380 enum signal_type signal, 1381 struct dc_link *link, 1382 struct hdcp_protection_message *message_info); 1383 #endif 1384 bool dc_is_dmcu_initialized(struct dc *dc); 1385 1386 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1387 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1388 #if defined(CONFIG_DRM_AMD_DC_DCN) 1389 1390 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1391 struct dc_cursor_attributes *cursor_attr); 1392 1393 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1394 1395 /* 1396 * blank all streams, and set min and max memory clock to 1397 * lowest and highest DPM level, respectively 1398 */ 1399 void dc_unlock_memory_clock_frequency(struct dc *dc); 1400 1401 /* 1402 * set min memory clock to the min required for current mode, 1403 * max to maxDPM, and unblank streams 1404 */ 1405 void dc_lock_memory_clock_frequency(struct dc *dc); 1406 1407 /* cleanup on driver unload */ 1408 void dc_hardware_release(struct dc *dc); 1409 1410 #endif 1411 1412 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1413 #if defined(CONFIG_DRM_AMD_DC_DCN) 1414 void dc_z10_restore(const struct dc *dc); 1415 void dc_z10_save_init(struct dc *dc); 1416 #endif 1417 1418 bool dc_enable_dmub_notifications(struct dc *dc); 1419 1420 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1421 uint32_t link_index, 1422 struct aux_payload *payload); 1423 1424 /* Get dc link index from dpia port index */ 1425 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1426 uint8_t dpia_port_index); 1427 1428 bool dc_process_dmub_set_config_async(struct dc *dc, 1429 uint32_t link_index, 1430 struct set_config_cmd_payload *payload, 1431 struct dmub_notification *notify); 1432 1433 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1434 uint32_t link_index, 1435 uint8_t mst_alloc_slots, 1436 uint8_t *mst_slots_in_use); 1437 1438 /******************************************************************************* 1439 * DSC Interfaces 1440 ******************************************************************************/ 1441 #include "dc_dsc.h" 1442 1443 /******************************************************************************* 1444 * Disable acc mode Interfaces 1445 ******************************************************************************/ 1446 void dc_disable_accelerated_mode(struct dc *dc); 1447 1448 #endif /* DC_INTERFACE_H_ */ 1449