1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.167" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 // Sizes defined as multiples of 64KB 79 enum det_size { 80 DET_SIZE_DEFAULT = 0, 81 DET_SIZE_192KB = 3, 82 DET_SIZE_256KB = 4, 83 DET_SIZE_320KB = 5, 84 DET_SIZE_384KB = 6 85 }; 86 87 88 struct dc_plane_cap { 89 enum dc_plane_type type; 90 uint32_t blends_with_above : 1; 91 uint32_t blends_with_below : 1; 92 uint32_t per_pixel_alpha : 1; 93 struct { 94 uint32_t argb8888 : 1; 95 uint32_t nv12 : 1; 96 uint32_t fp16 : 1; 97 uint32_t p010 : 1; 98 uint32_t ayuv : 1; 99 } pixel_format_support; 100 // max upscaling factor x1000 101 // upscaling factors are always >= 1 102 // for example, 1080p -> 8K is 4.0, or 4000 raw value 103 struct { 104 uint32_t argb8888; 105 uint32_t nv12; 106 uint32_t fp16; 107 } max_upscale_factor; 108 // max downscale factor x1000 109 // downscale factors are always <= 1 110 // for example, 8K -> 1080p is 0.25, or 250 raw value 111 struct { 112 uint32_t argb8888; 113 uint32_t nv12; 114 uint32_t fp16; 115 } max_downscale_factor; 116 // minimal width/height 117 uint32_t min_width; 118 uint32_t min_height; 119 }; 120 121 // Color management caps (DPP and MPC) 122 struct rom_curve_caps { 123 uint16_t srgb : 1; 124 uint16_t bt2020 : 1; 125 uint16_t gamma2_2 : 1; 126 uint16_t pq : 1; 127 uint16_t hlg : 1; 128 }; 129 130 struct dpp_color_caps { 131 uint16_t dcn_arch : 1; // all DCE generations treated the same 132 // input lut is different than most LUTs, just plain 256-entry lookup 133 uint16_t input_lut_shared : 1; // shared with DGAM 134 uint16_t icsc : 1; 135 uint16_t dgam_ram : 1; 136 uint16_t post_csc : 1; // before gamut remap 137 uint16_t gamma_corr : 1; 138 139 // hdr_mult and gamut remap always available in DPP (in that order) 140 // 3d lut implies shaper LUT, 141 // it may be shared with MPC - check MPC:shared_3d_lut flag 142 uint16_t hw_3d_lut : 1; 143 uint16_t ogam_ram : 1; // blnd gam 144 uint16_t ocsc : 1; 145 uint16_t dgam_rom_for_yuv : 1; 146 struct rom_curve_caps dgam_rom_caps; 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct mpc_color_caps { 151 uint16_t gamut_remap : 1; 152 uint16_t ogam_ram : 1; 153 uint16_t ocsc : 1; 154 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 155 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 156 157 struct rom_curve_caps ogam_rom_caps; 158 }; 159 160 struct dc_color_caps { 161 struct dpp_color_caps dpp; 162 struct mpc_color_caps mpc; 163 }; 164 165 struct dc_caps { 166 uint32_t max_streams; 167 uint32_t max_links; 168 uint32_t max_audios; 169 uint32_t max_slave_planes; 170 uint32_t max_slave_yuv_planes; 171 uint32_t max_slave_rgb_planes; 172 uint32_t max_planes; 173 uint32_t max_downscale_ratio; 174 uint32_t i2c_speed_in_khz; 175 uint32_t i2c_speed_in_khz_hdcp; 176 uint32_t dmdata_alloc_size; 177 unsigned int max_cursor_size; 178 unsigned int max_video_width; 179 unsigned int min_horizontal_blanking_period; 180 int linear_pitch_alignment; 181 bool dcc_const_color; 182 bool dynamic_audio; 183 bool is_apu; 184 bool dual_link_dvi; 185 bool post_blend_color_processing; 186 bool force_dp_tps4_for_cp2520; 187 bool disable_dp_clk_share; 188 bool psp_setup_panel_mode; 189 bool extended_aux_timeout_support; 190 bool dmcub_support; 191 uint32_t num_of_internal_disp; 192 enum dp_protocol_version max_dp_protocol_version; 193 unsigned int mall_size_per_mem_channel; 194 unsigned int mall_size_total; 195 unsigned int cursor_cache_size; 196 struct dc_plane_cap planes[MAX_PLANES]; 197 struct dc_color_caps color; 198 #if defined(CONFIG_DRM_AMD_DC_DCN) 199 bool dp_hpo; 200 bool hdmi_frl_pcon_support; 201 #endif 202 bool edp_dsc_support; 203 bool vbios_lttpr_aware; 204 bool vbios_lttpr_enable; 205 }; 206 207 struct dc_bug_wa { 208 bool no_connect_phy_config; 209 bool dedcn20_305_wa; 210 bool skip_clock_update; 211 bool lt_early_cr_pattern; 212 }; 213 214 struct dc_dcc_surface_param { 215 struct dc_size surface_size; 216 enum surface_pixel_format format; 217 enum swizzle_mode_values swizzle_mode; 218 enum dc_scan_direction scan; 219 }; 220 221 struct dc_dcc_setting { 222 unsigned int max_compressed_blk_size; 223 unsigned int max_uncompressed_blk_size; 224 bool independent_64b_blks; 225 #if defined(CONFIG_DRM_AMD_DC_DCN) 226 //These bitfields to be used starting with DCN 227 struct { 228 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 229 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 230 uint32_t dcc_256_128_128 : 1; //available starting with DCN 231 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 232 } dcc_controls; 233 #endif 234 }; 235 236 struct dc_surface_dcc_cap { 237 union { 238 struct { 239 struct dc_dcc_setting rgb; 240 } grph; 241 242 struct { 243 struct dc_dcc_setting luma; 244 struct dc_dcc_setting chroma; 245 } video; 246 }; 247 248 bool capable; 249 bool const_color_support; 250 }; 251 252 struct dc_static_screen_params { 253 struct { 254 bool force_trigger; 255 bool cursor_update; 256 bool surface_update; 257 bool overlay_update; 258 } triggers; 259 unsigned int num_frames; 260 }; 261 262 263 /* Surface update type is used by dc_update_surfaces_and_stream 264 * The update type is determined at the very beginning of the function based 265 * on parameters passed in and decides how much programming (or updating) is 266 * going to be done during the call. 267 * 268 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 269 * logical calculations or hardware register programming. This update MUST be 270 * ISR safe on windows. Currently fast update will only be used to flip surface 271 * address. 272 * 273 * UPDATE_TYPE_MED is used for slower updates which require significant hw 274 * re-programming however do not affect bandwidth consumption or clock 275 * requirements. At present, this is the level at which front end updates 276 * that do not require us to run bw_calcs happen. These are in/out transfer func 277 * updates, viewport offset changes, recout size changes and pixel depth changes. 278 * This update can be done at ISR, but we want to minimize how often this happens. 279 * 280 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 281 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 282 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 283 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 284 * a full update. This cannot be done at ISR level and should be a rare event. 285 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 286 * underscan we don't expect to see this call at all. 287 */ 288 289 enum surface_update_type { 290 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 291 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 292 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 293 }; 294 295 /* Forward declaration*/ 296 struct dc; 297 struct dc_plane_state; 298 struct dc_state; 299 300 301 struct dc_cap_funcs { 302 bool (*get_dcc_compression_cap)(const struct dc *dc, 303 const struct dc_dcc_surface_param *input, 304 struct dc_surface_dcc_cap *output); 305 }; 306 307 struct link_training_settings; 308 309 #if defined(CONFIG_DRM_AMD_DC_DCN) 310 union allow_lttpr_non_transparent_mode { 311 struct { 312 bool DP1_4A : 1; 313 bool DP2_0 : 1; 314 } bits; 315 unsigned char raw; 316 }; 317 #endif 318 /* Structure to hold configuration flags set by dm at dc creation. */ 319 struct dc_config { 320 bool gpu_vm_support; 321 bool disable_disp_pll_sharing; 322 bool fbc_support; 323 bool disable_fractional_pwm; 324 bool allow_seamless_boot_optimization; 325 bool power_down_display_on_boot; 326 bool edp_not_connected; 327 bool edp_no_power_sequencing; 328 bool force_enum_edp; 329 bool forced_clocks; 330 #if defined(CONFIG_DRM_AMD_DC_DCN) 331 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 332 #else 333 bool allow_lttpr_non_transparent_mode; 334 #endif 335 bool multi_mon_pp_mclk_switch; 336 bool disable_dmcu; 337 bool enable_4to1MPC; 338 bool enable_windowed_mpo_odm; 339 bool allow_edp_hotplug_detection; 340 #if defined(CONFIG_DRM_AMD_DC_DCN) 341 bool clamp_min_dcfclk; 342 #endif 343 uint64_t vblank_alignment_dto_params; 344 uint8_t vblank_alignment_max_frame_time_diff; 345 bool is_asymmetric_memory; 346 bool is_single_rank_dimm; 347 bool use_pipe_ctx_sync_logic; 348 }; 349 350 enum visual_confirm { 351 VISUAL_CONFIRM_DISABLE = 0, 352 VISUAL_CONFIRM_SURFACE = 1, 353 VISUAL_CONFIRM_HDR = 2, 354 VISUAL_CONFIRM_MPCTREE = 4, 355 VISUAL_CONFIRM_PSR = 5, 356 VISUAL_CONFIRM_SWIZZLE = 9, 357 }; 358 359 enum dc_psr_power_opts { 360 psr_power_opt_invalid = 0x0, 361 psr_power_opt_smu_opt_static_screen = 0x1, 362 psr_power_opt_z10_static_screen = 0x10, 363 }; 364 365 enum dcc_option { 366 DCC_ENABLE = 0, 367 DCC_DISABLE = 1, 368 DCC_HALF_REQ_DISALBE = 2, 369 }; 370 371 enum pipe_split_policy { 372 MPC_SPLIT_DYNAMIC = 0, 373 MPC_SPLIT_AVOID = 1, 374 MPC_SPLIT_AVOID_MULT_DISP = 2, 375 }; 376 377 enum wm_report_mode { 378 WM_REPORT_DEFAULT = 0, 379 WM_REPORT_OVERRIDE = 1, 380 }; 381 enum dtm_pstate{ 382 dtm_level_p0 = 0,/*highest voltage*/ 383 dtm_level_p1, 384 dtm_level_p2, 385 dtm_level_p3, 386 dtm_level_p4,/*when active_display_count = 0*/ 387 }; 388 389 enum dcn_pwr_state { 390 DCN_PWR_STATE_UNKNOWN = -1, 391 DCN_PWR_STATE_MISSION_MODE = 0, 392 DCN_PWR_STATE_LOW_POWER = 3, 393 }; 394 395 #if defined(CONFIG_DRM_AMD_DC_DCN) 396 enum dcn_zstate_support_state { 397 DCN_ZSTATE_SUPPORT_UNKNOWN, 398 DCN_ZSTATE_SUPPORT_ALLOW, 399 DCN_ZSTATE_SUPPORT_DISALLOW, 400 }; 401 #endif 402 /* 403 * For any clocks that may differ per pipe 404 * only the max is stored in this structure 405 */ 406 struct dc_clocks { 407 int dispclk_khz; 408 int actual_dispclk_khz; 409 int dppclk_khz; 410 int actual_dppclk_khz; 411 int disp_dpp_voltage_level_khz; 412 int dcfclk_khz; 413 int socclk_khz; 414 int dcfclk_deep_sleep_khz; 415 int fclk_khz; 416 int phyclk_khz; 417 int dramclk_khz; 418 bool p_state_change_support; 419 #if defined(CONFIG_DRM_AMD_DC_DCN) 420 enum dcn_zstate_support_state zstate_support; 421 bool dtbclk_en; 422 #endif 423 enum dcn_pwr_state pwr_state; 424 /* 425 * Elements below are not compared for the purposes of 426 * optimization required 427 */ 428 bool prev_p_state_change_support; 429 enum dtm_pstate dtm_level; 430 int max_supported_dppclk_khz; 431 int max_supported_dispclk_khz; 432 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 433 int bw_dispclk_khz; 434 }; 435 436 struct dc_bw_validation_profile { 437 bool enable; 438 439 unsigned long long total_ticks; 440 unsigned long long voltage_level_ticks; 441 unsigned long long watermark_ticks; 442 unsigned long long rq_dlg_ticks; 443 444 unsigned long long total_count; 445 unsigned long long skip_fast_count; 446 unsigned long long skip_pass_count; 447 unsigned long long skip_fail_count; 448 }; 449 450 #define BW_VAL_TRACE_SETUP() \ 451 unsigned long long end_tick = 0; \ 452 unsigned long long voltage_level_tick = 0; \ 453 unsigned long long watermark_tick = 0; \ 454 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 455 dm_get_timestamp(dc->ctx) : 0 456 457 #define BW_VAL_TRACE_COUNT() \ 458 if (dc->debug.bw_val_profile.enable) \ 459 dc->debug.bw_val_profile.total_count++ 460 461 #define BW_VAL_TRACE_SKIP(status) \ 462 if (dc->debug.bw_val_profile.enable) { \ 463 if (!voltage_level_tick) \ 464 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 465 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 466 } 467 468 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 469 if (dc->debug.bw_val_profile.enable) \ 470 voltage_level_tick = dm_get_timestamp(dc->ctx) 471 472 #define BW_VAL_TRACE_END_WATERMARKS() \ 473 if (dc->debug.bw_val_profile.enable) \ 474 watermark_tick = dm_get_timestamp(dc->ctx) 475 476 #define BW_VAL_TRACE_FINISH() \ 477 if (dc->debug.bw_val_profile.enable) { \ 478 end_tick = dm_get_timestamp(dc->ctx); \ 479 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 480 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 481 if (watermark_tick) { \ 482 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 483 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 484 } \ 485 } 486 487 union mem_low_power_enable_options { 488 struct { 489 bool vga: 1; 490 bool i2c: 1; 491 bool dmcu: 1; 492 bool dscl: 1; 493 bool cm: 1; 494 bool mpc: 1; 495 bool optc: 1; 496 bool vpg: 1; 497 bool afmt: 1; 498 } bits; 499 uint32_t u32All; 500 }; 501 502 union root_clock_optimization_options { 503 struct { 504 bool dpp: 1; 505 bool dsc: 1; 506 bool hdmistream: 1; 507 bool hdmichar: 1; 508 bool dpstream: 1; 509 bool symclk32_se: 1; 510 bool symclk32_le: 1; 511 bool symclk_fe: 1; 512 bool physymclk: 1; 513 bool dpiasymclk: 1; 514 uint32_t reserved: 22; 515 } bits; 516 uint32_t u32All; 517 }; 518 519 union dpia_debug_options { 520 struct { 521 uint32_t disable_dpia:1; 522 uint32_t force_non_lttpr:1; 523 uint32_t extend_aux_rd_interval:1; 524 uint32_t disable_mst_dsc_work_around:1; 525 uint32_t hpd_delay_in_ms:12; 526 uint32_t reserved:16; 527 } bits; 528 uint32_t raw; 529 }; 530 531 struct dc_debug_data { 532 uint32_t ltFailCount; 533 uint32_t i2cErrorCount; 534 uint32_t auxErrorCount; 535 }; 536 537 struct dc_phy_addr_space_config { 538 struct { 539 uint64_t start_addr; 540 uint64_t end_addr; 541 uint64_t fb_top; 542 uint64_t fb_offset; 543 uint64_t fb_base; 544 uint64_t agp_top; 545 uint64_t agp_bot; 546 uint64_t agp_base; 547 } system_aperture; 548 549 struct { 550 uint64_t page_table_start_addr; 551 uint64_t page_table_end_addr; 552 uint64_t page_table_base_addr; 553 bool base_addr_is_mc_addr; 554 } gart_config; 555 556 bool valid; 557 bool is_hvm_enabled; 558 uint64_t page_table_default_page_addr; 559 }; 560 561 struct dc_virtual_addr_space_config { 562 uint64_t page_table_base_addr; 563 uint64_t page_table_start_addr; 564 uint64_t page_table_end_addr; 565 uint32_t page_table_block_size_in_bytes; 566 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 567 }; 568 569 struct dc_bounding_box_overrides { 570 int sr_exit_time_ns; 571 int sr_enter_plus_exit_time_ns; 572 int urgent_latency_ns; 573 int percent_of_ideal_drambw; 574 int dram_clock_change_latency_ns; 575 int dummy_clock_change_latency_ns; 576 /* This forces a hard min on the DCFCLK we use 577 * for DML. Unlike the debug option for forcing 578 * DCFCLK, this override affects watermark calculations 579 */ 580 int min_dcfclk_mhz; 581 }; 582 583 struct dc_state; 584 struct resource_pool; 585 struct dce_hwseq; 586 587 struct dc_debug_options { 588 bool native422_support; 589 bool disable_dsc; 590 enum visual_confirm visual_confirm; 591 int visual_confirm_rect_height; 592 593 bool sanity_checks; 594 bool max_disp_clk; 595 bool surface_trace; 596 bool timing_trace; 597 bool clock_trace; 598 bool validation_trace; 599 bool bandwidth_calcs_trace; 600 int max_downscale_src_width; 601 602 /* stutter efficiency related */ 603 bool disable_stutter; 604 bool use_max_lb; 605 enum dcc_option disable_dcc; 606 enum pipe_split_policy pipe_split_policy; 607 bool force_single_disp_pipe_split; 608 bool voltage_align_fclk; 609 bool disable_min_fclk; 610 611 bool disable_dfs_bypass; 612 bool disable_dpp_power_gate; 613 bool disable_hubp_power_gate; 614 bool disable_dsc_power_gate; 615 int dsc_min_slice_height_override; 616 int dsc_bpp_increment_div; 617 bool disable_pplib_wm_range; 618 enum wm_report_mode pplib_wm_report_mode; 619 unsigned int min_disp_clk_khz; 620 unsigned int min_dpp_clk_khz; 621 unsigned int min_dram_clk_khz; 622 int sr_exit_time_dpm0_ns; 623 int sr_enter_plus_exit_time_dpm0_ns; 624 int sr_exit_time_ns; 625 int sr_enter_plus_exit_time_ns; 626 int urgent_latency_ns; 627 uint32_t underflow_assert_delay_us; 628 int percent_of_ideal_drambw; 629 int dram_clock_change_latency_ns; 630 bool optimized_watermark; 631 int always_scale; 632 bool disable_pplib_clock_request; 633 bool disable_clock_gate; 634 bool disable_mem_low_power; 635 #if defined(CONFIG_DRM_AMD_DC_DCN) 636 bool pstate_enabled; 637 #endif 638 bool disable_dmcu; 639 bool disable_psr; 640 bool force_abm_enable; 641 bool disable_stereo_support; 642 bool vsr_support; 643 bool performance_trace; 644 bool az_endpoint_mute_only; 645 bool always_use_regamma; 646 bool recovery_enabled; 647 bool avoid_vbios_exec_table; 648 bool scl_reset_length10; 649 bool hdmi20_disable; 650 bool skip_detection_link_training; 651 uint32_t edid_read_retry_times; 652 bool remove_disconnect_edp; 653 unsigned int force_odm_combine; //bit vector based on otg inst 654 #if defined(CONFIG_DRM_AMD_DC_DCN) 655 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 656 bool disable_z9_mpc; 657 #endif 658 unsigned int force_fclk_khz; 659 bool enable_tri_buf; 660 bool dmub_offload_enabled; 661 bool dmcub_emulation; 662 #if defined(CONFIG_DRM_AMD_DC_DCN) 663 bool disable_idle_power_optimizations; 664 unsigned int mall_size_override; 665 unsigned int mall_additional_timer_percent; 666 bool mall_error_as_fatal; 667 #endif 668 bool dmub_command_table; /* for testing only */ 669 struct dc_bw_validation_profile bw_val_profile; 670 bool disable_fec; 671 bool disable_48mhz_pwrdwn; 672 /* This forces a hard min on the DCFCLK requested to SMU/PP 673 * watermarks are not affected. 674 */ 675 unsigned int force_min_dcfclk_mhz; 676 #if defined(CONFIG_DRM_AMD_DC_DCN) 677 int dwb_fi_phase; 678 #endif 679 bool disable_timing_sync; 680 bool cm_in_bypass; 681 int force_clock_mode;/*every mode change.*/ 682 683 bool disable_dram_clock_change_vactive_support; 684 bool validate_dml_output; 685 bool enable_dmcub_surface_flip; 686 bool usbc_combo_phy_reset_wa; 687 bool disable_dsc_edp; 688 unsigned int force_dsc_edp_policy; 689 bool enable_dram_clock_change_one_display_vactive; 690 #if defined(CONFIG_DRM_AMD_DC_DCN) 691 /* TODO - remove once tested */ 692 bool legacy_dp2_lt; 693 bool set_mst_en_for_sst; 694 bool disable_uhbr; 695 bool force_dp2_lt_fallback_method; 696 #endif 697 union mem_low_power_enable_options enable_mem_low_power; 698 union root_clock_optimization_options root_clock_optimization; 699 bool hpo_optimization; 700 bool force_vblank_alignment; 701 702 /* Enable dmub aux for legacy ddc */ 703 bool enable_dmub_aux_for_legacy_ddc; 704 bool optimize_edp_link_rate; /* eDP ILR */ 705 /* FEC/PSR1 sequence enable delay in 100us */ 706 uint8_t fec_enable_delay_in100us; 707 bool enable_driver_sequence_debug; 708 enum det_size crb_alloc_policy; 709 int crb_alloc_policy_min_disp_count; 710 #if defined(CONFIG_DRM_AMD_DC_DCN) 711 bool disable_z10; 712 bool enable_sw_cntl_psr; 713 union dpia_debug_options dpia_debug; 714 #endif 715 bool apply_vendor_specific_lttpr_wa; 716 }; 717 718 struct gpu_info_soc_bounding_box_v1_0; 719 struct dc { 720 struct dc_debug_options debug; 721 struct dc_versions versions; 722 struct dc_caps caps; 723 struct dc_cap_funcs cap_funcs; 724 struct dc_config config; 725 struct dc_bounding_box_overrides bb_overrides; 726 struct dc_bug_wa work_arounds; 727 struct dc_context *ctx; 728 struct dc_phy_addr_space_config vm_pa_config; 729 730 uint8_t link_count; 731 struct dc_link *links[MAX_PIPES * 2]; 732 733 struct dc_state *current_state; 734 struct resource_pool *res_pool; 735 736 struct clk_mgr *clk_mgr; 737 738 /* Display Engine Clock levels */ 739 struct dm_pp_clock_levels sclk_lvls; 740 741 /* Inputs into BW and WM calculations. */ 742 struct bw_calcs_dceip *bw_dceip; 743 struct bw_calcs_vbios *bw_vbios; 744 #ifdef CONFIG_DRM_AMD_DC_DCN 745 struct dcn_soc_bounding_box *dcn_soc; 746 struct dcn_ip_params *dcn_ip; 747 struct display_mode_lib dml; 748 #endif 749 750 /* HW functions */ 751 struct hw_sequencer_funcs hwss; 752 struct dce_hwseq *hwseq; 753 754 /* Require to optimize clocks and bandwidth for added/removed planes */ 755 bool optimized_required; 756 bool wm_optimized_required; 757 #if defined(CONFIG_DRM_AMD_DC_DCN) 758 bool idle_optimizations_allowed; 759 #endif 760 #if defined(CONFIG_DRM_AMD_DC_DCN) 761 bool enable_c20_dtm_b0; 762 #endif 763 764 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 765 766 /* FBC compressor */ 767 struct compressor *fbc_compressor; 768 769 struct dc_debug_data debug_data; 770 struct dpcd_vendor_signature vendor_signature; 771 772 const char *build_id; 773 struct vm_helper *vm_helper; 774 }; 775 776 enum frame_buffer_mode { 777 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 778 FRAME_BUFFER_MODE_ZFB_ONLY, 779 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 780 } ; 781 782 struct dchub_init_data { 783 int64_t zfb_phys_addr_base; 784 int64_t zfb_mc_base_addr; 785 uint64_t zfb_size_in_byte; 786 enum frame_buffer_mode fb_mode; 787 bool dchub_initialzied; 788 bool dchub_info_valid; 789 }; 790 791 struct dc_init_data { 792 struct hw_asic_id asic_id; 793 void *driver; /* ctx */ 794 struct cgs_device *cgs_device; 795 struct dc_bounding_box_overrides bb_overrides; 796 797 int num_virtual_links; 798 /* 799 * If 'vbios_override' not NULL, it will be called instead 800 * of the real VBIOS. Intended use is Diagnostics on FPGA. 801 */ 802 struct dc_bios *vbios_override; 803 enum dce_environment dce_environment; 804 805 struct dmub_offload_funcs *dmub_if; 806 struct dc_reg_helper_state *dmub_offload; 807 808 struct dc_config flags; 809 uint64_t log_mask; 810 811 struct dpcd_vendor_signature vendor_signature; 812 #if defined(CONFIG_DRM_AMD_DC_DCN) 813 bool force_smu_not_present; 814 #endif 815 }; 816 817 struct dc_callback_init { 818 #ifdef CONFIG_DRM_AMD_DC_HDCP 819 struct cp_psp cp_psp; 820 #else 821 uint8_t reserved; 822 #endif 823 }; 824 825 struct dc *dc_create(const struct dc_init_data *init_params); 826 void dc_hardware_init(struct dc *dc); 827 828 int dc_get_vmid_use_vector(struct dc *dc); 829 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 830 /* Returns the number of vmids supported */ 831 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 832 void dc_init_callbacks(struct dc *dc, 833 const struct dc_callback_init *init_params); 834 void dc_deinit_callbacks(struct dc *dc); 835 void dc_destroy(struct dc **dc); 836 837 /******************************************************************************* 838 * Surface Interfaces 839 ******************************************************************************/ 840 841 enum { 842 TRANSFER_FUNC_POINTS = 1025 843 }; 844 845 struct dc_hdr_static_metadata { 846 /* display chromaticities and white point in units of 0.00001 */ 847 unsigned int chromaticity_green_x; 848 unsigned int chromaticity_green_y; 849 unsigned int chromaticity_blue_x; 850 unsigned int chromaticity_blue_y; 851 unsigned int chromaticity_red_x; 852 unsigned int chromaticity_red_y; 853 unsigned int chromaticity_white_point_x; 854 unsigned int chromaticity_white_point_y; 855 856 uint32_t min_luminance; 857 uint32_t max_luminance; 858 uint32_t maximum_content_light_level; 859 uint32_t maximum_frame_average_light_level; 860 }; 861 862 enum dc_transfer_func_type { 863 TF_TYPE_PREDEFINED, 864 TF_TYPE_DISTRIBUTED_POINTS, 865 TF_TYPE_BYPASS, 866 TF_TYPE_HWPWL 867 }; 868 869 struct dc_transfer_func_distributed_points { 870 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 871 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 872 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 873 874 uint16_t end_exponent; 875 uint16_t x_point_at_y1_red; 876 uint16_t x_point_at_y1_green; 877 uint16_t x_point_at_y1_blue; 878 }; 879 880 enum dc_transfer_func_predefined { 881 TRANSFER_FUNCTION_SRGB, 882 TRANSFER_FUNCTION_BT709, 883 TRANSFER_FUNCTION_PQ, 884 TRANSFER_FUNCTION_LINEAR, 885 TRANSFER_FUNCTION_UNITY, 886 TRANSFER_FUNCTION_HLG, 887 TRANSFER_FUNCTION_HLG12, 888 TRANSFER_FUNCTION_GAMMA22, 889 TRANSFER_FUNCTION_GAMMA24, 890 TRANSFER_FUNCTION_GAMMA26 891 }; 892 893 894 struct dc_transfer_func { 895 struct kref refcount; 896 enum dc_transfer_func_type type; 897 enum dc_transfer_func_predefined tf; 898 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 899 uint32_t sdr_ref_white_level; 900 union { 901 struct pwl_params pwl; 902 struct dc_transfer_func_distributed_points tf_pts; 903 }; 904 }; 905 906 907 union dc_3dlut_state { 908 struct { 909 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 910 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 911 uint32_t rmu_mux_num:3; /*index of mux to use*/ 912 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 913 uint32_t mpc_rmu1_mux:4; 914 uint32_t mpc_rmu2_mux:4; 915 uint32_t reserved:15; 916 } bits; 917 uint32_t raw; 918 }; 919 920 921 struct dc_3dlut { 922 struct kref refcount; 923 struct tetrahedral_params lut_3d; 924 struct fixed31_32 hdr_multiplier; 925 union dc_3dlut_state state; 926 }; 927 /* 928 * This structure is filled in by dc_surface_get_status and contains 929 * the last requested address and the currently active address so the called 930 * can determine if there are any outstanding flips 931 */ 932 struct dc_plane_status { 933 struct dc_plane_address requested_address; 934 struct dc_plane_address current_address; 935 bool is_flip_pending; 936 bool is_right_eye; 937 }; 938 939 union surface_update_flags { 940 941 struct { 942 uint32_t addr_update:1; 943 /* Medium updates */ 944 uint32_t dcc_change:1; 945 uint32_t color_space_change:1; 946 uint32_t horizontal_mirror_change:1; 947 uint32_t per_pixel_alpha_change:1; 948 uint32_t global_alpha_change:1; 949 uint32_t hdr_mult:1; 950 uint32_t rotation_change:1; 951 uint32_t swizzle_change:1; 952 uint32_t scaling_change:1; 953 uint32_t position_change:1; 954 uint32_t in_transfer_func_change:1; 955 uint32_t input_csc_change:1; 956 uint32_t coeff_reduction_change:1; 957 uint32_t output_tf_change:1; 958 uint32_t pixel_format_change:1; 959 uint32_t plane_size_change:1; 960 uint32_t gamut_remap_change:1; 961 962 /* Full updates */ 963 uint32_t new_plane:1; 964 uint32_t bpp_change:1; 965 uint32_t gamma_change:1; 966 uint32_t bandwidth_change:1; 967 uint32_t clock_change:1; 968 uint32_t stereo_format_change:1; 969 uint32_t lut_3d:1; 970 uint32_t full_update:1; 971 } bits; 972 973 uint32_t raw; 974 }; 975 976 struct dc_plane_state { 977 struct dc_plane_address address; 978 struct dc_plane_flip_time time; 979 bool triplebuffer_flips; 980 struct scaling_taps scaling_quality; 981 struct rect src_rect; 982 struct rect dst_rect; 983 struct rect clip_rect; 984 985 struct plane_size plane_size; 986 union dc_tiling_info tiling_info; 987 988 struct dc_plane_dcc_param dcc; 989 990 struct dc_gamma *gamma_correction; 991 struct dc_transfer_func *in_transfer_func; 992 struct dc_bias_and_scale *bias_and_scale; 993 struct dc_csc_transform input_csc_color_matrix; 994 struct fixed31_32 coeff_reduction_factor; 995 struct fixed31_32 hdr_mult; 996 struct colorspace_transform gamut_remap_matrix; 997 998 // TODO: No longer used, remove 999 struct dc_hdr_static_metadata hdr_static_ctx; 1000 1001 enum dc_color_space color_space; 1002 1003 struct dc_3dlut *lut3d_func; 1004 struct dc_transfer_func *in_shaper_func; 1005 struct dc_transfer_func *blend_tf; 1006 1007 #if defined(CONFIG_DRM_AMD_DC_DCN) 1008 struct dc_transfer_func *gamcor_tf; 1009 #endif 1010 enum surface_pixel_format format; 1011 enum dc_rotation_angle rotation; 1012 enum plane_stereo_format stereo_format; 1013 1014 bool is_tiling_rotated; 1015 bool per_pixel_alpha; 1016 bool global_alpha; 1017 int global_alpha_value; 1018 bool visible; 1019 bool flip_immediate; 1020 bool horizontal_mirror; 1021 int layer_index; 1022 1023 union surface_update_flags update_flags; 1024 bool flip_int_enabled; 1025 bool skip_manual_trigger; 1026 1027 /* private to DC core */ 1028 struct dc_plane_status status; 1029 struct dc_context *ctx; 1030 1031 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1032 bool force_full_update; 1033 1034 /* private to dc_surface.c */ 1035 enum dc_irq_source irq_source; 1036 struct kref refcount; 1037 }; 1038 1039 struct dc_plane_info { 1040 struct plane_size plane_size; 1041 union dc_tiling_info tiling_info; 1042 struct dc_plane_dcc_param dcc; 1043 enum surface_pixel_format format; 1044 enum dc_rotation_angle rotation; 1045 enum plane_stereo_format stereo_format; 1046 enum dc_color_space color_space; 1047 bool horizontal_mirror; 1048 bool visible; 1049 bool per_pixel_alpha; 1050 bool global_alpha; 1051 int global_alpha_value; 1052 bool input_csc_enabled; 1053 int layer_index; 1054 }; 1055 1056 struct dc_scaling_info { 1057 struct rect src_rect; 1058 struct rect dst_rect; 1059 struct rect clip_rect; 1060 struct scaling_taps scaling_quality; 1061 }; 1062 1063 struct dc_surface_update { 1064 struct dc_plane_state *surface; 1065 1066 /* isr safe update parameters. null means no updates */ 1067 const struct dc_flip_addrs *flip_addr; 1068 const struct dc_plane_info *plane_info; 1069 const struct dc_scaling_info *scaling_info; 1070 struct fixed31_32 hdr_mult; 1071 /* following updates require alloc/sleep/spin that is not isr safe, 1072 * null means no updates 1073 */ 1074 const struct dc_gamma *gamma; 1075 const struct dc_transfer_func *in_transfer_func; 1076 1077 const struct dc_csc_transform *input_csc_color_matrix; 1078 const struct fixed31_32 *coeff_reduction_factor; 1079 const struct dc_transfer_func *func_shaper; 1080 const struct dc_3dlut *lut3d_func; 1081 const struct dc_transfer_func *blend_tf; 1082 const struct colorspace_transform *gamut_remap_matrix; 1083 }; 1084 1085 /* 1086 * Create a new surface with default parameters; 1087 */ 1088 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1089 const struct dc_plane_status *dc_plane_get_status( 1090 const struct dc_plane_state *plane_state); 1091 1092 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1093 void dc_plane_state_release(struct dc_plane_state *plane_state); 1094 1095 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1096 void dc_gamma_release(struct dc_gamma **dc_gamma); 1097 struct dc_gamma *dc_create_gamma(void); 1098 1099 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1100 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1101 struct dc_transfer_func *dc_create_transfer_func(void); 1102 1103 struct dc_3dlut *dc_create_3dlut_func(void); 1104 void dc_3dlut_func_release(struct dc_3dlut *lut); 1105 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1106 /* 1107 * This structure holds a surface address. There could be multiple addresses 1108 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1109 * as frame durations and DCC format can also be set. 1110 */ 1111 struct dc_flip_addrs { 1112 struct dc_plane_address address; 1113 unsigned int flip_timestamp_in_us; 1114 bool flip_immediate; 1115 /* TODO: add flip duration for FreeSync */ 1116 bool triplebuffer_flips; 1117 }; 1118 1119 void dc_post_update_surfaces_to_stream( 1120 struct dc *dc); 1121 1122 #include "dc_stream.h" 1123 1124 /* 1125 * Structure to store surface/stream associations for validation 1126 */ 1127 struct dc_validation_set { 1128 struct dc_stream_state *stream; 1129 struct dc_plane_state *plane_states[MAX_SURFACES]; 1130 uint8_t plane_count; 1131 }; 1132 1133 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1134 const struct dc_sink *sink, 1135 struct dc_crtc_timing *crtc_timing); 1136 1137 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1138 1139 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1140 1141 bool dc_set_generic_gpio_for_stereo(bool enable, 1142 struct gpio_service *gpio_service); 1143 1144 /* 1145 * fast_validate: we return after determining if we can support the new state, 1146 * but before we populate the programming info 1147 */ 1148 enum dc_status dc_validate_global_state( 1149 struct dc *dc, 1150 struct dc_state *new_ctx, 1151 bool fast_validate); 1152 1153 1154 void dc_resource_state_construct( 1155 const struct dc *dc, 1156 struct dc_state *dst_ctx); 1157 1158 #if defined(CONFIG_DRM_AMD_DC_DCN) 1159 bool dc_acquire_release_mpc_3dlut( 1160 struct dc *dc, bool acquire, 1161 struct dc_stream_state *stream, 1162 struct dc_3dlut **lut, 1163 struct dc_transfer_func **shaper); 1164 #endif 1165 1166 void dc_resource_state_copy_construct( 1167 const struct dc_state *src_ctx, 1168 struct dc_state *dst_ctx); 1169 1170 void dc_resource_state_copy_construct_current( 1171 const struct dc *dc, 1172 struct dc_state *dst_ctx); 1173 1174 void dc_resource_state_destruct(struct dc_state *context); 1175 1176 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1177 1178 /* 1179 * TODO update to make it about validation sets 1180 * Set up streams and links associated to drive sinks 1181 * The streams parameter is an absolute set of all active streams. 1182 * 1183 * After this call: 1184 * Phy, Encoder, Timing Generator are programmed and enabled. 1185 * New streams are enabled with blank stream; no memory read. 1186 */ 1187 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1188 1189 struct dc_state *dc_create_state(struct dc *dc); 1190 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1191 void dc_retain_state(struct dc_state *context); 1192 void dc_release_state(struct dc_state *context); 1193 1194 /******************************************************************************* 1195 * Link Interfaces 1196 ******************************************************************************/ 1197 1198 struct dpcd_caps { 1199 union dpcd_rev dpcd_rev; 1200 union max_lane_count max_ln_count; 1201 union max_down_spread max_down_spread; 1202 union dprx_feature dprx_feature; 1203 1204 /* valid only for eDP v1.4 or higher*/ 1205 uint8_t edp_supported_link_rates_count; 1206 enum dc_link_rate edp_supported_link_rates[8]; 1207 1208 /* dongle type (DP converter, CV smart dongle) */ 1209 enum display_dongle_type dongle_type; 1210 /* branch device or sink device */ 1211 bool is_branch_dev; 1212 /* Dongle's downstream count. */ 1213 union sink_count sink_count; 1214 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1215 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1216 struct dc_dongle_caps dongle_caps; 1217 1218 uint32_t sink_dev_id; 1219 int8_t sink_dev_id_str[6]; 1220 int8_t sink_hw_revision; 1221 int8_t sink_fw_revision[2]; 1222 1223 uint32_t branch_dev_id; 1224 int8_t branch_dev_name[6]; 1225 int8_t branch_hw_revision; 1226 int8_t branch_fw_revision[2]; 1227 1228 bool allow_invalid_MSA_timing_param; 1229 bool panel_mode_edp; 1230 bool dpcd_display_control_capable; 1231 bool ext_receiver_cap_field_present; 1232 bool dynamic_backlight_capable_edp; 1233 union dpcd_fec_capability fec_cap; 1234 struct dpcd_dsc_capabilities dsc_caps; 1235 struct dc_lttpr_caps lttpr_caps; 1236 struct psr_caps psr_caps; 1237 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1238 1239 #if defined(CONFIG_DRM_AMD_DC_DCN) 1240 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1241 union dp_main_line_channel_coding_cap channel_coding_cap; 1242 union dp_sink_video_fallback_formats fallback_formats; 1243 union dp_fec_capability1 fec_cap1; 1244 #endif 1245 }; 1246 1247 union dpcd_sink_ext_caps { 1248 struct { 1249 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1250 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1251 */ 1252 uint8_t sdr_aux_backlight_control : 1; 1253 uint8_t hdr_aux_backlight_control : 1; 1254 uint8_t reserved_1 : 2; 1255 uint8_t oled : 1; 1256 uint8_t reserved : 3; 1257 } bits; 1258 uint8_t raw; 1259 }; 1260 1261 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1262 union hdcp_rx_caps { 1263 struct { 1264 uint8_t version; 1265 uint8_t reserved; 1266 struct { 1267 uint8_t repeater : 1; 1268 uint8_t hdcp_capable : 1; 1269 uint8_t reserved : 6; 1270 } byte0; 1271 } fields; 1272 uint8_t raw[3]; 1273 }; 1274 1275 union hdcp_bcaps { 1276 struct { 1277 uint8_t HDCP_CAPABLE:1; 1278 uint8_t REPEATER:1; 1279 uint8_t RESERVED:6; 1280 } bits; 1281 uint8_t raw; 1282 }; 1283 1284 struct hdcp_caps { 1285 union hdcp_rx_caps rx_caps; 1286 union hdcp_bcaps bcaps; 1287 }; 1288 #endif 1289 1290 #include "dc_link.h" 1291 1292 #if defined(CONFIG_DRM_AMD_DC_DCN) 1293 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1294 1295 #endif 1296 /******************************************************************************* 1297 * Sink Interfaces - A sink corresponds to a display output device 1298 ******************************************************************************/ 1299 1300 struct dc_container_id { 1301 // 128bit GUID in binary form 1302 unsigned char guid[16]; 1303 // 8 byte port ID -> ELD.PortID 1304 unsigned int portId[2]; 1305 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1306 unsigned short manufacturerName; 1307 // 2 byte product code -> ELD.ProductCode 1308 unsigned short productCode; 1309 }; 1310 1311 1312 struct dc_sink_dsc_caps { 1313 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1314 // 'false' if they are sink's DSC caps 1315 bool is_virtual_dpcd_dsc; 1316 #if defined(CONFIG_DRM_AMD_DC_DCN) 1317 // 'true' if MST topology supports DSC passthrough for sink 1318 // 'false' if MST topology does not support DSC passthrough 1319 bool is_dsc_passthrough_supported; 1320 #endif 1321 struct dsc_dec_dpcd_caps dsc_dec_caps; 1322 }; 1323 1324 struct dc_sink_fec_caps { 1325 bool is_rx_fec_supported; 1326 bool is_topology_fec_supported; 1327 }; 1328 1329 /* 1330 * The sink structure contains EDID and other display device properties 1331 */ 1332 struct dc_sink { 1333 enum signal_type sink_signal; 1334 struct dc_edid dc_edid; /* raw edid */ 1335 struct dc_edid_caps edid_caps; /* parse display caps */ 1336 struct dc_container_id *dc_container_id; 1337 uint32_t dongle_max_pix_clk; 1338 void *priv; 1339 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1340 bool converter_disable_audio; 1341 1342 struct dc_sink_dsc_caps dsc_caps; 1343 struct dc_sink_fec_caps fec_caps; 1344 1345 bool is_vsc_sdp_colorimetry_supported; 1346 1347 /* private to DC core */ 1348 struct dc_link *link; 1349 struct dc_context *ctx; 1350 1351 uint32_t sink_id; 1352 1353 /* private to dc_sink.c */ 1354 // refcount must be the last member in dc_sink, since we want the 1355 // sink structure to be logically cloneable up to (but not including) 1356 // refcount 1357 struct kref refcount; 1358 }; 1359 1360 void dc_sink_retain(struct dc_sink *sink); 1361 void dc_sink_release(struct dc_sink *sink); 1362 1363 struct dc_sink_init_data { 1364 enum signal_type sink_signal; 1365 struct dc_link *link; 1366 uint32_t dongle_max_pix_clk; 1367 bool converter_disable_audio; 1368 }; 1369 1370 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1371 1372 /* Newer interfaces */ 1373 struct dc_cursor { 1374 struct dc_plane_address address; 1375 struct dc_cursor_attributes attributes; 1376 }; 1377 1378 1379 /******************************************************************************* 1380 * Interrupt interfaces 1381 ******************************************************************************/ 1382 enum dc_irq_source dc_interrupt_to_irq_source( 1383 struct dc *dc, 1384 uint32_t src_id, 1385 uint32_t ext_id); 1386 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1387 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1388 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1389 struct dc *dc, uint32_t link_index); 1390 1391 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1392 1393 /******************************************************************************* 1394 * Power Interfaces 1395 ******************************************************************************/ 1396 1397 void dc_set_power_state( 1398 struct dc *dc, 1399 enum dc_acpi_cm_power_state power_state); 1400 void dc_resume(struct dc *dc); 1401 1402 void dc_power_down_on_boot(struct dc *dc); 1403 1404 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1405 /* 1406 * HDCP Interfaces 1407 */ 1408 enum hdcp_message_status dc_process_hdcp_msg( 1409 enum signal_type signal, 1410 struct dc_link *link, 1411 struct hdcp_protection_message *message_info); 1412 #endif 1413 bool dc_is_dmcu_initialized(struct dc *dc); 1414 1415 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1416 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1417 #if defined(CONFIG_DRM_AMD_DC_DCN) 1418 1419 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1420 struct dc_cursor_attributes *cursor_attr); 1421 1422 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1423 1424 /* 1425 * blank all streams, and set min and max memory clock to 1426 * lowest and highest DPM level, respectively 1427 */ 1428 void dc_unlock_memory_clock_frequency(struct dc *dc); 1429 1430 /* 1431 * set min memory clock to the min required for current mode, 1432 * max to maxDPM, and unblank streams 1433 */ 1434 void dc_lock_memory_clock_frequency(struct dc *dc); 1435 1436 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1437 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1438 1439 /* cleanup on driver unload */ 1440 void dc_hardware_release(struct dc *dc); 1441 1442 #endif 1443 1444 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1445 #if defined(CONFIG_DRM_AMD_DC_DCN) 1446 void dc_z10_restore(const struct dc *dc); 1447 void dc_z10_save_init(struct dc *dc); 1448 #endif 1449 1450 bool dc_enable_dmub_notifications(struct dc *dc); 1451 1452 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1453 uint32_t link_index, 1454 struct aux_payload *payload); 1455 1456 /* Get dc link index from dpia port index */ 1457 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1458 uint8_t dpia_port_index); 1459 1460 bool dc_process_dmub_set_config_async(struct dc *dc, 1461 uint32_t link_index, 1462 struct set_config_cmd_payload *payload, 1463 struct dmub_notification *notify); 1464 1465 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1466 uint32_t link_index, 1467 uint8_t mst_alloc_slots, 1468 uint8_t *mst_slots_in_use); 1469 1470 /******************************************************************************* 1471 * DSC Interfaces 1472 ******************************************************************************/ 1473 #include "dc_dsc.h" 1474 1475 /******************************************************************************* 1476 * Disable acc mode Interfaces 1477 ******************************************************************************/ 1478 void dc_disable_accelerated_mode(struct dc *dc); 1479 1480 #endif /* DC_INTERFACE_H_ */ 1481