1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.58" 43 44 #define MAX_SURFACES 3 45 #define MAX_PLANES 6 46 #define MAX_STREAMS 6 47 #define MAX_SINKS_PER_LINK 4 48 49 /******************************************************************************* 50 * Display Core Interfaces 51 ******************************************************************************/ 52 struct dc_versions { 53 const char *dc_ver; 54 struct dmcu_version dmcu_version; 55 }; 56 57 enum dc_plane_type { 58 DC_PLANE_TYPE_INVALID, 59 DC_PLANE_TYPE_DCE_RGB, 60 DC_PLANE_TYPE_DCE_UNDERLAY, 61 DC_PLANE_TYPE_DCN_UNIVERSAL, 62 }; 63 64 struct dc_plane_cap { 65 enum dc_plane_type type; 66 uint32_t blends_with_above : 1; 67 uint32_t blends_with_below : 1; 68 uint32_t per_pixel_alpha : 1; 69 struct { 70 uint32_t argb8888 : 1; 71 uint32_t nv12 : 1; 72 uint32_t fp16 : 1; 73 uint32_t p010 : 1; 74 uint32_t ayuv : 1; 75 } pixel_format_support; 76 // max upscaling factor x1000 77 // upscaling factors are always >= 1 78 // for example, 1080p -> 8K is 4.0, or 4000 raw value 79 struct { 80 uint32_t argb8888; 81 uint32_t nv12; 82 uint32_t fp16; 83 } max_upscale_factor; 84 // max downscale factor x1000 85 // downscale factors are always <= 1 86 // for example, 8K -> 1080p is 0.25, or 250 raw value 87 struct { 88 uint32_t argb8888; 89 uint32_t nv12; 90 uint32_t fp16; 91 } max_downscale_factor; 92 }; 93 94 struct dc_caps { 95 uint32_t max_streams; 96 uint32_t max_links; 97 uint32_t max_audios; 98 uint32_t max_slave_planes; 99 uint32_t max_planes; 100 uint32_t max_downscale_ratio; 101 uint32_t i2c_speed_in_khz; 102 uint32_t dmdata_alloc_size; 103 unsigned int max_cursor_size; 104 unsigned int max_video_width; 105 int linear_pitch_alignment; 106 bool dcc_const_color; 107 bool dynamic_audio; 108 bool is_apu; 109 bool dual_link_dvi; 110 bool post_blend_color_processing; 111 bool force_dp_tps4_for_cp2520; 112 bool disable_dp_clk_share; 113 bool psp_setup_panel_mode; 114 bool extended_aux_timeout_support; 115 bool dmcub_support; 116 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 117 bool hw_3d_lut; 118 #endif 119 struct dc_plane_cap planes[MAX_PLANES]; 120 }; 121 122 struct dc_bug_wa { 123 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 124 bool no_connect_phy_config; 125 bool dedcn20_305_wa; 126 #endif 127 bool skip_clock_update; 128 }; 129 130 struct dc_dcc_surface_param { 131 struct dc_size surface_size; 132 enum surface_pixel_format format; 133 enum swizzle_mode_values swizzle_mode; 134 enum dc_scan_direction scan; 135 }; 136 137 struct dc_dcc_setting { 138 unsigned int max_compressed_blk_size; 139 unsigned int max_uncompressed_blk_size; 140 bool independent_64b_blks; 141 }; 142 143 struct dc_surface_dcc_cap { 144 union { 145 struct { 146 struct dc_dcc_setting rgb; 147 } grph; 148 149 struct { 150 struct dc_dcc_setting luma; 151 struct dc_dcc_setting chroma; 152 } video; 153 }; 154 155 bool capable; 156 bool const_color_support; 157 }; 158 159 struct dc_static_screen_events { 160 bool force_trigger; 161 bool cursor_update; 162 bool surface_update; 163 bool overlay_update; 164 }; 165 166 167 /* Surface update type is used by dc_update_surfaces_and_stream 168 * The update type is determined at the very beginning of the function based 169 * on parameters passed in and decides how much programming (or updating) is 170 * going to be done during the call. 171 * 172 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 173 * logical calculations or hardware register programming. This update MUST be 174 * ISR safe on windows. Currently fast update will only be used to flip surface 175 * address. 176 * 177 * UPDATE_TYPE_MED is used for slower updates which require significant hw 178 * re-programming however do not affect bandwidth consumption or clock 179 * requirements. At present, this is the level at which front end updates 180 * that do not require us to run bw_calcs happen. These are in/out transfer func 181 * updates, viewport offset changes, recout size changes and pixel depth changes. 182 * This update can be done at ISR, but we want to minimize how often this happens. 183 * 184 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 185 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 186 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 187 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 188 * a full update. This cannot be done at ISR level and should be a rare event. 189 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 190 * underscan we don't expect to see this call at all. 191 */ 192 193 enum surface_update_type { 194 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 195 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 196 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 197 }; 198 199 /* Forward declaration*/ 200 struct dc; 201 struct dc_plane_state; 202 struct dc_state; 203 204 205 struct dc_cap_funcs { 206 bool (*get_dcc_compression_cap)(const struct dc *dc, 207 const struct dc_dcc_surface_param *input, 208 struct dc_surface_dcc_cap *output); 209 }; 210 211 struct link_training_settings; 212 213 214 /* Structure to hold configuration flags set by dm at dc creation. */ 215 struct dc_config { 216 bool gpu_vm_support; 217 bool disable_disp_pll_sharing; 218 bool fbc_support; 219 bool optimize_edp_link_rate; 220 bool disable_fractional_pwm; 221 bool allow_seamless_boot_optimization; 222 bool power_down_display_on_boot; 223 bool edp_not_connected; 224 bool force_enum_edp; 225 bool forced_clocks; 226 bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well 227 bool multi_mon_pp_mclk_switch; 228 }; 229 230 enum visual_confirm { 231 VISUAL_CONFIRM_DISABLE = 0, 232 VISUAL_CONFIRM_SURFACE = 1, 233 VISUAL_CONFIRM_HDR = 2, 234 VISUAL_CONFIRM_MPCTREE = 4, 235 }; 236 237 enum dcc_option { 238 DCC_ENABLE = 0, 239 DCC_DISABLE = 1, 240 DCC_HALF_REQ_DISALBE = 2, 241 }; 242 243 enum pipe_split_policy { 244 MPC_SPLIT_DYNAMIC = 0, 245 MPC_SPLIT_AVOID = 1, 246 MPC_SPLIT_AVOID_MULT_DISP = 2, 247 }; 248 249 enum wm_report_mode { 250 WM_REPORT_DEFAULT = 0, 251 WM_REPORT_OVERRIDE = 1, 252 }; 253 enum dtm_pstate{ 254 dtm_level_p0 = 0,/*highest voltage*/ 255 dtm_level_p1, 256 dtm_level_p2, 257 dtm_level_p3, 258 dtm_level_p4,/*when active_display_count = 0*/ 259 }; 260 261 enum dcn_pwr_state { 262 DCN_PWR_STATE_UNKNOWN = -1, 263 DCN_PWR_STATE_MISSION_MODE = 0, 264 DCN_PWR_STATE_LOW_POWER = 3, 265 }; 266 267 /* 268 * For any clocks that may differ per pipe 269 * only the max is stored in this structure 270 */ 271 struct dc_clocks { 272 int dispclk_khz; 273 int dppclk_khz; 274 int dcfclk_khz; 275 int socclk_khz; 276 int dcfclk_deep_sleep_khz; 277 int fclk_khz; 278 int phyclk_khz; 279 int dramclk_khz; 280 bool p_state_change_support; 281 enum dcn_pwr_state pwr_state; 282 /* 283 * Elements below are not compared for the purposes of 284 * optimization required 285 */ 286 bool prev_p_state_change_support; 287 enum dtm_pstate dtm_level; 288 int max_supported_dppclk_khz; 289 int max_supported_dispclk_khz; 290 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 291 int bw_dispclk_khz; 292 }; 293 294 struct dc_bw_validation_profile { 295 bool enable; 296 297 unsigned long long total_ticks; 298 unsigned long long voltage_level_ticks; 299 unsigned long long watermark_ticks; 300 unsigned long long rq_dlg_ticks; 301 302 unsigned long long total_count; 303 unsigned long long skip_fast_count; 304 unsigned long long skip_pass_count; 305 unsigned long long skip_fail_count; 306 }; 307 308 #define BW_VAL_TRACE_SETUP() \ 309 unsigned long long end_tick = 0; \ 310 unsigned long long voltage_level_tick = 0; \ 311 unsigned long long watermark_tick = 0; \ 312 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 313 dm_get_timestamp(dc->ctx) : 0 314 315 #define BW_VAL_TRACE_COUNT() \ 316 if (dc->debug.bw_val_profile.enable) \ 317 dc->debug.bw_val_profile.total_count++ 318 319 #define BW_VAL_TRACE_SKIP(status) \ 320 if (dc->debug.bw_val_profile.enable) { \ 321 if (!voltage_level_tick) \ 322 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 323 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 324 } 325 326 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 327 if (dc->debug.bw_val_profile.enable) \ 328 voltage_level_tick = dm_get_timestamp(dc->ctx) 329 330 #define BW_VAL_TRACE_END_WATERMARKS() \ 331 if (dc->debug.bw_val_profile.enable) \ 332 watermark_tick = dm_get_timestamp(dc->ctx) 333 334 #define BW_VAL_TRACE_FINISH() \ 335 if (dc->debug.bw_val_profile.enable) { \ 336 end_tick = dm_get_timestamp(dc->ctx); \ 337 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 338 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 339 if (watermark_tick) { \ 340 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 341 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 342 } \ 343 } 344 345 struct dc_debug_options { 346 enum visual_confirm visual_confirm; 347 bool sanity_checks; 348 bool max_disp_clk; 349 bool surface_trace; 350 bool timing_trace; 351 bool clock_trace; 352 bool validation_trace; 353 bool bandwidth_calcs_trace; 354 int max_downscale_src_width; 355 356 /* stutter efficiency related */ 357 bool disable_stutter; 358 bool use_max_lb; 359 enum dcc_option disable_dcc; 360 enum pipe_split_policy pipe_split_policy; 361 bool force_single_disp_pipe_split; 362 bool voltage_align_fclk; 363 364 bool disable_dfs_bypass; 365 bool disable_dpp_power_gate; 366 bool disable_hubp_power_gate; 367 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 368 bool disable_dsc_power_gate; 369 int dsc_min_slice_height_override; 370 #endif 371 bool disable_pplib_wm_range; 372 enum wm_report_mode pplib_wm_report_mode; 373 unsigned int min_disp_clk_khz; 374 unsigned int min_dpp_clk_khz; 375 int sr_exit_time_dpm0_ns; 376 int sr_enter_plus_exit_time_dpm0_ns; 377 int sr_exit_time_ns; 378 int sr_enter_plus_exit_time_ns; 379 int urgent_latency_ns; 380 uint32_t underflow_assert_delay_us; 381 int percent_of_ideal_drambw; 382 int dram_clock_change_latency_ns; 383 bool optimized_watermark; 384 int always_scale; 385 bool disable_pplib_clock_request; 386 bool disable_clock_gate; 387 bool disable_dmcu; 388 bool disable_psr; 389 bool force_abm_enable; 390 bool disable_stereo_support; 391 bool vsr_support; 392 bool performance_trace; 393 bool az_endpoint_mute_only; 394 bool always_use_regamma; 395 bool p010_mpo_support; 396 bool recovery_enabled; 397 bool avoid_vbios_exec_table; 398 bool scl_reset_length10; 399 bool hdmi20_disable; 400 bool skip_detection_link_training; 401 bool remove_disconnect_edp; 402 unsigned int force_odm_combine; //bit vector based on otg inst 403 unsigned int force_fclk_khz; 404 bool disable_tri_buf; 405 bool dmub_offload_enabled; 406 bool dmcub_emulation; 407 bool dmub_command_table; /* for testing only */ 408 struct dc_bw_validation_profile bw_val_profile; 409 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 410 bool disable_fec; 411 #endif 412 #ifdef CONFIG_DRM_AMD_DC_DCN2_1 413 bool disable_48mhz_pwrdwn; 414 #endif 415 /* This forces a hard min on the DCFCLK requested to SMU/PP 416 * watermarks are not affected. 417 */ 418 unsigned int force_min_dcfclk_mhz; 419 bool disable_timing_sync; 420 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 421 bool cm_in_bypass; 422 #endif 423 int force_clock_mode;/*every mode change.*/ 424 425 bool nv12_iflip_vm_wa; 426 bool disable_dram_clock_change_vactive_support; 427 }; 428 429 struct dc_debug_data { 430 uint32_t ltFailCount; 431 uint32_t i2cErrorCount; 432 uint32_t auxErrorCount; 433 }; 434 435 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 436 struct dc_phy_addr_space_config { 437 struct { 438 uint64_t start_addr; 439 uint64_t end_addr; 440 uint64_t fb_top; 441 uint64_t fb_offset; 442 uint64_t fb_base; 443 uint64_t agp_top; 444 uint64_t agp_bot; 445 uint64_t agp_base; 446 } system_aperture; 447 448 struct { 449 uint64_t page_table_start_addr; 450 uint64_t page_table_end_addr; 451 uint64_t page_table_base_addr; 452 } gart_config; 453 454 bool valid; 455 uint64_t page_table_default_page_addr; 456 }; 457 458 struct dc_virtual_addr_space_config { 459 uint64_t page_table_base_addr; 460 uint64_t page_table_start_addr; 461 uint64_t page_table_end_addr; 462 uint32_t page_table_block_size_in_bytes; 463 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 464 }; 465 #endif 466 467 struct dc_bounding_box_overrides { 468 int sr_exit_time_ns; 469 int sr_enter_plus_exit_time_ns; 470 int urgent_latency_ns; 471 int percent_of_ideal_drambw; 472 int dram_clock_change_latency_ns; 473 /* This forces a hard min on the DCFCLK we use 474 * for DML. Unlike the debug option for forcing 475 * DCFCLK, this override affects watermark calculations 476 */ 477 int min_dcfclk_mhz; 478 }; 479 480 struct dc_state; 481 struct resource_pool; 482 struct dce_hwseq; 483 struct gpu_info_soc_bounding_box_v1_0; 484 struct dc { 485 struct dc_versions versions; 486 struct dc_caps caps; 487 struct dc_cap_funcs cap_funcs; 488 struct dc_config config; 489 struct dc_debug_options debug; 490 struct dc_bounding_box_overrides bb_overrides; 491 struct dc_bug_wa work_arounds; 492 struct dc_context *ctx; 493 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 494 struct dc_phy_addr_space_config vm_pa_config; 495 #endif 496 497 uint8_t link_count; 498 struct dc_link *links[MAX_PIPES * 2]; 499 500 struct dc_state *current_state; 501 struct resource_pool *res_pool; 502 503 struct clk_mgr *clk_mgr; 504 505 /* Display Engine Clock levels */ 506 struct dm_pp_clock_levels sclk_lvls; 507 508 /* Inputs into BW and WM calculations. */ 509 struct bw_calcs_dceip *bw_dceip; 510 struct bw_calcs_vbios *bw_vbios; 511 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 512 struct dcn_soc_bounding_box *dcn_soc; 513 struct dcn_ip_params *dcn_ip; 514 struct display_mode_lib dml; 515 #endif 516 517 /* HW functions */ 518 struct hw_sequencer_funcs hwss; 519 struct dce_hwseq *hwseq; 520 521 /* Require to optimize clocks and bandwidth for added/removed planes */ 522 bool optimized_required; 523 524 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 525 bool optimize_seamless_boot; 526 527 /* FBC compressor */ 528 struct compressor *fbc_compressor; 529 530 struct dc_debug_data debug_data; 531 532 const char *build_id; 533 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 534 struct vm_helper *vm_helper; 535 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 536 #endif 537 }; 538 539 enum frame_buffer_mode { 540 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 541 FRAME_BUFFER_MODE_ZFB_ONLY, 542 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 543 } ; 544 545 struct dchub_init_data { 546 int64_t zfb_phys_addr_base; 547 int64_t zfb_mc_base_addr; 548 uint64_t zfb_size_in_byte; 549 enum frame_buffer_mode fb_mode; 550 bool dchub_initialzied; 551 bool dchub_info_valid; 552 }; 553 554 struct dc_init_data { 555 struct hw_asic_id asic_id; 556 void *driver; /* ctx */ 557 struct cgs_device *cgs_device; 558 struct dc_bounding_box_overrides bb_overrides; 559 560 int num_virtual_links; 561 /* 562 * If 'vbios_override' not NULL, it will be called instead 563 * of the real VBIOS. Intended use is Diagnostics on FPGA. 564 */ 565 struct dc_bios *vbios_override; 566 enum dce_environment dce_environment; 567 568 struct dmub_offload_funcs *dmub_if; 569 struct dc_reg_helper_state *dmub_offload; 570 571 struct dc_config flags; 572 uint32_t log_mask; 573 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 574 /** 575 * gpu_info FW provided soc bounding box struct or 0 if not 576 * available in FW 577 */ 578 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 579 #endif 580 }; 581 582 struct dc_callback_init { 583 #ifdef CONFIG_DRM_AMD_DC_HDCP 584 struct cp_psp cp_psp; 585 #else 586 uint8_t reserved; 587 #endif 588 }; 589 590 struct dc *dc_create(const struct dc_init_data *init_params); 591 void dc_hardware_init(struct dc *dc); 592 593 int dc_get_vmid_use_vector(struct dc *dc); 594 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 595 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 596 /* Returns the number of vmids supported */ 597 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 598 #endif 599 void dc_init_callbacks(struct dc *dc, 600 const struct dc_callback_init *init_params); 601 void dc_deinit_callbacks(struct dc *dc); 602 void dc_destroy(struct dc **dc); 603 604 /******************************************************************************* 605 * Surface Interfaces 606 ******************************************************************************/ 607 608 enum { 609 TRANSFER_FUNC_POINTS = 1025 610 }; 611 612 struct dc_hdr_static_metadata { 613 /* display chromaticities and white point in units of 0.00001 */ 614 unsigned int chromaticity_green_x; 615 unsigned int chromaticity_green_y; 616 unsigned int chromaticity_blue_x; 617 unsigned int chromaticity_blue_y; 618 unsigned int chromaticity_red_x; 619 unsigned int chromaticity_red_y; 620 unsigned int chromaticity_white_point_x; 621 unsigned int chromaticity_white_point_y; 622 623 uint32_t min_luminance; 624 uint32_t max_luminance; 625 uint32_t maximum_content_light_level; 626 uint32_t maximum_frame_average_light_level; 627 }; 628 629 enum dc_transfer_func_type { 630 TF_TYPE_PREDEFINED, 631 TF_TYPE_DISTRIBUTED_POINTS, 632 TF_TYPE_BYPASS, 633 TF_TYPE_HWPWL 634 }; 635 636 struct dc_transfer_func_distributed_points { 637 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 638 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 639 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 640 641 uint16_t end_exponent; 642 uint16_t x_point_at_y1_red; 643 uint16_t x_point_at_y1_green; 644 uint16_t x_point_at_y1_blue; 645 }; 646 647 enum dc_transfer_func_predefined { 648 TRANSFER_FUNCTION_SRGB, 649 TRANSFER_FUNCTION_BT709, 650 TRANSFER_FUNCTION_PQ, 651 TRANSFER_FUNCTION_LINEAR, 652 TRANSFER_FUNCTION_UNITY, 653 TRANSFER_FUNCTION_HLG, 654 TRANSFER_FUNCTION_HLG12, 655 TRANSFER_FUNCTION_GAMMA22, 656 TRANSFER_FUNCTION_GAMMA24, 657 TRANSFER_FUNCTION_GAMMA26 658 }; 659 660 661 struct dc_transfer_func { 662 struct kref refcount; 663 enum dc_transfer_func_type type; 664 enum dc_transfer_func_predefined tf; 665 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 666 uint32_t sdr_ref_white_level; 667 struct dc_context *ctx; 668 union { 669 struct pwl_params pwl; 670 struct dc_transfer_func_distributed_points tf_pts; 671 }; 672 }; 673 674 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 675 676 union dc_3dlut_state { 677 struct { 678 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 679 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 680 uint32_t rmu_mux_num:3; /*index of mux to use*/ 681 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 682 uint32_t mpc_rmu1_mux:4; 683 uint32_t mpc_rmu2_mux:4; 684 uint32_t reserved:15; 685 } bits; 686 uint32_t raw; 687 }; 688 689 690 struct dc_3dlut { 691 struct kref refcount; 692 struct tetrahedral_params lut_3d; 693 uint32_t hdr_multiplier; 694 bool initialized; /*remove after diag fix*/ 695 union dc_3dlut_state state; 696 struct dc_context *ctx; 697 }; 698 #endif 699 /* 700 * This structure is filled in by dc_surface_get_status and contains 701 * the last requested address and the currently active address so the called 702 * can determine if there are any outstanding flips 703 */ 704 struct dc_plane_status { 705 struct dc_plane_address requested_address; 706 struct dc_plane_address current_address; 707 bool is_flip_pending; 708 bool is_right_eye; 709 }; 710 711 union surface_update_flags { 712 713 struct { 714 uint32_t addr_update:1; 715 /* Medium updates */ 716 uint32_t dcc_change:1; 717 uint32_t color_space_change:1; 718 uint32_t horizontal_mirror_change:1; 719 uint32_t per_pixel_alpha_change:1; 720 uint32_t global_alpha_change:1; 721 uint32_t sdr_white_level:1; 722 uint32_t rotation_change:1; 723 uint32_t swizzle_change:1; 724 uint32_t scaling_change:1; 725 uint32_t position_change:1; 726 uint32_t in_transfer_func_change:1; 727 uint32_t input_csc_change:1; 728 uint32_t coeff_reduction_change:1; 729 uint32_t output_tf_change:1; 730 uint32_t pixel_format_change:1; 731 uint32_t plane_size_change:1; 732 733 /* Full updates */ 734 uint32_t new_plane:1; 735 uint32_t bpp_change:1; 736 uint32_t gamma_change:1; 737 uint32_t bandwidth_change:1; 738 uint32_t clock_change:1; 739 uint32_t stereo_format_change:1; 740 uint32_t full_update:1; 741 } bits; 742 743 uint32_t raw; 744 }; 745 746 struct dc_plane_state { 747 struct dc_plane_address address; 748 struct dc_plane_flip_time time; 749 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 750 bool triplebuffer_flips; 751 #endif 752 struct scaling_taps scaling_quality; 753 struct rect src_rect; 754 struct rect dst_rect; 755 struct rect clip_rect; 756 757 struct plane_size plane_size; 758 union dc_tiling_info tiling_info; 759 760 struct dc_plane_dcc_param dcc; 761 762 struct dc_gamma *gamma_correction; 763 struct dc_transfer_func *in_transfer_func; 764 struct dc_bias_and_scale *bias_and_scale; 765 struct dc_csc_transform input_csc_color_matrix; 766 struct fixed31_32 coeff_reduction_factor; 767 uint32_t sdr_white_level; 768 769 // TODO: No longer used, remove 770 struct dc_hdr_static_metadata hdr_static_ctx; 771 772 enum dc_color_space color_space; 773 774 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 775 struct dc_3dlut *lut3d_func; 776 struct dc_transfer_func *in_shaper_func; 777 struct dc_transfer_func *blend_tf; 778 #endif 779 780 enum surface_pixel_format format; 781 enum dc_rotation_angle rotation; 782 enum plane_stereo_format stereo_format; 783 784 bool is_tiling_rotated; 785 bool per_pixel_alpha; 786 bool global_alpha; 787 int global_alpha_value; 788 bool visible; 789 bool flip_immediate; 790 bool horizontal_mirror; 791 int layer_index; 792 793 union surface_update_flags update_flags; 794 /* private to DC core */ 795 struct dc_plane_status status; 796 struct dc_context *ctx; 797 798 /* HACK: Workaround for forcing full reprogramming under some conditions */ 799 bool force_full_update; 800 801 /* private to dc_surface.c */ 802 enum dc_irq_source irq_source; 803 struct kref refcount; 804 }; 805 806 struct dc_plane_info { 807 struct plane_size plane_size; 808 union dc_tiling_info tiling_info; 809 struct dc_plane_dcc_param dcc; 810 enum surface_pixel_format format; 811 enum dc_rotation_angle rotation; 812 enum plane_stereo_format stereo_format; 813 enum dc_color_space color_space; 814 unsigned int sdr_white_level; 815 bool horizontal_mirror; 816 bool visible; 817 bool per_pixel_alpha; 818 bool global_alpha; 819 int global_alpha_value; 820 bool input_csc_enabled; 821 int layer_index; 822 }; 823 824 struct dc_scaling_info { 825 struct rect src_rect; 826 struct rect dst_rect; 827 struct rect clip_rect; 828 struct scaling_taps scaling_quality; 829 }; 830 831 struct dc_surface_update { 832 struct dc_plane_state *surface; 833 834 /* isr safe update parameters. null means no updates */ 835 const struct dc_flip_addrs *flip_addr; 836 const struct dc_plane_info *plane_info; 837 const struct dc_scaling_info *scaling_info; 838 839 /* following updates require alloc/sleep/spin that is not isr safe, 840 * null means no updates 841 */ 842 const struct dc_gamma *gamma; 843 const struct dc_transfer_func *in_transfer_func; 844 845 const struct dc_csc_transform *input_csc_color_matrix; 846 const struct fixed31_32 *coeff_reduction_factor; 847 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 848 const struct dc_transfer_func *func_shaper; 849 const struct dc_3dlut *lut3d_func; 850 const struct dc_transfer_func *blend_tf; 851 #endif 852 }; 853 854 /* 855 * Create a new surface with default parameters; 856 */ 857 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 858 const struct dc_plane_status *dc_plane_get_status( 859 const struct dc_plane_state *plane_state); 860 861 void dc_plane_state_retain(struct dc_plane_state *plane_state); 862 void dc_plane_state_release(struct dc_plane_state *plane_state); 863 864 void dc_gamma_retain(struct dc_gamma *dc_gamma); 865 void dc_gamma_release(struct dc_gamma **dc_gamma); 866 struct dc_gamma *dc_create_gamma(void); 867 868 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 869 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 870 struct dc_transfer_func *dc_create_transfer_func(void); 871 872 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 873 struct dc_3dlut *dc_create_3dlut_func(void); 874 void dc_3dlut_func_release(struct dc_3dlut *lut); 875 void dc_3dlut_func_retain(struct dc_3dlut *lut); 876 #endif 877 /* 878 * This structure holds a surface address. There could be multiple addresses 879 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 880 * as frame durations and DCC format can also be set. 881 */ 882 struct dc_flip_addrs { 883 struct dc_plane_address address; 884 unsigned int flip_timestamp_in_us; 885 bool flip_immediate; 886 /* TODO: add flip duration for FreeSync */ 887 }; 888 889 bool dc_post_update_surfaces_to_stream( 890 struct dc *dc); 891 892 #include "dc_stream.h" 893 894 /* 895 * Structure to store surface/stream associations for validation 896 */ 897 struct dc_validation_set { 898 struct dc_stream_state *stream; 899 struct dc_plane_state *plane_states[MAX_SURFACES]; 900 uint8_t plane_count; 901 }; 902 903 bool dc_validate_seamless_boot_timing(const struct dc *dc, 904 const struct dc_sink *sink, 905 struct dc_crtc_timing *crtc_timing); 906 907 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 908 909 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 910 911 bool dc_set_generic_gpio_for_stereo(bool enable, 912 struct gpio_service *gpio_service); 913 914 /* 915 * fast_validate: we return after determining if we can support the new state, 916 * but before we populate the programming info 917 */ 918 enum dc_status dc_validate_global_state( 919 struct dc *dc, 920 struct dc_state *new_ctx, 921 bool fast_validate); 922 923 924 void dc_resource_state_construct( 925 const struct dc *dc, 926 struct dc_state *dst_ctx); 927 928 void dc_resource_state_copy_construct( 929 const struct dc_state *src_ctx, 930 struct dc_state *dst_ctx); 931 932 void dc_resource_state_copy_construct_current( 933 const struct dc *dc, 934 struct dc_state *dst_ctx); 935 936 void dc_resource_state_destruct(struct dc_state *context); 937 938 /* 939 * TODO update to make it about validation sets 940 * Set up streams and links associated to drive sinks 941 * The streams parameter is an absolute set of all active streams. 942 * 943 * After this call: 944 * Phy, Encoder, Timing Generator are programmed and enabled. 945 * New streams are enabled with blank stream; no memory read. 946 */ 947 bool dc_commit_state(struct dc *dc, struct dc_state *context); 948 949 950 struct dc_state *dc_create_state(struct dc *dc); 951 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 952 void dc_retain_state(struct dc_state *context); 953 void dc_release_state(struct dc_state *context); 954 955 /******************************************************************************* 956 * Link Interfaces 957 ******************************************************************************/ 958 959 struct dpcd_caps { 960 union dpcd_rev dpcd_rev; 961 union max_lane_count max_ln_count; 962 union max_down_spread max_down_spread; 963 union dprx_feature dprx_feature; 964 965 /* valid only for eDP v1.4 or higher*/ 966 uint8_t edp_supported_link_rates_count; 967 enum dc_link_rate edp_supported_link_rates[8]; 968 969 /* dongle type (DP converter, CV smart dongle) */ 970 enum display_dongle_type dongle_type; 971 /* branch device or sink device */ 972 bool is_branch_dev; 973 /* Dongle's downstream count. */ 974 union sink_count sink_count; 975 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 976 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 977 struct dc_dongle_caps dongle_caps; 978 979 uint32_t sink_dev_id; 980 int8_t sink_dev_id_str[6]; 981 int8_t sink_hw_revision; 982 int8_t sink_fw_revision[2]; 983 984 uint32_t branch_dev_id; 985 int8_t branch_dev_name[6]; 986 int8_t branch_hw_revision; 987 int8_t branch_fw_revision[2]; 988 989 bool allow_invalid_MSA_timing_param; 990 bool panel_mode_edp; 991 bool dpcd_display_control_capable; 992 bool ext_receiver_cap_field_present; 993 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 994 union dpcd_fec_capability fec_cap; 995 struct dpcd_dsc_capabilities dsc_caps; 996 #endif 997 }; 998 999 #include "dc_link.h" 1000 1001 /******************************************************************************* 1002 * Sink Interfaces - A sink corresponds to a display output device 1003 ******************************************************************************/ 1004 1005 struct dc_container_id { 1006 // 128bit GUID in binary form 1007 unsigned char guid[16]; 1008 // 8 byte port ID -> ELD.PortID 1009 unsigned int portId[2]; 1010 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1011 unsigned short manufacturerName; 1012 // 2 byte product code -> ELD.ProductCode 1013 unsigned short productCode; 1014 }; 1015 1016 1017 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1018 struct dc_sink_dsc_caps { 1019 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1020 // 'false' if they are sink's DSC caps 1021 bool is_virtual_dpcd_dsc; 1022 struct dsc_dec_dpcd_caps dsc_dec_caps; 1023 }; 1024 #endif 1025 1026 /* 1027 * The sink structure contains EDID and other display device properties 1028 */ 1029 struct dc_sink { 1030 enum signal_type sink_signal; 1031 struct dc_edid dc_edid; /* raw edid */ 1032 struct dc_edid_caps edid_caps; /* parse display caps */ 1033 struct dc_container_id *dc_container_id; 1034 uint32_t dongle_max_pix_clk; 1035 void *priv; 1036 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1037 bool converter_disable_audio; 1038 1039 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1040 struct dc_sink_dsc_caps sink_dsc_caps; 1041 #endif 1042 1043 /* private to DC core */ 1044 struct dc_link *link; 1045 struct dc_context *ctx; 1046 1047 uint32_t sink_id; 1048 1049 /* private to dc_sink.c */ 1050 // refcount must be the last member in dc_sink, since we want the 1051 // sink structure to be logically cloneable up to (but not including) 1052 // refcount 1053 struct kref refcount; 1054 }; 1055 1056 void dc_sink_retain(struct dc_sink *sink); 1057 void dc_sink_release(struct dc_sink *sink); 1058 1059 struct dc_sink_init_data { 1060 enum signal_type sink_signal; 1061 struct dc_link *link; 1062 uint32_t dongle_max_pix_clk; 1063 bool converter_disable_audio; 1064 }; 1065 1066 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1067 1068 /* Newer interfaces */ 1069 struct dc_cursor { 1070 struct dc_plane_address address; 1071 struct dc_cursor_attributes attributes; 1072 }; 1073 1074 1075 /******************************************************************************* 1076 * Interrupt interfaces 1077 ******************************************************************************/ 1078 enum dc_irq_source dc_interrupt_to_irq_source( 1079 struct dc *dc, 1080 uint32_t src_id, 1081 uint32_t ext_id); 1082 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1083 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1084 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1085 struct dc *dc, uint32_t link_index); 1086 1087 /******************************************************************************* 1088 * Power Interfaces 1089 ******************************************************************************/ 1090 1091 void dc_set_power_state( 1092 struct dc *dc, 1093 enum dc_acpi_cm_power_state power_state); 1094 void dc_resume(struct dc *dc); 1095 unsigned int dc_get_current_backlight_pwm(struct dc *dc); 1096 unsigned int dc_get_target_backlight_pwm(struct dc *dc); 1097 1098 bool dc_is_dmcu_initialized(struct dc *dc); 1099 1100 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1101 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1102 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) 1103 /******************************************************************************* 1104 * DSC Interfaces 1105 ******************************************************************************/ 1106 #include "dc_dsc.h" 1107 #endif 1108 #endif /* DC_INTERFACE_H_ */ 1109