1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.187" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 // Sizes defined as multiples of 64KB 79 enum det_size { 80 DET_SIZE_DEFAULT = 0, 81 DET_SIZE_192KB = 3, 82 DET_SIZE_256KB = 4, 83 DET_SIZE_320KB = 5, 84 DET_SIZE_384KB = 6 85 }; 86 87 88 struct dc_plane_cap { 89 enum dc_plane_type type; 90 uint32_t blends_with_above : 1; 91 uint32_t blends_with_below : 1; 92 uint32_t per_pixel_alpha : 1; 93 struct { 94 uint32_t argb8888 : 1; 95 uint32_t nv12 : 1; 96 uint32_t fp16 : 1; 97 uint32_t p010 : 1; 98 uint32_t ayuv : 1; 99 } pixel_format_support; 100 // max upscaling factor x1000 101 // upscaling factors are always >= 1 102 // for example, 1080p -> 8K is 4.0, or 4000 raw value 103 struct { 104 uint32_t argb8888; 105 uint32_t nv12; 106 uint32_t fp16; 107 } max_upscale_factor; 108 // max downscale factor x1000 109 // downscale factors are always <= 1 110 // for example, 8K -> 1080p is 0.25, or 250 raw value 111 struct { 112 uint32_t argb8888; 113 uint32_t nv12; 114 uint32_t fp16; 115 } max_downscale_factor; 116 // minimal width/height 117 uint32_t min_width; 118 uint32_t min_height; 119 }; 120 121 // Color management caps (DPP and MPC) 122 struct rom_curve_caps { 123 uint16_t srgb : 1; 124 uint16_t bt2020 : 1; 125 uint16_t gamma2_2 : 1; 126 uint16_t pq : 1; 127 uint16_t hlg : 1; 128 }; 129 130 struct dpp_color_caps { 131 uint16_t dcn_arch : 1; // all DCE generations treated the same 132 // input lut is different than most LUTs, just plain 256-entry lookup 133 uint16_t input_lut_shared : 1; // shared with DGAM 134 uint16_t icsc : 1; 135 uint16_t dgam_ram : 1; 136 uint16_t post_csc : 1; // before gamut remap 137 uint16_t gamma_corr : 1; 138 139 // hdr_mult and gamut remap always available in DPP (in that order) 140 // 3d lut implies shaper LUT, 141 // it may be shared with MPC - check MPC:shared_3d_lut flag 142 uint16_t hw_3d_lut : 1; 143 uint16_t ogam_ram : 1; // blnd gam 144 uint16_t ocsc : 1; 145 uint16_t dgam_rom_for_yuv : 1; 146 struct rom_curve_caps dgam_rom_caps; 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct mpc_color_caps { 151 uint16_t gamut_remap : 1; 152 uint16_t ogam_ram : 1; 153 uint16_t ocsc : 1; 154 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 155 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 156 157 struct rom_curve_caps ogam_rom_caps; 158 }; 159 160 struct dc_color_caps { 161 struct dpp_color_caps dpp; 162 struct mpc_color_caps mpc; 163 }; 164 165 struct dc_dmub_caps { 166 bool psr; 167 }; 168 169 struct dc_caps { 170 uint32_t max_streams; 171 uint32_t max_links; 172 uint32_t max_audios; 173 uint32_t max_slave_planes; 174 uint32_t max_slave_yuv_planes; 175 uint32_t max_slave_rgb_planes; 176 uint32_t max_planes; 177 uint32_t max_downscale_ratio; 178 uint32_t i2c_speed_in_khz; 179 uint32_t i2c_speed_in_khz_hdcp; 180 uint32_t dmdata_alloc_size; 181 unsigned int max_cursor_size; 182 unsigned int max_video_width; 183 unsigned int min_horizontal_blanking_period; 184 int linear_pitch_alignment; 185 bool dcc_const_color; 186 bool dynamic_audio; 187 bool is_apu; 188 bool dual_link_dvi; 189 bool post_blend_color_processing; 190 bool force_dp_tps4_for_cp2520; 191 bool disable_dp_clk_share; 192 bool psp_setup_panel_mode; 193 bool extended_aux_timeout_support; 194 bool dmcub_support; 195 bool zstate_support; 196 uint32_t num_of_internal_disp; 197 enum dp_protocol_version max_dp_protocol_version; 198 unsigned int mall_size_per_mem_channel; 199 unsigned int mall_size_total; 200 unsigned int cursor_cache_size; 201 struct dc_plane_cap planes[MAX_PLANES]; 202 struct dc_color_caps color; 203 struct dc_dmub_caps dmub_caps; 204 bool dp_hpo; 205 bool hdmi_frl_pcon_support; 206 bool edp_dsc_support; 207 bool vbios_lttpr_aware; 208 bool vbios_lttpr_enable; 209 uint32_t max_otg_num; 210 #ifdef CONFIG_DRM_AMD_DC_DCN 211 uint32_t max_cab_allocation_bytes; 212 uint32_t cache_line_size; 213 uint32_t cache_num_ways; 214 uint16_t subvp_fw_processing_delay_us; 215 uint16_t subvp_prefetch_end_to_mall_start_us; 216 uint16_t subvp_pstate_allow_width_us; 217 uint16_t subvp_vertical_int_margin_us; 218 #endif 219 }; 220 221 struct dc_bug_wa { 222 bool no_connect_phy_config; 223 bool dedcn20_305_wa; 224 bool skip_clock_update; 225 bool lt_early_cr_pattern; 226 }; 227 228 struct dc_dcc_surface_param { 229 struct dc_size surface_size; 230 enum surface_pixel_format format; 231 enum swizzle_mode_values swizzle_mode; 232 enum dc_scan_direction scan; 233 }; 234 235 struct dc_dcc_setting { 236 unsigned int max_compressed_blk_size; 237 unsigned int max_uncompressed_blk_size; 238 bool independent_64b_blks; 239 //These bitfields to be used starting with DCN 240 struct { 241 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 242 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 243 uint32_t dcc_256_128_128 : 1; //available starting with DCN 244 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 245 } dcc_controls; 246 }; 247 248 struct dc_surface_dcc_cap { 249 union { 250 struct { 251 struct dc_dcc_setting rgb; 252 } grph; 253 254 struct { 255 struct dc_dcc_setting luma; 256 struct dc_dcc_setting chroma; 257 } video; 258 }; 259 260 bool capable; 261 bool const_color_support; 262 }; 263 264 struct dc_static_screen_params { 265 struct { 266 bool force_trigger; 267 bool cursor_update; 268 bool surface_update; 269 bool overlay_update; 270 } triggers; 271 unsigned int num_frames; 272 }; 273 274 275 /* Surface update type is used by dc_update_surfaces_and_stream 276 * The update type is determined at the very beginning of the function based 277 * on parameters passed in and decides how much programming (or updating) is 278 * going to be done during the call. 279 * 280 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 281 * logical calculations or hardware register programming. This update MUST be 282 * ISR safe on windows. Currently fast update will only be used to flip surface 283 * address. 284 * 285 * UPDATE_TYPE_MED is used for slower updates which require significant hw 286 * re-programming however do not affect bandwidth consumption or clock 287 * requirements. At present, this is the level at which front end updates 288 * that do not require us to run bw_calcs happen. These are in/out transfer func 289 * updates, viewport offset changes, recout size changes and pixel depth changes. 290 * This update can be done at ISR, but we want to minimize how often this happens. 291 * 292 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 293 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 294 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 295 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 296 * a full update. This cannot be done at ISR level and should be a rare event. 297 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 298 * underscan we don't expect to see this call at all. 299 */ 300 301 enum surface_update_type { 302 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 303 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 304 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 305 }; 306 307 /* Forward declaration*/ 308 struct dc; 309 struct dc_plane_state; 310 struct dc_state; 311 312 313 struct dc_cap_funcs { 314 bool (*get_dcc_compression_cap)(const struct dc *dc, 315 const struct dc_dcc_surface_param *input, 316 struct dc_surface_dcc_cap *output); 317 }; 318 319 struct link_training_settings; 320 321 union allow_lttpr_non_transparent_mode { 322 struct { 323 bool DP1_4A : 1; 324 bool DP2_0 : 1; 325 } bits; 326 unsigned char raw; 327 }; 328 329 /* Structure to hold configuration flags set by dm at dc creation. */ 330 struct dc_config { 331 bool gpu_vm_support; 332 bool disable_disp_pll_sharing; 333 bool fbc_support; 334 bool disable_fractional_pwm; 335 bool allow_seamless_boot_optimization; 336 bool seamless_boot_edp_requested; 337 bool edp_not_connected; 338 bool edp_no_power_sequencing; 339 bool force_enum_edp; 340 bool forced_clocks; 341 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 342 bool multi_mon_pp_mclk_switch; 343 bool disable_dmcu; 344 bool enable_4to1MPC; 345 bool enable_windowed_mpo_odm; 346 uint32_t allow_edp_hotplug_detection; 347 bool clamp_min_dcfclk; 348 uint64_t vblank_alignment_dto_params; 349 uint8_t vblank_alignment_max_frame_time_diff; 350 bool is_asymmetric_memory; 351 bool is_single_rank_dimm; 352 bool use_pipe_ctx_sync_logic; 353 bool ignore_dpref_ss; 354 bool enable_mipi_converter_optimization; 355 }; 356 357 enum visual_confirm { 358 VISUAL_CONFIRM_DISABLE = 0, 359 VISUAL_CONFIRM_SURFACE = 1, 360 VISUAL_CONFIRM_HDR = 2, 361 VISUAL_CONFIRM_MPCTREE = 4, 362 VISUAL_CONFIRM_PSR = 5, 363 VISUAL_CONFIRM_SWIZZLE = 9, 364 }; 365 366 enum dc_psr_power_opts { 367 psr_power_opt_invalid = 0x0, 368 psr_power_opt_smu_opt_static_screen = 0x1, 369 psr_power_opt_z10_static_screen = 0x10, 370 psr_power_opt_ds_disable_allow = 0x100, 371 }; 372 373 enum dml_hostvm_override_opts { 374 DML_HOSTVM_NO_OVERRIDE = 0x0, 375 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 376 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 377 }; 378 379 enum dcc_option { 380 DCC_ENABLE = 0, 381 DCC_DISABLE = 1, 382 DCC_HALF_REQ_DISALBE = 2, 383 }; 384 385 enum pipe_split_policy { 386 MPC_SPLIT_DYNAMIC = 0, 387 MPC_SPLIT_AVOID = 1, 388 MPC_SPLIT_AVOID_MULT_DISP = 2, 389 }; 390 391 enum wm_report_mode { 392 WM_REPORT_DEFAULT = 0, 393 WM_REPORT_OVERRIDE = 1, 394 }; 395 enum dtm_pstate{ 396 dtm_level_p0 = 0,/*highest voltage*/ 397 dtm_level_p1, 398 dtm_level_p2, 399 dtm_level_p3, 400 dtm_level_p4,/*when active_display_count = 0*/ 401 }; 402 403 enum dcn_pwr_state { 404 DCN_PWR_STATE_UNKNOWN = -1, 405 DCN_PWR_STATE_MISSION_MODE = 0, 406 DCN_PWR_STATE_LOW_POWER = 3, 407 }; 408 409 enum dcn_zstate_support_state { 410 DCN_ZSTATE_SUPPORT_UNKNOWN, 411 DCN_ZSTATE_SUPPORT_ALLOW, 412 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 413 DCN_ZSTATE_SUPPORT_DISALLOW, 414 }; 415 /* 416 * For any clocks that may differ per pipe 417 * only the max is stored in this structure 418 */ 419 struct dc_clocks { 420 int dispclk_khz; 421 int actual_dispclk_khz; 422 int dppclk_khz; 423 int actual_dppclk_khz; 424 int disp_dpp_voltage_level_khz; 425 int dcfclk_khz; 426 int socclk_khz; 427 int dcfclk_deep_sleep_khz; 428 int fclk_khz; 429 int phyclk_khz; 430 int dramclk_khz; 431 bool p_state_change_support; 432 enum dcn_zstate_support_state zstate_support; 433 bool dtbclk_en; 434 int ref_dtbclk_khz; 435 int dtbclk_khz; 436 bool fclk_p_state_change_support; 437 enum dcn_pwr_state pwr_state; 438 /* 439 * Elements below are not compared for the purposes of 440 * optimization required 441 */ 442 bool prev_p_state_change_support; 443 bool fclk_prev_p_state_change_support; 444 int num_ways; 445 int prev_num_ways; 446 enum dtm_pstate dtm_level; 447 int max_supported_dppclk_khz; 448 int max_supported_dispclk_khz; 449 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 450 int bw_dispclk_khz; 451 }; 452 453 struct dc_bw_validation_profile { 454 bool enable; 455 456 unsigned long long total_ticks; 457 unsigned long long voltage_level_ticks; 458 unsigned long long watermark_ticks; 459 unsigned long long rq_dlg_ticks; 460 461 unsigned long long total_count; 462 unsigned long long skip_fast_count; 463 unsigned long long skip_pass_count; 464 unsigned long long skip_fail_count; 465 }; 466 467 #define BW_VAL_TRACE_SETUP() \ 468 unsigned long long end_tick = 0; \ 469 unsigned long long voltage_level_tick = 0; \ 470 unsigned long long watermark_tick = 0; \ 471 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 472 dm_get_timestamp(dc->ctx) : 0 473 474 #define BW_VAL_TRACE_COUNT() \ 475 if (dc->debug.bw_val_profile.enable) \ 476 dc->debug.bw_val_profile.total_count++ 477 478 #define BW_VAL_TRACE_SKIP(status) \ 479 if (dc->debug.bw_val_profile.enable) { \ 480 if (!voltage_level_tick) \ 481 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 482 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 483 } 484 485 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 486 if (dc->debug.bw_val_profile.enable) \ 487 voltage_level_tick = dm_get_timestamp(dc->ctx) 488 489 #define BW_VAL_TRACE_END_WATERMARKS() \ 490 if (dc->debug.bw_val_profile.enable) \ 491 watermark_tick = dm_get_timestamp(dc->ctx) 492 493 #define BW_VAL_TRACE_FINISH() \ 494 if (dc->debug.bw_val_profile.enable) { \ 495 end_tick = dm_get_timestamp(dc->ctx); \ 496 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 497 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 498 if (watermark_tick) { \ 499 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 500 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 501 } \ 502 } 503 504 union mem_low_power_enable_options { 505 struct { 506 bool vga: 1; 507 bool i2c: 1; 508 bool dmcu: 1; 509 bool dscl: 1; 510 bool cm: 1; 511 bool mpc: 1; 512 bool optc: 1; 513 bool vpg: 1; 514 bool afmt: 1; 515 } bits; 516 uint32_t u32All; 517 }; 518 519 union root_clock_optimization_options { 520 struct { 521 bool dpp: 1; 522 bool dsc: 1; 523 bool hdmistream: 1; 524 bool hdmichar: 1; 525 bool dpstream: 1; 526 bool symclk32_se: 1; 527 bool symclk32_le: 1; 528 bool symclk_fe: 1; 529 bool physymclk: 1; 530 bool dpiasymclk: 1; 531 uint32_t reserved: 22; 532 } bits; 533 uint32_t u32All; 534 }; 535 536 union dpia_debug_options { 537 struct { 538 uint32_t disable_dpia:1; /* bit 0 */ 539 uint32_t force_non_lttpr:1; /* bit 1 */ 540 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 541 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 542 uint32_t hpd_delay_in_ms:12; /* bits 4-15 */ 543 uint32_t disable_force_tbt3_work_around:1; /* bit 16 */ 544 uint32_t reserved:15; 545 } bits; 546 uint32_t raw; 547 }; 548 549 /* AUX wake work around options 550 * 0: enable/disable work around 551 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 552 * 15-2: reserved 553 * 31-16: timeout in ms 554 */ 555 union aux_wake_wa_options { 556 struct { 557 uint32_t enable_wa : 1; 558 uint32_t use_default_timeout : 1; 559 uint32_t rsvd: 14; 560 uint32_t timeout_ms : 16; 561 } bits; 562 uint32_t raw; 563 }; 564 565 struct dc_debug_data { 566 uint32_t ltFailCount; 567 uint32_t i2cErrorCount; 568 uint32_t auxErrorCount; 569 }; 570 571 struct dc_phy_addr_space_config { 572 struct { 573 uint64_t start_addr; 574 uint64_t end_addr; 575 uint64_t fb_top; 576 uint64_t fb_offset; 577 uint64_t fb_base; 578 uint64_t agp_top; 579 uint64_t agp_bot; 580 uint64_t agp_base; 581 } system_aperture; 582 583 struct { 584 uint64_t page_table_start_addr; 585 uint64_t page_table_end_addr; 586 uint64_t page_table_base_addr; 587 bool base_addr_is_mc_addr; 588 } gart_config; 589 590 bool valid; 591 bool is_hvm_enabled; 592 uint64_t page_table_default_page_addr; 593 }; 594 595 struct dc_virtual_addr_space_config { 596 uint64_t page_table_base_addr; 597 uint64_t page_table_start_addr; 598 uint64_t page_table_end_addr; 599 uint32_t page_table_block_size_in_bytes; 600 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 601 }; 602 603 struct dc_bounding_box_overrides { 604 int sr_exit_time_ns; 605 int sr_enter_plus_exit_time_ns; 606 int urgent_latency_ns; 607 int percent_of_ideal_drambw; 608 int dram_clock_change_latency_ns; 609 int dummy_clock_change_latency_ns; 610 /* This forces a hard min on the DCFCLK we use 611 * for DML. Unlike the debug option for forcing 612 * DCFCLK, this override affects watermark calculations 613 */ 614 int min_dcfclk_mhz; 615 }; 616 617 struct dc_state; 618 struct resource_pool; 619 struct dce_hwseq; 620 621 struct dc_debug_options { 622 bool native422_support; 623 bool disable_dsc; 624 enum visual_confirm visual_confirm; 625 int visual_confirm_rect_height; 626 627 bool sanity_checks; 628 bool max_disp_clk; 629 bool surface_trace; 630 bool timing_trace; 631 bool clock_trace; 632 bool validation_trace; 633 bool bandwidth_calcs_trace; 634 int max_downscale_src_width; 635 636 /* stutter efficiency related */ 637 bool disable_stutter; 638 bool use_max_lb; 639 enum dcc_option disable_dcc; 640 enum pipe_split_policy pipe_split_policy; 641 bool force_single_disp_pipe_split; 642 bool voltage_align_fclk; 643 bool disable_min_fclk; 644 645 bool disable_dfs_bypass; 646 bool disable_dpp_power_gate; 647 bool disable_hubp_power_gate; 648 bool disable_dsc_power_gate; 649 int dsc_min_slice_height_override; 650 int dsc_bpp_increment_div; 651 bool disable_pplib_wm_range; 652 enum wm_report_mode pplib_wm_report_mode; 653 unsigned int min_disp_clk_khz; 654 unsigned int min_dpp_clk_khz; 655 unsigned int min_dram_clk_khz; 656 int sr_exit_time_dpm0_ns; 657 int sr_enter_plus_exit_time_dpm0_ns; 658 int sr_exit_time_ns; 659 int sr_enter_plus_exit_time_ns; 660 int urgent_latency_ns; 661 uint32_t underflow_assert_delay_us; 662 int percent_of_ideal_drambw; 663 int dram_clock_change_latency_ns; 664 bool optimized_watermark; 665 int always_scale; 666 bool disable_pplib_clock_request; 667 bool disable_clock_gate; 668 bool disable_mem_low_power; 669 bool pstate_enabled; 670 bool disable_dmcu; 671 bool disable_psr; 672 bool force_abm_enable; 673 bool disable_stereo_support; 674 bool vsr_support; 675 bool performance_trace; 676 bool az_endpoint_mute_only; 677 bool always_use_regamma; 678 bool recovery_enabled; 679 bool avoid_vbios_exec_table; 680 bool scl_reset_length10; 681 bool hdmi20_disable; 682 bool skip_detection_link_training; 683 uint32_t edid_read_retry_times; 684 bool remove_disconnect_edp; 685 unsigned int force_odm_combine; //bit vector based on otg inst 686 unsigned int seamless_boot_odm_combine; 687 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 688 bool disable_z9_mpc; 689 unsigned int force_fclk_khz; 690 bool enable_tri_buf; 691 bool dmub_offload_enabled; 692 bool dmcub_emulation; 693 bool disable_idle_power_optimizations; 694 unsigned int mall_size_override; 695 unsigned int mall_additional_timer_percent; 696 bool mall_error_as_fatal; 697 bool dmub_command_table; /* for testing only */ 698 struct dc_bw_validation_profile bw_val_profile; 699 bool disable_fec; 700 bool disable_48mhz_pwrdwn; 701 /* This forces a hard min on the DCFCLK requested to SMU/PP 702 * watermarks are not affected. 703 */ 704 unsigned int force_min_dcfclk_mhz; 705 int dwb_fi_phase; 706 bool disable_timing_sync; 707 bool cm_in_bypass; 708 int force_clock_mode;/*every mode change.*/ 709 710 bool disable_dram_clock_change_vactive_support; 711 bool validate_dml_output; 712 bool enable_dmcub_surface_flip; 713 bool usbc_combo_phy_reset_wa; 714 bool disable_dsc_edp; 715 unsigned int force_dsc_edp_policy; 716 bool enable_dram_clock_change_one_display_vactive; 717 /* TODO - remove once tested */ 718 bool legacy_dp2_lt; 719 bool set_mst_en_for_sst; 720 bool disable_uhbr; 721 bool force_dp2_lt_fallback_method; 722 bool ignore_cable_id; 723 union mem_low_power_enable_options enable_mem_low_power; 724 union root_clock_optimization_options root_clock_optimization; 725 bool hpo_optimization; 726 bool force_vblank_alignment; 727 728 /* Enable dmub aux for legacy ddc */ 729 bool enable_dmub_aux_for_legacy_ddc; 730 bool optimize_edp_link_rate; /* eDP ILR */ 731 /* FEC/PSR1 sequence enable delay in 100us */ 732 uint8_t fec_enable_delay_in100us; 733 bool enable_driver_sequence_debug; 734 enum det_size crb_alloc_policy; 735 int crb_alloc_policy_min_disp_count; 736 bool disable_z10; 737 bool enable_z9_disable_interface; 738 bool enable_sw_cntl_psr; 739 union dpia_debug_options dpia_debug; 740 bool force_disable_subvp; 741 bool force_subvp_mclk_switch; 742 bool force_usr_allow; 743 bool apply_vendor_specific_lttpr_wa; 744 bool extended_blank_optimization; 745 union aux_wake_wa_options aux_wake_wa; 746 /* uses value at boot and disables switch */ 747 bool disable_dtb_ref_clk_switch; 748 uint8_t psr_power_use_phy_fsm; 749 enum dml_hostvm_override_opts dml_hostvm_override; 750 }; 751 752 struct gpu_info_soc_bounding_box_v1_0; 753 struct dc { 754 struct dc_debug_options debug; 755 struct dc_versions versions; 756 struct dc_caps caps; 757 struct dc_cap_funcs cap_funcs; 758 struct dc_config config; 759 struct dc_bounding_box_overrides bb_overrides; 760 struct dc_bug_wa work_arounds; 761 struct dc_context *ctx; 762 struct dc_phy_addr_space_config vm_pa_config; 763 764 uint8_t link_count; 765 struct dc_link *links[MAX_PIPES * 2]; 766 767 struct dc_state *current_state; 768 struct resource_pool *res_pool; 769 770 struct clk_mgr *clk_mgr; 771 772 /* Display Engine Clock levels */ 773 struct dm_pp_clock_levels sclk_lvls; 774 775 /* Inputs into BW and WM calculations. */ 776 struct bw_calcs_dceip *bw_dceip; 777 struct bw_calcs_vbios *bw_vbios; 778 struct dcn_soc_bounding_box *dcn_soc; 779 struct dcn_ip_params *dcn_ip; 780 struct display_mode_lib dml; 781 782 /* HW functions */ 783 struct hw_sequencer_funcs hwss; 784 struct dce_hwseq *hwseq; 785 786 /* Require to optimize clocks and bandwidth for added/removed planes */ 787 bool optimized_required; 788 bool wm_optimized_required; 789 bool idle_optimizations_allowed; 790 bool enable_c20_dtm_b0; 791 792 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 793 794 /* FBC compressor */ 795 struct compressor *fbc_compressor; 796 797 struct dc_debug_data debug_data; 798 struct dpcd_vendor_signature vendor_signature; 799 800 const char *build_id; 801 struct vm_helper *vm_helper; 802 }; 803 804 enum frame_buffer_mode { 805 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 806 FRAME_BUFFER_MODE_ZFB_ONLY, 807 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 808 } ; 809 810 struct dchub_init_data { 811 int64_t zfb_phys_addr_base; 812 int64_t zfb_mc_base_addr; 813 uint64_t zfb_size_in_byte; 814 enum frame_buffer_mode fb_mode; 815 bool dchub_initialzied; 816 bool dchub_info_valid; 817 }; 818 819 struct dc_init_data { 820 struct hw_asic_id asic_id; 821 void *driver; /* ctx */ 822 struct cgs_device *cgs_device; 823 struct dc_bounding_box_overrides bb_overrides; 824 825 int num_virtual_links; 826 /* 827 * If 'vbios_override' not NULL, it will be called instead 828 * of the real VBIOS. Intended use is Diagnostics on FPGA. 829 */ 830 struct dc_bios *vbios_override; 831 enum dce_environment dce_environment; 832 833 struct dmub_offload_funcs *dmub_if; 834 struct dc_reg_helper_state *dmub_offload; 835 836 struct dc_config flags; 837 uint64_t log_mask; 838 839 struct dpcd_vendor_signature vendor_signature; 840 bool force_smu_not_present; 841 }; 842 843 struct dc_callback_init { 844 #ifdef CONFIG_DRM_AMD_DC_HDCP 845 struct cp_psp cp_psp; 846 #else 847 uint8_t reserved; 848 #endif 849 }; 850 851 struct dc *dc_create(const struct dc_init_data *init_params); 852 void dc_hardware_init(struct dc *dc); 853 854 int dc_get_vmid_use_vector(struct dc *dc); 855 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 856 /* Returns the number of vmids supported */ 857 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 858 void dc_init_callbacks(struct dc *dc, 859 const struct dc_callback_init *init_params); 860 void dc_deinit_callbacks(struct dc *dc); 861 void dc_destroy(struct dc **dc); 862 863 /******************************************************************************* 864 * Surface Interfaces 865 ******************************************************************************/ 866 867 enum { 868 TRANSFER_FUNC_POINTS = 1025 869 }; 870 871 struct dc_hdr_static_metadata { 872 /* display chromaticities and white point in units of 0.00001 */ 873 unsigned int chromaticity_green_x; 874 unsigned int chromaticity_green_y; 875 unsigned int chromaticity_blue_x; 876 unsigned int chromaticity_blue_y; 877 unsigned int chromaticity_red_x; 878 unsigned int chromaticity_red_y; 879 unsigned int chromaticity_white_point_x; 880 unsigned int chromaticity_white_point_y; 881 882 uint32_t min_luminance; 883 uint32_t max_luminance; 884 uint32_t maximum_content_light_level; 885 uint32_t maximum_frame_average_light_level; 886 }; 887 888 enum dc_transfer_func_type { 889 TF_TYPE_PREDEFINED, 890 TF_TYPE_DISTRIBUTED_POINTS, 891 TF_TYPE_BYPASS, 892 TF_TYPE_HWPWL 893 }; 894 895 struct dc_transfer_func_distributed_points { 896 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 897 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 898 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 899 900 uint16_t end_exponent; 901 uint16_t x_point_at_y1_red; 902 uint16_t x_point_at_y1_green; 903 uint16_t x_point_at_y1_blue; 904 }; 905 906 enum dc_transfer_func_predefined { 907 TRANSFER_FUNCTION_SRGB, 908 TRANSFER_FUNCTION_BT709, 909 TRANSFER_FUNCTION_PQ, 910 TRANSFER_FUNCTION_LINEAR, 911 TRANSFER_FUNCTION_UNITY, 912 TRANSFER_FUNCTION_HLG, 913 TRANSFER_FUNCTION_HLG12, 914 TRANSFER_FUNCTION_GAMMA22, 915 TRANSFER_FUNCTION_GAMMA24, 916 TRANSFER_FUNCTION_GAMMA26 917 }; 918 919 920 struct dc_transfer_func { 921 struct kref refcount; 922 enum dc_transfer_func_type type; 923 enum dc_transfer_func_predefined tf; 924 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 925 uint32_t sdr_ref_white_level; 926 union { 927 struct pwl_params pwl; 928 struct dc_transfer_func_distributed_points tf_pts; 929 }; 930 }; 931 932 933 union dc_3dlut_state { 934 struct { 935 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 936 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 937 uint32_t rmu_mux_num:3; /*index of mux to use*/ 938 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 939 uint32_t mpc_rmu1_mux:4; 940 uint32_t mpc_rmu2_mux:4; 941 uint32_t reserved:15; 942 } bits; 943 uint32_t raw; 944 }; 945 946 947 struct dc_3dlut { 948 struct kref refcount; 949 struct tetrahedral_params lut_3d; 950 struct fixed31_32 hdr_multiplier; 951 union dc_3dlut_state state; 952 }; 953 /* 954 * This structure is filled in by dc_surface_get_status and contains 955 * the last requested address and the currently active address so the called 956 * can determine if there are any outstanding flips 957 */ 958 struct dc_plane_status { 959 struct dc_plane_address requested_address; 960 struct dc_plane_address current_address; 961 bool is_flip_pending; 962 bool is_right_eye; 963 }; 964 965 union surface_update_flags { 966 967 struct { 968 uint32_t addr_update:1; 969 /* Medium updates */ 970 uint32_t dcc_change:1; 971 uint32_t color_space_change:1; 972 uint32_t horizontal_mirror_change:1; 973 uint32_t per_pixel_alpha_change:1; 974 uint32_t global_alpha_change:1; 975 uint32_t hdr_mult:1; 976 uint32_t rotation_change:1; 977 uint32_t swizzle_change:1; 978 uint32_t scaling_change:1; 979 uint32_t position_change:1; 980 uint32_t in_transfer_func_change:1; 981 uint32_t input_csc_change:1; 982 uint32_t coeff_reduction_change:1; 983 uint32_t output_tf_change:1; 984 uint32_t pixel_format_change:1; 985 uint32_t plane_size_change:1; 986 uint32_t gamut_remap_change:1; 987 988 /* Full updates */ 989 uint32_t new_plane:1; 990 uint32_t bpp_change:1; 991 uint32_t gamma_change:1; 992 uint32_t bandwidth_change:1; 993 uint32_t clock_change:1; 994 uint32_t stereo_format_change:1; 995 uint32_t lut_3d:1; 996 uint32_t full_update:1; 997 } bits; 998 999 uint32_t raw; 1000 }; 1001 1002 struct dc_plane_state { 1003 struct dc_plane_address address; 1004 struct dc_plane_flip_time time; 1005 bool triplebuffer_flips; 1006 struct scaling_taps scaling_quality; 1007 struct rect src_rect; 1008 struct rect dst_rect; 1009 struct rect clip_rect; 1010 1011 struct plane_size plane_size; 1012 union dc_tiling_info tiling_info; 1013 1014 struct dc_plane_dcc_param dcc; 1015 1016 struct dc_gamma *gamma_correction; 1017 struct dc_transfer_func *in_transfer_func; 1018 struct dc_bias_and_scale *bias_and_scale; 1019 struct dc_csc_transform input_csc_color_matrix; 1020 struct fixed31_32 coeff_reduction_factor; 1021 struct fixed31_32 hdr_mult; 1022 struct colorspace_transform gamut_remap_matrix; 1023 1024 // TODO: No longer used, remove 1025 struct dc_hdr_static_metadata hdr_static_ctx; 1026 1027 enum dc_color_space color_space; 1028 1029 struct dc_3dlut *lut3d_func; 1030 struct dc_transfer_func *in_shaper_func; 1031 struct dc_transfer_func *blend_tf; 1032 1033 struct dc_transfer_func *gamcor_tf; 1034 enum surface_pixel_format format; 1035 enum dc_rotation_angle rotation; 1036 enum plane_stereo_format stereo_format; 1037 1038 bool is_tiling_rotated; 1039 bool per_pixel_alpha; 1040 bool pre_multiplied_alpha; 1041 bool global_alpha; 1042 int global_alpha_value; 1043 bool visible; 1044 bool flip_immediate; 1045 bool horizontal_mirror; 1046 int layer_index; 1047 1048 union surface_update_flags update_flags; 1049 bool flip_int_enabled; 1050 bool skip_manual_trigger; 1051 1052 /* private to DC core */ 1053 struct dc_plane_status status; 1054 struct dc_context *ctx; 1055 1056 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1057 bool force_full_update; 1058 1059 /* private to dc_surface.c */ 1060 enum dc_irq_source irq_source; 1061 struct kref refcount; 1062 }; 1063 1064 struct dc_plane_info { 1065 struct plane_size plane_size; 1066 union dc_tiling_info tiling_info; 1067 struct dc_plane_dcc_param dcc; 1068 enum surface_pixel_format format; 1069 enum dc_rotation_angle rotation; 1070 enum plane_stereo_format stereo_format; 1071 enum dc_color_space color_space; 1072 bool horizontal_mirror; 1073 bool visible; 1074 bool per_pixel_alpha; 1075 bool pre_multiplied_alpha; 1076 bool global_alpha; 1077 int global_alpha_value; 1078 bool input_csc_enabled; 1079 int layer_index; 1080 }; 1081 1082 struct dc_scaling_info { 1083 struct rect src_rect; 1084 struct rect dst_rect; 1085 struct rect clip_rect; 1086 struct scaling_taps scaling_quality; 1087 }; 1088 1089 struct dc_surface_update { 1090 struct dc_plane_state *surface; 1091 1092 /* isr safe update parameters. null means no updates */ 1093 const struct dc_flip_addrs *flip_addr; 1094 const struct dc_plane_info *plane_info; 1095 const struct dc_scaling_info *scaling_info; 1096 struct fixed31_32 hdr_mult; 1097 /* following updates require alloc/sleep/spin that is not isr safe, 1098 * null means no updates 1099 */ 1100 const struct dc_gamma *gamma; 1101 const struct dc_transfer_func *in_transfer_func; 1102 1103 const struct dc_csc_transform *input_csc_color_matrix; 1104 const struct fixed31_32 *coeff_reduction_factor; 1105 const struct dc_transfer_func *func_shaper; 1106 const struct dc_3dlut *lut3d_func; 1107 const struct dc_transfer_func *blend_tf; 1108 const struct colorspace_transform *gamut_remap_matrix; 1109 }; 1110 1111 /* 1112 * Create a new surface with default parameters; 1113 */ 1114 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1115 const struct dc_plane_status *dc_plane_get_status( 1116 const struct dc_plane_state *plane_state); 1117 1118 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1119 void dc_plane_state_release(struct dc_plane_state *plane_state); 1120 1121 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1122 void dc_gamma_release(struct dc_gamma **dc_gamma); 1123 struct dc_gamma *dc_create_gamma(void); 1124 1125 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1126 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1127 struct dc_transfer_func *dc_create_transfer_func(void); 1128 1129 struct dc_3dlut *dc_create_3dlut_func(void); 1130 void dc_3dlut_func_release(struct dc_3dlut *lut); 1131 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1132 1133 void dc_post_update_surfaces_to_stream( 1134 struct dc *dc); 1135 1136 #include "dc_stream.h" 1137 1138 /* 1139 * Structure to store surface/stream associations for validation 1140 */ 1141 struct dc_validation_set { 1142 struct dc_stream_state *stream; 1143 struct dc_plane_state *plane_states[MAX_SURFACES]; 1144 uint8_t plane_count; 1145 }; 1146 1147 bool dc_validate_boot_timing(const struct dc *dc, 1148 const struct dc_sink *sink, 1149 struct dc_crtc_timing *crtc_timing); 1150 1151 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1152 1153 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1154 1155 bool dc_set_generic_gpio_for_stereo(bool enable, 1156 struct gpio_service *gpio_service); 1157 1158 /* 1159 * fast_validate: we return after determining if we can support the new state, 1160 * but before we populate the programming info 1161 */ 1162 enum dc_status dc_validate_global_state( 1163 struct dc *dc, 1164 struct dc_state *new_ctx, 1165 bool fast_validate); 1166 1167 1168 void dc_resource_state_construct( 1169 const struct dc *dc, 1170 struct dc_state *dst_ctx); 1171 1172 bool dc_acquire_release_mpc_3dlut( 1173 struct dc *dc, bool acquire, 1174 struct dc_stream_state *stream, 1175 struct dc_3dlut **lut, 1176 struct dc_transfer_func **shaper); 1177 1178 void dc_resource_state_copy_construct( 1179 const struct dc_state *src_ctx, 1180 struct dc_state *dst_ctx); 1181 1182 void dc_resource_state_copy_construct_current( 1183 const struct dc *dc, 1184 struct dc_state *dst_ctx); 1185 1186 void dc_resource_state_destruct(struct dc_state *context); 1187 1188 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1189 1190 /* 1191 * TODO update to make it about validation sets 1192 * Set up streams and links associated to drive sinks 1193 * The streams parameter is an absolute set of all active streams. 1194 * 1195 * After this call: 1196 * Phy, Encoder, Timing Generator are programmed and enabled. 1197 * New streams are enabled with blank stream; no memory read. 1198 */ 1199 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1200 1201 struct dc_state *dc_create_state(struct dc *dc); 1202 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1203 void dc_retain_state(struct dc_state *context); 1204 void dc_release_state(struct dc_state *context); 1205 1206 /******************************************************************************* 1207 * Link Interfaces 1208 ******************************************************************************/ 1209 1210 struct dpcd_caps { 1211 union dpcd_rev dpcd_rev; 1212 union max_lane_count max_ln_count; 1213 union max_down_spread max_down_spread; 1214 union dprx_feature dprx_feature; 1215 1216 /* valid only for eDP v1.4 or higher*/ 1217 uint8_t edp_supported_link_rates_count; 1218 enum dc_link_rate edp_supported_link_rates[8]; 1219 1220 /* dongle type (DP converter, CV smart dongle) */ 1221 enum display_dongle_type dongle_type; 1222 bool is_dongle_type_one; 1223 /* branch device or sink device */ 1224 bool is_branch_dev; 1225 /* Dongle's downstream count. */ 1226 union sink_count sink_count; 1227 bool is_mst_capable; 1228 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1229 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1230 struct dc_dongle_caps dongle_caps; 1231 1232 uint32_t sink_dev_id; 1233 int8_t sink_dev_id_str[6]; 1234 int8_t sink_hw_revision; 1235 int8_t sink_fw_revision[2]; 1236 1237 uint32_t branch_dev_id; 1238 int8_t branch_dev_name[6]; 1239 int8_t branch_hw_revision; 1240 int8_t branch_fw_revision[2]; 1241 1242 bool allow_invalid_MSA_timing_param; 1243 bool panel_mode_edp; 1244 bool dpcd_display_control_capable; 1245 bool ext_receiver_cap_field_present; 1246 bool dynamic_backlight_capable_edp; 1247 union dpcd_fec_capability fec_cap; 1248 struct dpcd_dsc_capabilities dsc_caps; 1249 struct dc_lttpr_caps lttpr_caps; 1250 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1251 1252 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1253 union dp_main_line_channel_coding_cap channel_coding_cap; 1254 union dp_sink_video_fallback_formats fallback_formats; 1255 union dp_fec_capability1 fec_cap1; 1256 union dp_cable_id cable_id; 1257 uint8_t edp_rev; 1258 union edp_alpm_caps alpm_caps; 1259 struct edp_psr_info psr_info; 1260 }; 1261 1262 union dpcd_sink_ext_caps { 1263 struct { 1264 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1265 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1266 */ 1267 uint8_t sdr_aux_backlight_control : 1; 1268 uint8_t hdr_aux_backlight_control : 1; 1269 uint8_t reserved_1 : 2; 1270 uint8_t oled : 1; 1271 uint8_t reserved : 3; 1272 } bits; 1273 uint8_t raw; 1274 }; 1275 1276 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1277 union hdcp_rx_caps { 1278 struct { 1279 uint8_t version; 1280 uint8_t reserved; 1281 struct { 1282 uint8_t repeater : 1; 1283 uint8_t hdcp_capable : 1; 1284 uint8_t reserved : 6; 1285 } byte0; 1286 } fields; 1287 uint8_t raw[3]; 1288 }; 1289 1290 union hdcp_bcaps { 1291 struct { 1292 uint8_t HDCP_CAPABLE:1; 1293 uint8_t REPEATER:1; 1294 uint8_t RESERVED:6; 1295 } bits; 1296 uint8_t raw; 1297 }; 1298 1299 struct hdcp_caps { 1300 union hdcp_rx_caps rx_caps; 1301 union hdcp_bcaps bcaps; 1302 }; 1303 #endif 1304 1305 #include "dc_link.h" 1306 1307 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1308 1309 /******************************************************************************* 1310 * Sink Interfaces - A sink corresponds to a display output device 1311 ******************************************************************************/ 1312 1313 struct dc_container_id { 1314 // 128bit GUID in binary form 1315 unsigned char guid[16]; 1316 // 8 byte port ID -> ELD.PortID 1317 unsigned int portId[2]; 1318 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1319 unsigned short manufacturerName; 1320 // 2 byte product code -> ELD.ProductCode 1321 unsigned short productCode; 1322 }; 1323 1324 1325 struct dc_sink_dsc_caps { 1326 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1327 // 'false' if they are sink's DSC caps 1328 bool is_virtual_dpcd_dsc; 1329 #if defined(CONFIG_DRM_AMD_DC_DCN) 1330 // 'true' if MST topology supports DSC passthrough for sink 1331 // 'false' if MST topology does not support DSC passthrough 1332 bool is_dsc_passthrough_supported; 1333 #endif 1334 struct dsc_dec_dpcd_caps dsc_dec_caps; 1335 }; 1336 1337 struct dc_sink_fec_caps { 1338 bool is_rx_fec_supported; 1339 bool is_topology_fec_supported; 1340 }; 1341 1342 /* 1343 * The sink structure contains EDID and other display device properties 1344 */ 1345 struct dc_sink { 1346 enum signal_type sink_signal; 1347 struct dc_edid dc_edid; /* raw edid */ 1348 struct dc_edid_caps edid_caps; /* parse display caps */ 1349 struct dc_container_id *dc_container_id; 1350 uint32_t dongle_max_pix_clk; 1351 void *priv; 1352 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1353 bool converter_disable_audio; 1354 1355 struct dc_sink_dsc_caps dsc_caps; 1356 struct dc_sink_fec_caps fec_caps; 1357 1358 bool is_vsc_sdp_colorimetry_supported; 1359 1360 /* private to DC core */ 1361 struct dc_link *link; 1362 struct dc_context *ctx; 1363 1364 uint32_t sink_id; 1365 1366 /* private to dc_sink.c */ 1367 // refcount must be the last member in dc_sink, since we want the 1368 // sink structure to be logically cloneable up to (but not including) 1369 // refcount 1370 struct kref refcount; 1371 }; 1372 1373 void dc_sink_retain(struct dc_sink *sink); 1374 void dc_sink_release(struct dc_sink *sink); 1375 1376 struct dc_sink_init_data { 1377 enum signal_type sink_signal; 1378 struct dc_link *link; 1379 uint32_t dongle_max_pix_clk; 1380 bool converter_disable_audio; 1381 }; 1382 1383 bool dc_extended_blank_supported(struct dc *dc); 1384 1385 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1386 1387 /* Newer interfaces */ 1388 struct dc_cursor { 1389 struct dc_plane_address address; 1390 struct dc_cursor_attributes attributes; 1391 }; 1392 1393 1394 /******************************************************************************* 1395 * Interrupt interfaces 1396 ******************************************************************************/ 1397 enum dc_irq_source dc_interrupt_to_irq_source( 1398 struct dc *dc, 1399 uint32_t src_id, 1400 uint32_t ext_id); 1401 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1402 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1403 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1404 struct dc *dc, uint32_t link_index); 1405 1406 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1407 1408 /******************************************************************************* 1409 * Power Interfaces 1410 ******************************************************************************/ 1411 1412 void dc_set_power_state( 1413 struct dc *dc, 1414 enum dc_acpi_cm_power_state power_state); 1415 void dc_resume(struct dc *dc); 1416 1417 void dc_power_down_on_boot(struct dc *dc); 1418 1419 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1420 /* 1421 * HDCP Interfaces 1422 */ 1423 enum hdcp_message_status dc_process_hdcp_msg( 1424 enum signal_type signal, 1425 struct dc_link *link, 1426 struct hdcp_protection_message *message_info); 1427 #endif 1428 bool dc_is_dmcu_initialized(struct dc *dc); 1429 1430 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1431 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1432 1433 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1434 struct dc_cursor_attributes *cursor_attr); 1435 1436 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1437 1438 /* 1439 * blank all streams, and set min and max memory clock to 1440 * lowest and highest DPM level, respectively 1441 */ 1442 void dc_unlock_memory_clock_frequency(struct dc *dc); 1443 1444 /* 1445 * set min memory clock to the min required for current mode, 1446 * max to maxDPM, and unblank streams 1447 */ 1448 void dc_lock_memory_clock_frequency(struct dc *dc); 1449 1450 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1451 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1452 1453 /* cleanup on driver unload */ 1454 void dc_hardware_release(struct dc *dc); 1455 1456 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1457 void dc_z10_restore(const struct dc *dc); 1458 void dc_z10_save_init(struct dc *dc); 1459 1460 bool dc_is_dmub_outbox_supported(struct dc *dc); 1461 bool dc_enable_dmub_notifications(struct dc *dc); 1462 1463 void dc_enable_dmub_outbox(struct dc *dc); 1464 1465 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1466 uint32_t link_index, 1467 struct aux_payload *payload); 1468 1469 /* Get dc link index from dpia port index */ 1470 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1471 uint8_t dpia_port_index); 1472 1473 bool dc_process_dmub_set_config_async(struct dc *dc, 1474 uint32_t link_index, 1475 struct set_config_cmd_payload *payload, 1476 struct dmub_notification *notify); 1477 1478 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1479 uint32_t link_index, 1480 uint8_t mst_alloc_slots, 1481 uint8_t *mst_slots_in_use); 1482 1483 /******************************************************************************* 1484 * DSC Interfaces 1485 ******************************************************************************/ 1486 #include "dc_dsc.h" 1487 1488 /******************************************************************************* 1489 * Disable acc mode Interfaces 1490 ******************************************************************************/ 1491 void dc_disable_accelerated_mode(struct dc *dc); 1492 1493 #endif /* DC_INTERFACE_H_ */ 1494