1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "hdcp_msg_types.h" 33 #include "gpio_types.h" 34 #include "link_service_types.h" 35 #include "grph_object_ctrl_defs.h" 36 #include <inc/hw/opp.h> 37 38 #include "inc/hw_sequencer.h" 39 #include "inc/compressor.h" 40 #include "inc/hw/dmcu.h" 41 #include "dml/display_mode_lib.h" 42 43 /* forward declaration */ 44 struct aux_payload; 45 struct set_config_cmd_payload; 46 struct dmub_notification; 47 48 #define DC_VER "3.2.239" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MIN_VIEWPORT_SIZE 12 54 #define MAX_NUM_EDP 2 55 56 /* Display Core Interfaces */ 57 struct dc_versions { 58 const char *dc_ver; 59 struct dmcu_version dmcu_version; 60 }; 61 62 enum dp_protocol_version { 63 DP_VERSION_1_4 = 0, 64 DP_VERSION_2_1, 65 DP_VERSION_UNKNOWN, 66 }; 67 68 enum dc_plane_type { 69 DC_PLANE_TYPE_INVALID, 70 DC_PLANE_TYPE_DCE_RGB, 71 DC_PLANE_TYPE_DCE_UNDERLAY, 72 DC_PLANE_TYPE_DCN_UNIVERSAL, 73 }; 74 75 // Sizes defined as multiples of 64KB 76 enum det_size { 77 DET_SIZE_DEFAULT = 0, 78 DET_SIZE_192KB = 3, 79 DET_SIZE_256KB = 4, 80 DET_SIZE_320KB = 5, 81 DET_SIZE_384KB = 6 82 }; 83 84 85 struct dc_plane_cap { 86 enum dc_plane_type type; 87 uint32_t per_pixel_alpha : 1; 88 struct { 89 uint32_t argb8888 : 1; 90 uint32_t nv12 : 1; 91 uint32_t fp16 : 1; 92 uint32_t p010 : 1; 93 uint32_t ayuv : 1; 94 } pixel_format_support; 95 // max upscaling factor x1000 96 // upscaling factors are always >= 1 97 // for example, 1080p -> 8K is 4.0, or 4000 raw value 98 struct { 99 uint32_t argb8888; 100 uint32_t nv12; 101 uint32_t fp16; 102 } max_upscale_factor; 103 // max downscale factor x1000 104 // downscale factors are always <= 1 105 // for example, 8K -> 1080p is 0.25, or 250 raw value 106 struct { 107 uint32_t argb8888; 108 uint32_t nv12; 109 uint32_t fp16; 110 } max_downscale_factor; 111 // minimal width/height 112 uint32_t min_width; 113 uint32_t min_height; 114 }; 115 116 /** 117 * DOC: color-management-caps 118 * 119 * **Color management caps (DPP and MPC)** 120 * 121 * Modules/color calculates various color operations which are translated to 122 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 123 * DCN1, every new generation comes with fairly major differences in color 124 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 125 * decide mapping to HW block based on logical capabilities. 126 */ 127 128 /** 129 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 130 * @srgb: RGB color space transfer func 131 * @bt2020: BT.2020 transfer func 132 * @gamma2_2: standard gamma 133 * @pq: perceptual quantizer transfer function 134 * @hlg: hybrid log–gamma transfer function 135 */ 136 struct rom_curve_caps { 137 uint16_t srgb : 1; 138 uint16_t bt2020 : 1; 139 uint16_t gamma2_2 : 1; 140 uint16_t pq : 1; 141 uint16_t hlg : 1; 142 }; 143 144 /** 145 * struct dpp_color_caps - color pipeline capabilities for display pipe and 146 * plane blocks 147 * 148 * @dcn_arch: all DCE generations treated the same 149 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 150 * just plain 256-entry lookup 151 * @icsc: input color space conversion 152 * @dgam_ram: programmable degamma LUT 153 * @post_csc: post color space conversion, before gamut remap 154 * @gamma_corr: degamma correction 155 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 156 * with MPC by setting mpc:shared_3d_lut flag 157 * @ogam_ram: programmable out/blend gamma LUT 158 * @ocsc: output color space conversion 159 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 160 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 161 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 162 * 163 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 164 */ 165 struct dpp_color_caps { 166 uint16_t dcn_arch : 1; 167 uint16_t input_lut_shared : 1; 168 uint16_t icsc : 1; 169 uint16_t dgam_ram : 1; 170 uint16_t post_csc : 1; 171 uint16_t gamma_corr : 1; 172 uint16_t hw_3d_lut : 1; 173 uint16_t ogam_ram : 1; 174 uint16_t ocsc : 1; 175 uint16_t dgam_rom_for_yuv : 1; 176 struct rom_curve_caps dgam_rom_caps; 177 struct rom_curve_caps ogam_rom_caps; 178 }; 179 180 /** 181 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 182 * plane combined blocks 183 * 184 * @gamut_remap: color transformation matrix 185 * @ogam_ram: programmable out gamma LUT 186 * @ocsc: output color space conversion matrix 187 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 188 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 189 * instance 190 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 191 */ 192 struct mpc_color_caps { 193 uint16_t gamut_remap : 1; 194 uint16_t ogam_ram : 1; 195 uint16_t ocsc : 1; 196 uint16_t num_3dluts : 3; 197 uint16_t shared_3d_lut:1; 198 struct rom_curve_caps ogam_rom_caps; 199 }; 200 201 /** 202 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 203 * @dpp: color pipes caps for DPP 204 * @mpc: color pipes caps for MPC 205 */ 206 struct dc_color_caps { 207 struct dpp_color_caps dpp; 208 struct mpc_color_caps mpc; 209 }; 210 211 struct dc_dmub_caps { 212 bool psr; 213 bool mclk_sw; 214 bool subvp_psr; 215 bool gecc_enable; 216 }; 217 218 struct dc_caps { 219 uint32_t max_streams; 220 uint32_t max_links; 221 uint32_t max_audios; 222 uint32_t max_slave_planes; 223 uint32_t max_slave_yuv_planes; 224 uint32_t max_slave_rgb_planes; 225 uint32_t max_planes; 226 uint32_t max_downscale_ratio; 227 uint32_t i2c_speed_in_khz; 228 uint32_t i2c_speed_in_khz_hdcp; 229 uint32_t dmdata_alloc_size; 230 unsigned int max_cursor_size; 231 unsigned int max_video_width; 232 unsigned int min_horizontal_blanking_period; 233 int linear_pitch_alignment; 234 bool dcc_const_color; 235 bool dynamic_audio; 236 bool is_apu; 237 bool dual_link_dvi; 238 bool post_blend_color_processing; 239 bool force_dp_tps4_for_cp2520; 240 bool disable_dp_clk_share; 241 bool psp_setup_panel_mode; 242 bool extended_aux_timeout_support; 243 bool dmcub_support; 244 bool zstate_support; 245 uint32_t num_of_internal_disp; 246 enum dp_protocol_version max_dp_protocol_version; 247 unsigned int mall_size_per_mem_channel; 248 unsigned int mall_size_total; 249 unsigned int cursor_cache_size; 250 struct dc_plane_cap planes[MAX_PLANES]; 251 struct dc_color_caps color; 252 struct dc_dmub_caps dmub_caps; 253 bool dp_hpo; 254 bool dp_hdmi21_pcon_support; 255 bool edp_dsc_support; 256 bool vbios_lttpr_aware; 257 bool vbios_lttpr_enable; 258 uint32_t max_otg_num; 259 uint32_t max_cab_allocation_bytes; 260 uint32_t cache_line_size; 261 uint32_t cache_num_ways; 262 uint16_t subvp_fw_processing_delay_us; 263 uint8_t subvp_drr_max_vblank_margin_us; 264 uint16_t subvp_prefetch_end_to_mall_start_us; 265 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 266 uint16_t subvp_pstate_allow_width_us; 267 uint16_t subvp_vertical_int_margin_us; 268 bool seamless_odm; 269 uint32_t max_v_total; 270 uint8_t subvp_drr_vblank_start_margin_us; 271 }; 272 273 struct dc_bug_wa { 274 bool no_connect_phy_config; 275 bool dedcn20_305_wa; 276 bool skip_clock_update; 277 bool lt_early_cr_pattern; 278 struct { 279 uint8_t uclk : 1; 280 uint8_t fclk : 1; 281 uint8_t dcfclk : 1; 282 uint8_t dcfclk_ds: 1; 283 } clock_update_disable_mask; 284 }; 285 struct dc_dcc_surface_param { 286 struct dc_size surface_size; 287 enum surface_pixel_format format; 288 enum swizzle_mode_values swizzle_mode; 289 enum dc_scan_direction scan; 290 }; 291 292 struct dc_dcc_setting { 293 unsigned int max_compressed_blk_size; 294 unsigned int max_uncompressed_blk_size; 295 bool independent_64b_blks; 296 //These bitfields to be used starting with DCN 297 struct { 298 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 299 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 300 uint32_t dcc_256_128_128 : 1; //available starting with DCN 301 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 302 } dcc_controls; 303 }; 304 305 struct dc_surface_dcc_cap { 306 union { 307 struct { 308 struct dc_dcc_setting rgb; 309 } grph; 310 311 struct { 312 struct dc_dcc_setting luma; 313 struct dc_dcc_setting chroma; 314 } video; 315 }; 316 317 bool capable; 318 bool const_color_support; 319 }; 320 321 struct dc_static_screen_params { 322 struct { 323 bool force_trigger; 324 bool cursor_update; 325 bool surface_update; 326 bool overlay_update; 327 } triggers; 328 unsigned int num_frames; 329 }; 330 331 332 /* Surface update type is used by dc_update_surfaces_and_stream 333 * The update type is determined at the very beginning of the function based 334 * on parameters passed in and decides how much programming (or updating) is 335 * going to be done during the call. 336 * 337 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 338 * logical calculations or hardware register programming. This update MUST be 339 * ISR safe on windows. Currently fast update will only be used to flip surface 340 * address. 341 * 342 * UPDATE_TYPE_MED is used for slower updates which require significant hw 343 * re-programming however do not affect bandwidth consumption or clock 344 * requirements. At present, this is the level at which front end updates 345 * that do not require us to run bw_calcs happen. These are in/out transfer func 346 * updates, viewport offset changes, recout size changes and pixel depth changes. 347 * This update can be done at ISR, but we want to minimize how often this happens. 348 * 349 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 350 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 351 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 352 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 353 * a full update. This cannot be done at ISR level and should be a rare event. 354 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 355 * underscan we don't expect to see this call at all. 356 */ 357 358 enum surface_update_type { 359 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 360 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 361 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 362 }; 363 364 /* Forward declaration*/ 365 struct dc; 366 struct dc_plane_state; 367 struct dc_state; 368 369 370 struct dc_cap_funcs { 371 bool (*get_dcc_compression_cap)(const struct dc *dc, 372 const struct dc_dcc_surface_param *input, 373 struct dc_surface_dcc_cap *output); 374 }; 375 376 struct link_training_settings; 377 378 union allow_lttpr_non_transparent_mode { 379 struct { 380 bool DP1_4A : 1; 381 bool DP2_0 : 1; 382 } bits; 383 unsigned char raw; 384 }; 385 386 /* Structure to hold configuration flags set by dm at dc creation. */ 387 struct dc_config { 388 bool gpu_vm_support; 389 bool disable_disp_pll_sharing; 390 bool fbc_support; 391 bool disable_fractional_pwm; 392 bool allow_seamless_boot_optimization; 393 bool seamless_boot_edp_requested; 394 bool edp_not_connected; 395 bool edp_no_power_sequencing; 396 bool force_enum_edp; 397 bool forced_clocks; 398 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 399 bool multi_mon_pp_mclk_switch; 400 bool disable_dmcu; 401 bool enable_4to1MPC; 402 bool enable_windowed_mpo_odm; 403 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 404 uint32_t allow_edp_hotplug_detection; 405 bool clamp_min_dcfclk; 406 uint64_t vblank_alignment_dto_params; 407 uint8_t vblank_alignment_max_frame_time_diff; 408 bool is_asymmetric_memory; 409 bool is_single_rank_dimm; 410 bool is_vmin_only_asic; 411 bool use_pipe_ctx_sync_logic; 412 bool ignore_dpref_ss; 413 bool enable_mipi_converter_optimization; 414 bool use_default_clock_table; 415 bool force_bios_enable_lttpr; 416 uint8_t force_bios_fixed_vs; 417 int sdpif_request_limit_words_per_umc; 418 bool use_old_fixed_vs_sequence; 419 bool disable_subvp_drr; 420 }; 421 422 enum visual_confirm { 423 VISUAL_CONFIRM_DISABLE = 0, 424 VISUAL_CONFIRM_SURFACE = 1, 425 VISUAL_CONFIRM_HDR = 2, 426 VISUAL_CONFIRM_MPCTREE = 4, 427 VISUAL_CONFIRM_PSR = 5, 428 VISUAL_CONFIRM_SWAPCHAIN = 6, 429 VISUAL_CONFIRM_FAMS = 7, 430 VISUAL_CONFIRM_SWIZZLE = 9, 431 VISUAL_CONFIRM_SUBVP = 14, 432 VISUAL_CONFIRM_MCLK_SWITCH = 16, 433 }; 434 435 enum dc_psr_power_opts { 436 psr_power_opt_invalid = 0x0, 437 psr_power_opt_smu_opt_static_screen = 0x1, 438 psr_power_opt_z10_static_screen = 0x10, 439 psr_power_opt_ds_disable_allow = 0x100, 440 }; 441 442 enum dml_hostvm_override_opts { 443 DML_HOSTVM_NO_OVERRIDE = 0x0, 444 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 445 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 446 }; 447 448 enum dcc_option { 449 DCC_ENABLE = 0, 450 DCC_DISABLE = 1, 451 DCC_HALF_REQ_DISALBE = 2, 452 }; 453 454 /** 455 * enum pipe_split_policy - Pipe split strategy supported by DCN 456 * 457 * This enum is used to define the pipe split policy supported by DCN. By 458 * default, DC favors MPC_SPLIT_DYNAMIC. 459 */ 460 enum pipe_split_policy { 461 /** 462 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 463 * pipe in order to bring the best trade-off between performance and 464 * power consumption. This is the recommended option. 465 */ 466 MPC_SPLIT_DYNAMIC = 0, 467 468 /** 469 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 470 * try any sort of split optimization. 471 */ 472 MPC_SPLIT_AVOID = 1, 473 474 /** 475 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 476 * optimize the pipe utilization when using a single display; if the 477 * user connects to a second display, DC will avoid pipe split. 478 */ 479 MPC_SPLIT_AVOID_MULT_DISP = 2, 480 }; 481 482 enum wm_report_mode { 483 WM_REPORT_DEFAULT = 0, 484 WM_REPORT_OVERRIDE = 1, 485 }; 486 enum dtm_pstate{ 487 dtm_level_p0 = 0,/*highest voltage*/ 488 dtm_level_p1, 489 dtm_level_p2, 490 dtm_level_p3, 491 dtm_level_p4,/*when active_display_count = 0*/ 492 }; 493 494 enum dcn_pwr_state { 495 DCN_PWR_STATE_UNKNOWN = -1, 496 DCN_PWR_STATE_MISSION_MODE = 0, 497 DCN_PWR_STATE_LOW_POWER = 3, 498 }; 499 500 enum dcn_zstate_support_state { 501 DCN_ZSTATE_SUPPORT_UNKNOWN, 502 DCN_ZSTATE_SUPPORT_ALLOW, 503 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 504 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 505 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 506 DCN_ZSTATE_SUPPORT_DISALLOW, 507 }; 508 509 /** 510 * struct dc_clocks - DC pipe clocks 511 * 512 * For any clocks that may differ per pipe only the max is stored in this 513 * structure 514 */ 515 struct dc_clocks { 516 int dispclk_khz; 517 int actual_dispclk_khz; 518 int dppclk_khz; 519 int actual_dppclk_khz; 520 int disp_dpp_voltage_level_khz; 521 int dcfclk_khz; 522 int socclk_khz; 523 int dcfclk_deep_sleep_khz; 524 int fclk_khz; 525 int phyclk_khz; 526 int dramclk_khz; 527 bool p_state_change_support; 528 enum dcn_zstate_support_state zstate_support; 529 bool dtbclk_en; 530 int ref_dtbclk_khz; 531 bool fclk_p_state_change_support; 532 enum dcn_pwr_state pwr_state; 533 /* 534 * Elements below are not compared for the purposes of 535 * optimization required 536 */ 537 bool prev_p_state_change_support; 538 bool fclk_prev_p_state_change_support; 539 int num_ways; 540 541 /* 542 * @fw_based_mclk_switching 543 * 544 * DC has a mechanism that leverage the variable refresh rate to switch 545 * memory clock in cases that we have a large latency to achieve the 546 * memory clock change and a short vblank window. DC has some 547 * requirements to enable this feature, and this field describes if the 548 * system support or not such a feature. 549 */ 550 bool fw_based_mclk_switching; 551 bool fw_based_mclk_switching_shut_down; 552 int prev_num_ways; 553 enum dtm_pstate dtm_level; 554 int max_supported_dppclk_khz; 555 int max_supported_dispclk_khz; 556 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 557 int bw_dispclk_khz; 558 }; 559 560 struct dc_bw_validation_profile { 561 bool enable; 562 563 unsigned long long total_ticks; 564 unsigned long long voltage_level_ticks; 565 unsigned long long watermark_ticks; 566 unsigned long long rq_dlg_ticks; 567 568 unsigned long long total_count; 569 unsigned long long skip_fast_count; 570 unsigned long long skip_pass_count; 571 unsigned long long skip_fail_count; 572 }; 573 574 #define BW_VAL_TRACE_SETUP() \ 575 unsigned long long end_tick = 0; \ 576 unsigned long long voltage_level_tick = 0; \ 577 unsigned long long watermark_tick = 0; \ 578 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 579 dm_get_timestamp(dc->ctx) : 0 580 581 #define BW_VAL_TRACE_COUNT() \ 582 if (dc->debug.bw_val_profile.enable) \ 583 dc->debug.bw_val_profile.total_count++ 584 585 #define BW_VAL_TRACE_SKIP(status) \ 586 if (dc->debug.bw_val_profile.enable) { \ 587 if (!voltage_level_tick) \ 588 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 589 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 590 } 591 592 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 593 if (dc->debug.bw_val_profile.enable) \ 594 voltage_level_tick = dm_get_timestamp(dc->ctx) 595 596 #define BW_VAL_TRACE_END_WATERMARKS() \ 597 if (dc->debug.bw_val_profile.enable) \ 598 watermark_tick = dm_get_timestamp(dc->ctx) 599 600 #define BW_VAL_TRACE_FINISH() \ 601 if (dc->debug.bw_val_profile.enable) { \ 602 end_tick = dm_get_timestamp(dc->ctx); \ 603 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 604 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 605 if (watermark_tick) { \ 606 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 607 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 608 } \ 609 } 610 611 union mem_low_power_enable_options { 612 struct { 613 bool vga: 1; 614 bool i2c: 1; 615 bool dmcu: 1; 616 bool dscl: 1; 617 bool cm: 1; 618 bool mpc: 1; 619 bool optc: 1; 620 bool vpg: 1; 621 bool afmt: 1; 622 } bits; 623 uint32_t u32All; 624 }; 625 626 union root_clock_optimization_options { 627 struct { 628 bool dpp: 1; 629 bool dsc: 1; 630 bool hdmistream: 1; 631 bool hdmichar: 1; 632 bool dpstream: 1; 633 bool symclk32_se: 1; 634 bool symclk32_le: 1; 635 bool symclk_fe: 1; 636 bool physymclk: 1; 637 bool dpiasymclk: 1; 638 uint32_t reserved: 22; 639 } bits; 640 uint32_t u32All; 641 }; 642 643 union dpia_debug_options { 644 struct { 645 uint32_t disable_dpia:1; /* bit 0 */ 646 uint32_t force_non_lttpr:1; /* bit 1 */ 647 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 648 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 649 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 650 uint32_t reserved:27; 651 } bits; 652 uint32_t raw; 653 }; 654 655 /* AUX wake work around options 656 * 0: enable/disable work around 657 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 658 * 15-2: reserved 659 * 31-16: timeout in ms 660 */ 661 union aux_wake_wa_options { 662 struct { 663 uint32_t enable_wa : 1; 664 uint32_t use_default_timeout : 1; 665 uint32_t rsvd: 14; 666 uint32_t timeout_ms : 16; 667 } bits; 668 uint32_t raw; 669 }; 670 671 struct dc_debug_data { 672 uint32_t ltFailCount; 673 uint32_t i2cErrorCount; 674 uint32_t auxErrorCount; 675 }; 676 677 struct dc_phy_addr_space_config { 678 struct { 679 uint64_t start_addr; 680 uint64_t end_addr; 681 uint64_t fb_top; 682 uint64_t fb_offset; 683 uint64_t fb_base; 684 uint64_t agp_top; 685 uint64_t agp_bot; 686 uint64_t agp_base; 687 } system_aperture; 688 689 struct { 690 uint64_t page_table_start_addr; 691 uint64_t page_table_end_addr; 692 uint64_t page_table_base_addr; 693 bool base_addr_is_mc_addr; 694 } gart_config; 695 696 bool valid; 697 bool is_hvm_enabled; 698 uint64_t page_table_default_page_addr; 699 }; 700 701 struct dc_virtual_addr_space_config { 702 uint64_t page_table_base_addr; 703 uint64_t page_table_start_addr; 704 uint64_t page_table_end_addr; 705 uint32_t page_table_block_size_in_bytes; 706 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 707 }; 708 709 struct dc_bounding_box_overrides { 710 int sr_exit_time_ns; 711 int sr_enter_plus_exit_time_ns; 712 int sr_exit_z8_time_ns; 713 int sr_enter_plus_exit_z8_time_ns; 714 int urgent_latency_ns; 715 int percent_of_ideal_drambw; 716 int dram_clock_change_latency_ns; 717 int dummy_clock_change_latency_ns; 718 int fclk_clock_change_latency_ns; 719 /* This forces a hard min on the DCFCLK we use 720 * for DML. Unlike the debug option for forcing 721 * DCFCLK, this override affects watermark calculations 722 */ 723 int min_dcfclk_mhz; 724 }; 725 726 struct dc_state; 727 struct resource_pool; 728 struct dce_hwseq; 729 struct link_service; 730 731 /** 732 * struct dc_debug_options - DC debug struct 733 * 734 * This struct provides a simple mechanism for developers to change some 735 * configurations, enable/disable features, and activate extra debug options. 736 * This can be very handy to narrow down whether some specific feature is 737 * causing an issue or not. 738 */ 739 struct dc_debug_options { 740 bool native422_support; 741 bool disable_dsc; 742 enum visual_confirm visual_confirm; 743 int visual_confirm_rect_height; 744 745 bool sanity_checks; 746 bool max_disp_clk; 747 bool surface_trace; 748 bool timing_trace; 749 bool clock_trace; 750 bool validation_trace; 751 bool bandwidth_calcs_trace; 752 int max_downscale_src_width; 753 754 /* stutter efficiency related */ 755 bool disable_stutter; 756 bool use_max_lb; 757 enum dcc_option disable_dcc; 758 759 /** 760 * @pipe_split_policy: Define which pipe split policy is used by the 761 * display core. 762 */ 763 enum pipe_split_policy pipe_split_policy; 764 bool force_single_disp_pipe_split; 765 bool voltage_align_fclk; 766 bool disable_min_fclk; 767 768 bool disable_dfs_bypass; 769 bool disable_dpp_power_gate; 770 bool disable_hubp_power_gate; 771 bool disable_dsc_power_gate; 772 int dsc_min_slice_height_override; 773 int dsc_bpp_increment_div; 774 bool disable_pplib_wm_range; 775 enum wm_report_mode pplib_wm_report_mode; 776 unsigned int min_disp_clk_khz; 777 unsigned int min_dpp_clk_khz; 778 unsigned int min_dram_clk_khz; 779 int sr_exit_time_dpm0_ns; 780 int sr_enter_plus_exit_time_dpm0_ns; 781 int sr_exit_time_ns; 782 int sr_enter_plus_exit_time_ns; 783 int sr_exit_z8_time_ns; 784 int sr_enter_plus_exit_z8_time_ns; 785 int urgent_latency_ns; 786 uint32_t underflow_assert_delay_us; 787 int percent_of_ideal_drambw; 788 int dram_clock_change_latency_ns; 789 bool optimized_watermark; 790 int always_scale; 791 bool disable_pplib_clock_request; 792 bool disable_clock_gate; 793 bool disable_mem_low_power; 794 bool pstate_enabled; 795 bool disable_dmcu; 796 bool force_abm_enable; 797 bool disable_stereo_support; 798 bool vsr_support; 799 bool performance_trace; 800 bool az_endpoint_mute_only; 801 bool always_use_regamma; 802 bool recovery_enabled; 803 bool avoid_vbios_exec_table; 804 bool scl_reset_length10; 805 bool hdmi20_disable; 806 bool skip_detection_link_training; 807 uint32_t edid_read_retry_times; 808 unsigned int force_odm_combine; //bit vector based on otg inst 809 unsigned int seamless_boot_odm_combine; 810 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 811 int minimum_z8_residency_time; 812 bool disable_z9_mpc; 813 unsigned int force_fclk_khz; 814 bool enable_tri_buf; 815 bool dmub_offload_enabled; 816 bool dmcub_emulation; 817 bool disable_idle_power_optimizations; 818 unsigned int mall_size_override; 819 unsigned int mall_additional_timer_percent; 820 bool mall_error_as_fatal; 821 bool dmub_command_table; /* for testing only */ 822 struct dc_bw_validation_profile bw_val_profile; 823 bool disable_fec; 824 bool disable_48mhz_pwrdwn; 825 /* This forces a hard min on the DCFCLK requested to SMU/PP 826 * watermarks are not affected. 827 */ 828 unsigned int force_min_dcfclk_mhz; 829 int dwb_fi_phase; 830 bool disable_timing_sync; 831 bool cm_in_bypass; 832 int force_clock_mode;/*every mode change.*/ 833 834 bool disable_dram_clock_change_vactive_support; 835 bool validate_dml_output; 836 bool enable_dmcub_surface_flip; 837 bool usbc_combo_phy_reset_wa; 838 bool enable_dram_clock_change_one_display_vactive; 839 /* TODO - remove once tested */ 840 bool legacy_dp2_lt; 841 bool set_mst_en_for_sst; 842 bool disable_uhbr; 843 bool force_dp2_lt_fallback_method; 844 bool ignore_cable_id; 845 union mem_low_power_enable_options enable_mem_low_power; 846 union root_clock_optimization_options root_clock_optimization; 847 bool hpo_optimization; 848 bool force_vblank_alignment; 849 850 /* Enable dmub aux for legacy ddc */ 851 bool enable_dmub_aux_for_legacy_ddc; 852 bool disable_fams; 853 /* FEC/PSR1 sequence enable delay in 100us */ 854 uint8_t fec_enable_delay_in100us; 855 bool enable_driver_sequence_debug; 856 enum det_size crb_alloc_policy; 857 int crb_alloc_policy_min_disp_count; 858 bool disable_z10; 859 bool enable_z9_disable_interface; 860 bool psr_skip_crtc_disable; 861 union dpia_debug_options dpia_debug; 862 bool disable_fixed_vs_aux_timeout_wa; 863 bool force_disable_subvp; 864 bool force_subvp_mclk_switch; 865 bool allow_sw_cursor_fallback; 866 unsigned int force_subvp_num_ways; 867 unsigned int force_mall_ss_num_ways; 868 bool alloc_extra_way_for_cursor; 869 uint32_t subvp_extra_lines; 870 bool force_usr_allow; 871 /* uses value at boot and disables switch */ 872 bool disable_dtb_ref_clk_switch; 873 bool extended_blank_optimization; 874 union aux_wake_wa_options aux_wake_wa; 875 uint32_t mst_start_top_delay; 876 uint8_t psr_power_use_phy_fsm; 877 enum dml_hostvm_override_opts dml_hostvm_override; 878 bool dml_disallow_alternate_prefetch_modes; 879 bool use_legacy_soc_bb_mechanism; 880 bool exit_idle_opt_for_cursor_updates; 881 bool enable_single_display_2to1_odm_policy; 882 bool enable_double_buffered_dsc_pg_support; 883 bool enable_dp_dig_pixel_rate_div_policy; 884 enum lttpr_mode lttpr_mode_override; 885 unsigned int dsc_delay_factor_wa_x1000; 886 unsigned int min_prefetch_in_strobe_ns; 887 bool disable_unbounded_requesting; 888 bool dig_fifo_off_in_blank; 889 bool temp_mst_deallocation_sequence; 890 bool override_dispclk_programming; 891 bool disable_fpo_optimizations; 892 bool support_eDP1_5; 893 uint32_t fpo_vactive_margin_us; 894 bool disable_fpo_vactive; 895 bool disable_boot_optimizations; 896 bool override_odm_optimization; 897 bool minimize_dispclk_using_odm; 898 bool disable_subvp_high_refresh; 899 bool disable_dp_plus_plus_wa; 900 uint32_t fpo_vactive_min_active_margin_us; 901 uint32_t fpo_vactive_max_blank_us; 902 bool enable_legacy_fast_update; 903 bool disable_dc_mode_overwrite; 904 }; 905 906 struct gpu_info_soc_bounding_box_v1_0; 907 struct dc { 908 struct dc_debug_options debug; 909 struct dc_versions versions; 910 struct dc_caps caps; 911 struct dc_cap_funcs cap_funcs; 912 struct dc_config config; 913 struct dc_bounding_box_overrides bb_overrides; 914 struct dc_bug_wa work_arounds; 915 struct dc_context *ctx; 916 struct dc_phy_addr_space_config vm_pa_config; 917 918 uint8_t link_count; 919 struct dc_link *links[MAX_PIPES * 2]; 920 struct link_service *link_srv; 921 922 struct dc_state *current_state; 923 struct resource_pool *res_pool; 924 925 struct clk_mgr *clk_mgr; 926 927 /* Display Engine Clock levels */ 928 struct dm_pp_clock_levels sclk_lvls; 929 930 /* Inputs into BW and WM calculations. */ 931 struct bw_calcs_dceip *bw_dceip; 932 struct bw_calcs_vbios *bw_vbios; 933 struct dcn_soc_bounding_box *dcn_soc; 934 struct dcn_ip_params *dcn_ip; 935 struct display_mode_lib dml; 936 937 /* HW functions */ 938 struct hw_sequencer_funcs hwss; 939 struct dce_hwseq *hwseq; 940 941 /* Require to optimize clocks and bandwidth for added/removed planes */ 942 bool optimized_required; 943 bool wm_optimized_required; 944 bool idle_optimizations_allowed; 945 bool enable_c20_dtm_b0; 946 947 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 948 949 /* FBC compressor */ 950 struct compressor *fbc_compressor; 951 952 struct dc_debug_data debug_data; 953 struct dpcd_vendor_signature vendor_signature; 954 955 const char *build_id; 956 struct vm_helper *vm_helper; 957 958 uint32_t *dcn_reg_offsets; 959 uint32_t *nbio_reg_offsets; 960 961 /* Scratch memory */ 962 struct { 963 struct { 964 /* 965 * For matching clock_limits table in driver with table 966 * from PMFW. 967 */ 968 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 969 } update_bw_bounding_box; 970 } scratch; 971 }; 972 973 enum frame_buffer_mode { 974 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 975 FRAME_BUFFER_MODE_ZFB_ONLY, 976 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 977 } ; 978 979 struct dchub_init_data { 980 int64_t zfb_phys_addr_base; 981 int64_t zfb_mc_base_addr; 982 uint64_t zfb_size_in_byte; 983 enum frame_buffer_mode fb_mode; 984 bool dchub_initialzied; 985 bool dchub_info_valid; 986 }; 987 988 struct dc_init_data { 989 struct hw_asic_id asic_id; 990 void *driver; /* ctx */ 991 struct cgs_device *cgs_device; 992 struct dc_bounding_box_overrides bb_overrides; 993 994 int num_virtual_links; 995 /* 996 * If 'vbios_override' not NULL, it will be called instead 997 * of the real VBIOS. Intended use is Diagnostics on FPGA. 998 */ 999 struct dc_bios *vbios_override; 1000 enum dce_environment dce_environment; 1001 1002 struct dmub_offload_funcs *dmub_if; 1003 struct dc_reg_helper_state *dmub_offload; 1004 1005 struct dc_config flags; 1006 uint64_t log_mask; 1007 1008 struct dpcd_vendor_signature vendor_signature; 1009 bool force_smu_not_present; 1010 /* 1011 * IP offset for run time initializaion of register addresses 1012 * 1013 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1014 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1015 * before them. 1016 */ 1017 uint32_t *dcn_reg_offsets; 1018 uint32_t *nbio_reg_offsets; 1019 }; 1020 1021 struct dc_callback_init { 1022 struct cp_psp cp_psp; 1023 }; 1024 1025 struct dc *dc_create(const struct dc_init_data *init_params); 1026 void dc_hardware_init(struct dc *dc); 1027 1028 int dc_get_vmid_use_vector(struct dc *dc); 1029 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1030 /* Returns the number of vmids supported */ 1031 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1032 void dc_init_callbacks(struct dc *dc, 1033 const struct dc_callback_init *init_params); 1034 void dc_deinit_callbacks(struct dc *dc); 1035 void dc_destroy(struct dc **dc); 1036 1037 /* Surface Interfaces */ 1038 1039 enum { 1040 TRANSFER_FUNC_POINTS = 1025 1041 }; 1042 1043 struct dc_hdr_static_metadata { 1044 /* display chromaticities and white point in units of 0.00001 */ 1045 unsigned int chromaticity_green_x; 1046 unsigned int chromaticity_green_y; 1047 unsigned int chromaticity_blue_x; 1048 unsigned int chromaticity_blue_y; 1049 unsigned int chromaticity_red_x; 1050 unsigned int chromaticity_red_y; 1051 unsigned int chromaticity_white_point_x; 1052 unsigned int chromaticity_white_point_y; 1053 1054 uint32_t min_luminance; 1055 uint32_t max_luminance; 1056 uint32_t maximum_content_light_level; 1057 uint32_t maximum_frame_average_light_level; 1058 }; 1059 1060 enum dc_transfer_func_type { 1061 TF_TYPE_PREDEFINED, 1062 TF_TYPE_DISTRIBUTED_POINTS, 1063 TF_TYPE_BYPASS, 1064 TF_TYPE_HWPWL 1065 }; 1066 1067 struct dc_transfer_func_distributed_points { 1068 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1069 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1070 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1071 1072 uint16_t end_exponent; 1073 uint16_t x_point_at_y1_red; 1074 uint16_t x_point_at_y1_green; 1075 uint16_t x_point_at_y1_blue; 1076 }; 1077 1078 enum dc_transfer_func_predefined { 1079 TRANSFER_FUNCTION_SRGB, 1080 TRANSFER_FUNCTION_BT709, 1081 TRANSFER_FUNCTION_PQ, 1082 TRANSFER_FUNCTION_LINEAR, 1083 TRANSFER_FUNCTION_UNITY, 1084 TRANSFER_FUNCTION_HLG, 1085 TRANSFER_FUNCTION_HLG12, 1086 TRANSFER_FUNCTION_GAMMA22, 1087 TRANSFER_FUNCTION_GAMMA24, 1088 TRANSFER_FUNCTION_GAMMA26 1089 }; 1090 1091 1092 struct dc_transfer_func { 1093 struct kref refcount; 1094 enum dc_transfer_func_type type; 1095 enum dc_transfer_func_predefined tf; 1096 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1097 uint32_t sdr_ref_white_level; 1098 union { 1099 struct pwl_params pwl; 1100 struct dc_transfer_func_distributed_points tf_pts; 1101 }; 1102 }; 1103 1104 1105 union dc_3dlut_state { 1106 struct { 1107 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1108 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1109 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1110 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1111 uint32_t mpc_rmu1_mux:4; 1112 uint32_t mpc_rmu2_mux:4; 1113 uint32_t reserved:15; 1114 } bits; 1115 uint32_t raw; 1116 }; 1117 1118 1119 struct dc_3dlut { 1120 struct kref refcount; 1121 struct tetrahedral_params lut_3d; 1122 struct fixed31_32 hdr_multiplier; 1123 union dc_3dlut_state state; 1124 }; 1125 /* 1126 * This structure is filled in by dc_surface_get_status and contains 1127 * the last requested address and the currently active address so the called 1128 * can determine if there are any outstanding flips 1129 */ 1130 struct dc_plane_status { 1131 struct dc_plane_address requested_address; 1132 struct dc_plane_address current_address; 1133 bool is_flip_pending; 1134 bool is_right_eye; 1135 }; 1136 1137 union surface_update_flags { 1138 1139 struct { 1140 uint32_t addr_update:1; 1141 /* Medium updates */ 1142 uint32_t dcc_change:1; 1143 uint32_t color_space_change:1; 1144 uint32_t horizontal_mirror_change:1; 1145 uint32_t per_pixel_alpha_change:1; 1146 uint32_t global_alpha_change:1; 1147 uint32_t hdr_mult:1; 1148 uint32_t rotation_change:1; 1149 uint32_t swizzle_change:1; 1150 uint32_t scaling_change:1; 1151 uint32_t position_change:1; 1152 uint32_t in_transfer_func_change:1; 1153 uint32_t input_csc_change:1; 1154 uint32_t coeff_reduction_change:1; 1155 uint32_t output_tf_change:1; 1156 uint32_t pixel_format_change:1; 1157 uint32_t plane_size_change:1; 1158 uint32_t gamut_remap_change:1; 1159 1160 /* Full updates */ 1161 uint32_t new_plane:1; 1162 uint32_t bpp_change:1; 1163 uint32_t gamma_change:1; 1164 uint32_t bandwidth_change:1; 1165 uint32_t clock_change:1; 1166 uint32_t stereo_format_change:1; 1167 uint32_t lut_3d:1; 1168 uint32_t tmz_changed:1; 1169 uint32_t full_update:1; 1170 } bits; 1171 1172 uint32_t raw; 1173 }; 1174 1175 struct dc_plane_state { 1176 struct dc_plane_address address; 1177 struct dc_plane_flip_time time; 1178 bool triplebuffer_flips; 1179 struct scaling_taps scaling_quality; 1180 struct rect src_rect; 1181 struct rect dst_rect; 1182 struct rect clip_rect; 1183 1184 struct plane_size plane_size; 1185 union dc_tiling_info tiling_info; 1186 1187 struct dc_plane_dcc_param dcc; 1188 1189 struct dc_gamma *gamma_correction; 1190 struct dc_transfer_func *in_transfer_func; 1191 struct dc_bias_and_scale *bias_and_scale; 1192 struct dc_csc_transform input_csc_color_matrix; 1193 struct fixed31_32 coeff_reduction_factor; 1194 struct fixed31_32 hdr_mult; 1195 struct colorspace_transform gamut_remap_matrix; 1196 1197 // TODO: No longer used, remove 1198 struct dc_hdr_static_metadata hdr_static_ctx; 1199 1200 enum dc_color_space color_space; 1201 1202 struct dc_3dlut *lut3d_func; 1203 struct dc_transfer_func *in_shaper_func; 1204 struct dc_transfer_func *blend_tf; 1205 1206 struct dc_transfer_func *gamcor_tf; 1207 enum surface_pixel_format format; 1208 enum dc_rotation_angle rotation; 1209 enum plane_stereo_format stereo_format; 1210 1211 bool is_tiling_rotated; 1212 bool per_pixel_alpha; 1213 bool pre_multiplied_alpha; 1214 bool global_alpha; 1215 int global_alpha_value; 1216 bool visible; 1217 bool flip_immediate; 1218 bool horizontal_mirror; 1219 int layer_index; 1220 1221 union surface_update_flags update_flags; 1222 bool flip_int_enabled; 1223 bool skip_manual_trigger; 1224 1225 /* private to DC core */ 1226 struct dc_plane_status status; 1227 struct dc_context *ctx; 1228 1229 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1230 bool force_full_update; 1231 1232 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1233 1234 /* private to dc_surface.c */ 1235 enum dc_irq_source irq_source; 1236 struct kref refcount; 1237 struct tg_color visual_confirm_color; 1238 1239 bool is_statically_allocated; 1240 }; 1241 1242 struct dc_plane_info { 1243 struct plane_size plane_size; 1244 union dc_tiling_info tiling_info; 1245 struct dc_plane_dcc_param dcc; 1246 enum surface_pixel_format format; 1247 enum dc_rotation_angle rotation; 1248 enum plane_stereo_format stereo_format; 1249 enum dc_color_space color_space; 1250 bool horizontal_mirror; 1251 bool visible; 1252 bool per_pixel_alpha; 1253 bool pre_multiplied_alpha; 1254 bool global_alpha; 1255 int global_alpha_value; 1256 bool input_csc_enabled; 1257 int layer_index; 1258 }; 1259 1260 struct dc_scaling_info { 1261 struct rect src_rect; 1262 struct rect dst_rect; 1263 struct rect clip_rect; 1264 struct scaling_taps scaling_quality; 1265 }; 1266 1267 struct dc_surface_update { 1268 struct dc_plane_state *surface; 1269 1270 /* isr safe update parameters. null means no updates */ 1271 const struct dc_flip_addrs *flip_addr; 1272 const struct dc_plane_info *plane_info; 1273 const struct dc_scaling_info *scaling_info; 1274 struct fixed31_32 hdr_mult; 1275 /* following updates require alloc/sleep/spin that is not isr safe, 1276 * null means no updates 1277 */ 1278 const struct dc_gamma *gamma; 1279 const struct dc_transfer_func *in_transfer_func; 1280 1281 const struct dc_csc_transform *input_csc_color_matrix; 1282 const struct fixed31_32 *coeff_reduction_factor; 1283 const struct dc_transfer_func *func_shaper; 1284 const struct dc_3dlut *lut3d_func; 1285 const struct dc_transfer_func *blend_tf; 1286 const struct colorspace_transform *gamut_remap_matrix; 1287 }; 1288 1289 /* 1290 * Create a new surface with default parameters; 1291 */ 1292 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1293 const struct dc_plane_status *dc_plane_get_status( 1294 const struct dc_plane_state *plane_state); 1295 1296 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1297 void dc_plane_state_release(struct dc_plane_state *plane_state); 1298 1299 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1300 void dc_gamma_release(struct dc_gamma **dc_gamma); 1301 struct dc_gamma *dc_create_gamma(void); 1302 1303 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1304 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1305 struct dc_transfer_func *dc_create_transfer_func(void); 1306 1307 struct dc_3dlut *dc_create_3dlut_func(void); 1308 void dc_3dlut_func_release(struct dc_3dlut *lut); 1309 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1310 1311 void dc_post_update_surfaces_to_stream( 1312 struct dc *dc); 1313 1314 #include "dc_stream.h" 1315 1316 /** 1317 * struct dc_validation_set - Struct to store surface/stream associations for validation 1318 */ 1319 struct dc_validation_set { 1320 /** 1321 * @stream: Stream state properties 1322 */ 1323 struct dc_stream_state *stream; 1324 1325 /** 1326 * @plane_state: Surface state 1327 */ 1328 struct dc_plane_state *plane_states[MAX_SURFACES]; 1329 1330 /** 1331 * @plane_count: Total of active planes 1332 */ 1333 uint8_t plane_count; 1334 }; 1335 1336 bool dc_validate_boot_timing(const struct dc *dc, 1337 const struct dc_sink *sink, 1338 struct dc_crtc_timing *crtc_timing); 1339 1340 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1341 1342 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1343 1344 enum dc_status dc_validate_with_context(struct dc *dc, 1345 const struct dc_validation_set set[], 1346 int set_count, 1347 struct dc_state *context, 1348 bool fast_validate); 1349 1350 bool dc_set_generic_gpio_for_stereo(bool enable, 1351 struct gpio_service *gpio_service); 1352 1353 /* 1354 * fast_validate: we return after determining if we can support the new state, 1355 * but before we populate the programming info 1356 */ 1357 enum dc_status dc_validate_global_state( 1358 struct dc *dc, 1359 struct dc_state *new_ctx, 1360 bool fast_validate); 1361 1362 1363 void dc_resource_state_construct( 1364 const struct dc *dc, 1365 struct dc_state *dst_ctx); 1366 1367 bool dc_acquire_release_mpc_3dlut( 1368 struct dc *dc, bool acquire, 1369 struct dc_stream_state *stream, 1370 struct dc_3dlut **lut, 1371 struct dc_transfer_func **shaper); 1372 1373 void dc_resource_state_copy_construct( 1374 const struct dc_state *src_ctx, 1375 struct dc_state *dst_ctx); 1376 1377 void dc_resource_state_copy_construct_current( 1378 const struct dc *dc, 1379 struct dc_state *dst_ctx); 1380 1381 void dc_resource_state_destruct(struct dc_state *context); 1382 1383 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1384 1385 enum dc_status dc_commit_streams(struct dc *dc, 1386 struct dc_stream_state *streams[], 1387 uint8_t stream_count); 1388 1389 struct dc_state *dc_create_state(struct dc *dc); 1390 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1391 void dc_retain_state(struct dc_state *context); 1392 void dc_release_state(struct dc_state *context); 1393 1394 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1395 struct dc_stream_state *stream, 1396 int mpcc_inst); 1397 1398 1399 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1400 1401 /* The function returns minimum bandwidth required to drive a given timing 1402 * return - minimum required timing bandwidth in kbps. 1403 */ 1404 uint32_t dc_bandwidth_in_kbps_from_timing(const struct dc_crtc_timing *timing); 1405 1406 /* Link Interfaces */ 1407 /* 1408 * A link contains one or more sinks and their connected status. 1409 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1410 */ 1411 struct dc_link { 1412 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1413 unsigned int sink_count; 1414 struct dc_sink *local_sink; 1415 unsigned int link_index; 1416 enum dc_connection_type type; 1417 enum signal_type connector_signal; 1418 enum dc_irq_source irq_source_hpd; 1419 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1420 1421 bool is_hpd_filter_disabled; 1422 bool dp_ss_off; 1423 1424 /** 1425 * @link_state_valid: 1426 * 1427 * If there is no link and local sink, this variable should be set to 1428 * false. Otherwise, it should be set to true; usually, the function 1429 * core_link_enable_stream sets this field to true. 1430 */ 1431 bool link_state_valid; 1432 bool aux_access_disabled; 1433 bool sync_lt_in_progress; 1434 bool skip_stream_reenable; 1435 bool is_internal_display; 1436 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1437 bool is_dig_mapping_flexible; 1438 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1439 bool is_hpd_pending; /* Indicates a new received hpd */ 1440 bool is_automated; /* Indicates automated testing */ 1441 1442 bool edp_sink_present; 1443 1444 struct dp_trace dp_trace; 1445 1446 /* caps is the same as reported_link_cap. link_traing use 1447 * reported_link_cap. Will clean up. TODO 1448 */ 1449 struct dc_link_settings reported_link_cap; 1450 struct dc_link_settings verified_link_cap; 1451 struct dc_link_settings cur_link_settings; 1452 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1453 struct dc_link_settings preferred_link_setting; 1454 /* preferred_training_settings are override values that 1455 * come from DM. DM is responsible for the memory 1456 * management of the override pointers. 1457 */ 1458 struct dc_link_training_overrides preferred_training_settings; 1459 struct dp_audio_test_data audio_test_data; 1460 1461 uint8_t ddc_hw_inst; 1462 1463 uint8_t hpd_src; 1464 1465 uint8_t link_enc_hw_inst; 1466 /* DIG link encoder ID. Used as index in link encoder resource pool. 1467 * For links with fixed mapping to DIG, this is not changed after dc_link 1468 * object creation. 1469 */ 1470 enum engine_id eng_id; 1471 1472 bool test_pattern_enabled; 1473 union compliance_test_state compliance_test_state; 1474 1475 void *priv; 1476 1477 struct ddc_service *ddc; 1478 1479 enum dp_panel_mode panel_mode; 1480 bool aux_mode; 1481 1482 /* Private to DC core */ 1483 1484 const struct dc *dc; 1485 1486 struct dc_context *ctx; 1487 1488 struct panel_cntl *panel_cntl; 1489 struct link_encoder *link_enc; 1490 struct graphics_object_id link_id; 1491 /* Endpoint type distinguishes display endpoints which do not have entries 1492 * in the BIOS connector table from those that do. Helps when tracking link 1493 * encoder to display endpoint assignments. 1494 */ 1495 enum display_endpoint_type ep_type; 1496 union ddi_channel_mapping ddi_channel_mapping; 1497 struct connector_device_tag_info device_tag; 1498 struct dpcd_caps dpcd_caps; 1499 uint32_t dongle_max_pix_clk; 1500 unsigned short chip_caps; 1501 unsigned int dpcd_sink_count; 1502 struct hdcp_caps hdcp_caps; 1503 enum edp_revision edp_revision; 1504 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1505 1506 struct psr_settings psr_settings; 1507 1508 /* Drive settings read from integrated info table */ 1509 struct dc_lane_settings bios_forced_drive_settings; 1510 1511 /* Vendor specific LTTPR workaround variables */ 1512 uint8_t vendor_specific_lttpr_link_rate_wa; 1513 bool apply_vendor_specific_lttpr_link_rate_wa; 1514 1515 /* MST record stream using this link */ 1516 struct link_flags { 1517 bool dp_keep_receiver_powered; 1518 bool dp_skip_DID2; 1519 bool dp_skip_reset_segment; 1520 bool dp_skip_fs_144hz; 1521 bool dp_mot_reset_segment; 1522 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1523 bool dpia_mst_dsc_always_on; 1524 /* Forced DPIA into TBT3 compatibility mode. */ 1525 bool dpia_forced_tbt3_mode; 1526 bool dongle_mode_timing_override; 1527 bool blank_stream_on_ocs_change; 1528 } wa_flags; 1529 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1530 1531 struct dc_link_status link_status; 1532 struct dprx_states dprx_states; 1533 1534 struct gpio *hpd_gpio; 1535 enum dc_link_fec_state fec_state; 1536 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1537 1538 struct dc_panel_config panel_config; 1539 struct phy_state phy_state; 1540 // BW ALLOCATON USB4 ONLY 1541 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1542 }; 1543 1544 /* Return an enumerated dc_link. 1545 * dc_link order is constant and determined at 1546 * boot time. They cannot be created or destroyed. 1547 * Use dc_get_caps() to get number of links. 1548 */ 1549 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1550 1551 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1552 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1553 const struct dc_link *link, 1554 unsigned int *inst_out); 1555 1556 /* Return an array of link pointers to edp links. */ 1557 void dc_get_edp_links(const struct dc *dc, 1558 struct dc_link **edp_links, 1559 int *edp_num); 1560 1561 /* The function initiates detection handshake over the given link. It first 1562 * determines if there are display connections over the link. If so it initiates 1563 * detection protocols supported by the connected receiver device. The function 1564 * contains protocol specific handshake sequences which are sometimes mandatory 1565 * to establish a proper connection between TX and RX. So it is always 1566 * recommended to call this function as the first link operation upon HPD event 1567 * or power up event. Upon completion, the function will update link structure 1568 * in place based on latest RX capabilities. The function may also cause dpms 1569 * to be reset to off for all currently enabled streams to the link. It is DM's 1570 * responsibility to serialize detection and DPMS updates. 1571 * 1572 * @reason - Indicate which event triggers this detection. dc may customize 1573 * detection flow depending on the triggering events. 1574 * return false - if detection is not fully completed. This could happen when 1575 * there is an unrecoverable error during detection or detection is partially 1576 * completed (detection has been delegated to dm mst manager ie. 1577 * link->connection_type == dc_connection_mst_branch when returning false). 1578 * return true - detection is completed, link has been fully updated with latest 1579 * detection result. 1580 */ 1581 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1582 1583 struct dc_sink_init_data; 1584 1585 /* When link connection type is dc_connection_mst_branch, remote sink can be 1586 * added to the link. The interface creates a remote sink and associates it with 1587 * current link. The sink will be retained by link until remove remote sink is 1588 * called. 1589 * 1590 * @dc_link - link the remote sink will be added to. 1591 * @edid - byte array of EDID raw data. 1592 * @len - size of the edid in byte 1593 * @init_data - 1594 */ 1595 struct dc_sink *dc_link_add_remote_sink( 1596 struct dc_link *dc_link, 1597 const uint8_t *edid, 1598 int len, 1599 struct dc_sink_init_data *init_data); 1600 1601 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1602 * @link - link the sink should be removed from 1603 * @sink - sink to be removed. 1604 */ 1605 void dc_link_remove_remote_sink( 1606 struct dc_link *link, 1607 struct dc_sink *sink); 1608 1609 /* Enable HPD interrupt handler for a given link */ 1610 void dc_link_enable_hpd(const struct dc_link *link); 1611 1612 /* Disable HPD interrupt handler for a given link */ 1613 void dc_link_disable_hpd(const struct dc_link *link); 1614 1615 /* determine if there is a sink connected to the link 1616 * 1617 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1618 * return - false if an unexpected error occurs, true otherwise. 1619 * 1620 * NOTE: This function doesn't detect downstream sink connections i.e 1621 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1622 * return dc_connection_single if the branch device is connected despite of 1623 * downstream sink's connection status. 1624 */ 1625 bool dc_link_detect_connection_type(struct dc_link *link, 1626 enum dc_connection_type *type); 1627 1628 /* query current hpd pin value 1629 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1630 * 1631 */ 1632 bool dc_link_get_hpd_state(struct dc_link *link); 1633 1634 /* Getter for cached link status from given link */ 1635 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1636 1637 /* enable/disable hardware HPD filter. 1638 * 1639 * @link - The link the HPD pin is associated with. 1640 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1641 * handler once after no HPD change has been detected within dc default HPD 1642 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1643 * pulses within default HPD interval, no HPD event will be received until HPD 1644 * toggles have stopped. Then HPD event will be queued to irq handler once after 1645 * dc default HPD filtering interval since last HPD event. 1646 * 1647 * @enable = false - disable hardware HPD filter. HPD event will be queued 1648 * immediately to irq handler after no HPD change has been detected within 1649 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1650 */ 1651 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1652 1653 /* submit i2c read/write payloads through ddc channel 1654 * @link_index - index to a link with ddc in i2c mode 1655 * @cmd - i2c command structure 1656 * return - true if success, false otherwise. 1657 */ 1658 bool dc_submit_i2c( 1659 struct dc *dc, 1660 uint32_t link_index, 1661 struct i2c_command *cmd); 1662 1663 /* submit i2c read/write payloads through oem channel 1664 * @link_index - index to a link with ddc in i2c mode 1665 * @cmd - i2c command structure 1666 * return - true if success, false otherwise. 1667 */ 1668 bool dc_submit_i2c_oem( 1669 struct dc *dc, 1670 struct i2c_command *cmd); 1671 1672 enum aux_return_code_type; 1673 /* Attempt to transfer the given aux payload. This function does not perform 1674 * retries or handle error states. The reply is returned in the payload->reply 1675 * and the result through operation_result. Returns the number of bytes 1676 * transferred,or -1 on a failure. 1677 */ 1678 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1679 struct aux_payload *payload, 1680 enum aux_return_code_type *operation_result); 1681 1682 bool dc_is_oem_i2c_device_present( 1683 struct dc *dc, 1684 size_t slave_address 1685 ); 1686 1687 /* return true if the connected receiver supports the hdcp version */ 1688 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1689 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1690 1691 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1692 * 1693 * TODO - When defer_handling is true the function will have a different purpose. 1694 * It no longer does complete hpd rx irq handling. We should create a separate 1695 * interface specifically for this case. 1696 * 1697 * Return: 1698 * true - Downstream port status changed. DM should call DC to do the 1699 * detection. 1700 * false - no change in Downstream port status. No further action required 1701 * from DM. 1702 */ 1703 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1704 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1705 bool defer_handling, bool *has_left_work); 1706 /* handle DP specs define test automation sequence*/ 1707 void dc_link_dp_handle_automated_test(struct dc_link *link); 1708 1709 /* handle DP Link loss sequence and try to recover RX link loss with best 1710 * effort 1711 */ 1712 void dc_link_dp_handle_link_loss(struct dc_link *link); 1713 1714 /* Determine if hpd rx irq should be handled or ignored 1715 * return true - hpd rx irq should be handled. 1716 * return false - it is safe to ignore hpd rx irq event 1717 */ 1718 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1719 1720 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1721 * @link - link the hpd irq data associated with 1722 * @hpd_irq_dpcd_data - input hpd irq data 1723 * return - true if hpd irq data indicates a link lost 1724 */ 1725 bool dc_link_check_link_loss_status(struct dc_link *link, 1726 union hpd_irq_data *hpd_irq_dpcd_data); 1727 1728 /* Read hpd rx irq data from a given link 1729 * @link - link where the hpd irq data should be read from 1730 * @irq_data - output hpd irq data 1731 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1732 * read has failed. 1733 */ 1734 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1735 struct dc_link *link, 1736 union hpd_irq_data *irq_data); 1737 1738 /* The function clears recorded DP RX states in the link. DM should call this 1739 * function when it is resuming from S3 power state to previously connected links. 1740 * 1741 * TODO - in the future we should consider to expand link resume interface to 1742 * support clearing previous rx states. So we don't have to rely on dm to call 1743 * this interface explicitly. 1744 */ 1745 void dc_link_clear_dprx_states(struct dc_link *link); 1746 1747 /* Destruct the mst topology of the link and reset the allocated payload table 1748 * 1749 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1750 * still wants to reset MST topology on an unplug event */ 1751 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1752 1753 /* The function calculates effective DP link bandwidth when a given link is 1754 * using the given link settings. 1755 * 1756 * return - total effective link bandwidth in kbps. 1757 */ 1758 uint32_t dc_link_bandwidth_kbps( 1759 const struct dc_link *link, 1760 const struct dc_link_settings *link_setting); 1761 1762 /* The function takes a snapshot of current link resource allocation state 1763 * @dc: pointer to dc of the dm calling this 1764 * @map: a dc link resource snapshot defined internally to dc. 1765 * 1766 * DM needs to capture a snapshot of current link resource allocation mapping 1767 * and store it in its persistent storage. 1768 * 1769 * Some of the link resource is using first come first serve policy. 1770 * The allocation mapping depends on original hotplug order. This information 1771 * is lost after driver is loaded next time. The snapshot is used in order to 1772 * restore link resource to its previous state so user will get consistent 1773 * link capability allocation across reboot. 1774 * 1775 */ 1776 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1777 1778 /* This function restores link resource allocation state from a snapshot 1779 * @dc: pointer to dc of the dm calling this 1780 * @map: a dc link resource snapshot defined internally to dc. 1781 * 1782 * DM needs to call this function after initial link detection on boot and 1783 * before first commit streams to restore link resource allocation state 1784 * from previous boot session. 1785 * 1786 * Some of the link resource is using first come first serve policy. 1787 * The allocation mapping depends on original hotplug order. This information 1788 * is lost after driver is loaded next time. The snapshot is used in order to 1789 * restore link resource to its previous state so user will get consistent 1790 * link capability allocation across reboot. 1791 * 1792 */ 1793 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1794 1795 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1796 * interface i.e stream_update->dsc_config 1797 */ 1798 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1799 1800 /* translate a raw link rate data to bandwidth in kbps */ 1801 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 1802 1803 /* determine the optimal bandwidth given link and required bw. 1804 * @link - current detected link 1805 * @req_bw - requested bandwidth in kbps 1806 * @link_settings - returned most optimal link settings that can fit the 1807 * requested bandwidth 1808 * return - false if link can't support requested bandwidth, true if link 1809 * settings is found. 1810 */ 1811 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1812 struct dc_link_settings *link_settings, 1813 uint32_t req_bw); 1814 1815 /* return the max dp link settings can be driven by the link without considering 1816 * connected RX device and its capability 1817 */ 1818 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1819 struct dc_link_settings *max_link_enc_cap); 1820 1821 /* determine when the link is driving MST mode, what DP link channel coding 1822 * format will be used. The decision will remain unchanged until next HPD event. 1823 * 1824 * @link - a link with DP RX connection 1825 * return - if stream is committed to this link with MST signal type, type of 1826 * channel coding format dc will choose. 1827 */ 1828 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1829 const struct dc_link *link); 1830 1831 /* get max dp link settings the link can enable with all things considered. (i.e 1832 * TX/RX/Cable capabilities and dp override policies. 1833 * 1834 * @link - a link with DP RX connection 1835 * return - max dp link settings the link can enable. 1836 * 1837 */ 1838 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 1839 1840 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 1841 * to a link with dp connector signal type. 1842 * @link - a link with dp connector signal type 1843 * return - true if connected, false otherwise 1844 */ 1845 bool dc_link_is_dp_sink_present(struct dc_link *link); 1846 1847 /* Force DP lane settings update to main-link video signal and notify the change 1848 * to DP RX via DPCD. This is a debug interface used for video signal integrity 1849 * tuning purpose. The interface assumes link has already been enabled with DP 1850 * signal. 1851 * 1852 * @lt_settings - a container structure with desired hw_lane_settings 1853 */ 1854 void dc_link_set_drive_settings(struct dc *dc, 1855 struct link_training_settings *lt_settings, 1856 struct dc_link *link); 1857 1858 /* Enable a test pattern in Link or PHY layer in an active link for compliance 1859 * test or debugging purpose. The test pattern will remain until next un-plug. 1860 * 1861 * @link - active link with DP signal output enabled. 1862 * @test_pattern - desired test pattern to output. 1863 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 1864 * @test_pattern_color_space - for video test pattern choose a desired color 1865 * space. 1866 * @p_link_settings - For PHY pattern choose a desired link settings 1867 * @p_custom_pattern - some test pattern will require a custom input to 1868 * customize some pattern details. Otherwise keep it to NULL. 1869 * @cust_pattern_size - size of the custom pattern input. 1870 * 1871 */ 1872 bool dc_link_dp_set_test_pattern( 1873 struct dc_link *link, 1874 enum dp_test_pattern test_pattern, 1875 enum dp_test_pattern_color_space test_pattern_color_space, 1876 const struct link_training_settings *p_link_settings, 1877 const unsigned char *p_custom_pattern, 1878 unsigned int cust_pattern_size); 1879 1880 /* Force DP link settings to always use a specific value until reboot to a 1881 * specific link. If link has already been enabled, the interface will also 1882 * switch to desired link settings immediately. This is a debug interface to 1883 * generic dp issue trouble shooting. 1884 */ 1885 void dc_link_set_preferred_link_settings(struct dc *dc, 1886 struct dc_link_settings *link_setting, 1887 struct dc_link *link); 1888 1889 /* Force DP link to customize a specific link training behavior by overriding to 1890 * standard DP specs defined protocol. This is a debug interface to trouble shoot 1891 * display specific link training issues or apply some display specific 1892 * workaround in link training. 1893 * 1894 * @link_settings - if not NULL, force preferred link settings to the link. 1895 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 1896 * will apply this particular override in future link training. If NULL is 1897 * passed in, dc resets previous overrides. 1898 * NOTE: DM must keep the memory from override pointers until DM resets preferred 1899 * training settings. 1900 */ 1901 void dc_link_set_preferred_training_settings(struct dc *dc, 1902 struct dc_link_settings *link_setting, 1903 struct dc_link_training_overrides *lt_overrides, 1904 struct dc_link *link, 1905 bool skip_immediate_retrain); 1906 1907 /* return - true if FEC is supported with connected DP RX, false otherwise */ 1908 bool dc_link_is_fec_supported(const struct dc_link *link); 1909 1910 /* query FEC enablement policy to determine if FEC will be enabled by dc during 1911 * link enablement. 1912 * return - true if FEC should be enabled, false otherwise. 1913 */ 1914 bool dc_link_should_enable_fec(const struct dc_link *link); 1915 1916 /* determine lttpr mode the current link should be enabled with a specific link 1917 * settings. 1918 */ 1919 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 1920 struct dc_link_settings *link_setting); 1921 1922 /* Force DP RX to update its power state. 1923 * NOTE: this interface doesn't update dp main-link. Calling this function will 1924 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 1925 * RX power state back upon finish DM specific execution requiring DP RX in a 1926 * specific power state. 1927 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 1928 * state. 1929 */ 1930 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 1931 1932 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 1933 * current value read from extended receiver cap from 02200h - 0220Fh. 1934 * Some DP RX has problems of providing accurate DP receiver caps from extended 1935 * field, this interface is a workaround to revert link back to use base caps. 1936 */ 1937 void dc_link_overwrite_extended_receiver_cap( 1938 struct dc_link *link); 1939 1940 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 1941 bool wait_for_hpd); 1942 1943 /* Set backlight level of an embedded panel (eDP, LVDS). 1944 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 1945 * and 16 bit fractional, where 1.0 is max backlight value. 1946 */ 1947 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 1948 uint32_t backlight_pwm_u16_16, 1949 uint32_t frame_ramp); 1950 1951 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 1952 bool dc_link_set_backlight_level_nits(struct dc_link *link, 1953 bool isHDR, 1954 uint32_t backlight_millinits, 1955 uint32_t transition_time_in_ms); 1956 1957 bool dc_link_get_backlight_level_nits(struct dc_link *link, 1958 uint32_t *backlight_millinits, 1959 uint32_t *backlight_millinits_peak); 1960 1961 int dc_link_get_backlight_level(const struct dc_link *dc_link); 1962 1963 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 1964 1965 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 1966 bool wait, bool force_static, const unsigned int *power_opts); 1967 1968 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 1969 1970 bool dc_link_setup_psr(struct dc_link *dc_link, 1971 const struct dc_stream_state *stream, struct psr_config *psr_config, 1972 struct psr_context *psr_context); 1973 1974 /* On eDP links this function call will stall until T12 has elapsed. 1975 * If the panel is not in power off state, this function will return 1976 * immediately. 1977 */ 1978 bool dc_link_wait_for_t12(struct dc_link *link); 1979 1980 /* Determine if dp trace has been initialized to reflect upto date result * 1981 * return - true if trace is initialized and has valid data. False dp trace 1982 * doesn't have valid result. 1983 */ 1984 bool dc_dp_trace_is_initialized(struct dc_link *link); 1985 1986 /* Query a dp trace flag to indicate if the current dp trace data has been 1987 * logged before 1988 */ 1989 bool dc_dp_trace_is_logged(struct dc_link *link, 1990 bool in_detection); 1991 1992 /* Set dp trace flag to indicate whether DM has already logged the current dp 1993 * trace data. DM can set is_logged to true upon logging and check 1994 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 1995 */ 1996 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 1997 bool in_detection, 1998 bool is_logged); 1999 2000 /* Obtain driver time stamp for last dp link training end. The time stamp is 2001 * formatted based on dm_get_timestamp DM function. 2002 * @in_detection - true to get link training end time stamp of last link 2003 * training in detection sequence. false to get link training end time stamp 2004 * of last link training in commit (dpms) sequence 2005 */ 2006 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2007 bool in_detection); 2008 2009 /* Get how many link training attempts dc has done with latest sequence. 2010 * @in_detection - true to get link training count of last link 2011 * training in detection sequence. false to get link training count of last link 2012 * training in commit (dpms) sequence 2013 */ 2014 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2015 bool in_detection); 2016 2017 /* Get how many link loss has happened since last link training attempts */ 2018 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2019 2020 /* 2021 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2022 */ 2023 /* 2024 * Send a request from DP-Tx requesting to allocate BW remotely after 2025 * allocating it locally. This will get processed by CM and a CB function 2026 * will be called. 2027 * 2028 * @link: pointer to the dc_link struct instance 2029 * @req_bw: The requested bw in Kbyte to allocated 2030 * 2031 * return: none 2032 */ 2033 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2034 2035 /* 2036 * Handle function for when the status of the Request above is complete. 2037 * We will find out the result of allocating on CM and update structs. 2038 * 2039 * @link: pointer to the dc_link struct instance 2040 * @bw: Allocated or Estimated BW depending on the result 2041 * @result: Response type 2042 * 2043 * return: none 2044 */ 2045 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2046 uint8_t bw, uint8_t result); 2047 2048 /* 2049 * Handle the USB4 BW Allocation related functionality here: 2050 * Plug => Try to allocate max bw from timing parameters supported by the sink 2051 * Unplug => de-allocate bw 2052 * 2053 * @link: pointer to the dc_link struct instance 2054 * @peak_bw: Peak bw used by the link/sink 2055 * 2056 * return: allocated bw else return 0 2057 */ 2058 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2059 struct dc_link *link, int peak_bw); 2060 2061 /* 2062 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2063 * available BW for each host router 2064 * 2065 * @dc: pointer to dc struct 2066 * @stream: pointer to all possible streams 2067 * @num_streams: number of valid DPIA streams 2068 * 2069 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2070 */ 2071 bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, 2072 const unsigned int count); 2073 2074 /* Sink Interfaces - A sink corresponds to a display output device */ 2075 2076 struct dc_container_id { 2077 // 128bit GUID in binary form 2078 unsigned char guid[16]; 2079 // 8 byte port ID -> ELD.PortID 2080 unsigned int portId[2]; 2081 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2082 unsigned short manufacturerName; 2083 // 2 byte product code -> ELD.ProductCode 2084 unsigned short productCode; 2085 }; 2086 2087 2088 struct dc_sink_dsc_caps { 2089 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2090 // 'false' if they are sink's DSC caps 2091 bool is_virtual_dpcd_dsc; 2092 #if defined(CONFIG_DRM_AMD_DC_FP) 2093 // 'true' if MST topology supports DSC passthrough for sink 2094 // 'false' if MST topology does not support DSC passthrough 2095 bool is_dsc_passthrough_supported; 2096 #endif 2097 struct dsc_dec_dpcd_caps dsc_dec_caps; 2098 }; 2099 2100 struct dc_sink_fec_caps { 2101 bool is_rx_fec_supported; 2102 bool is_topology_fec_supported; 2103 }; 2104 2105 struct scdc_caps { 2106 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2107 union hdmi_scdc_device_id_data device_id; 2108 }; 2109 2110 /* 2111 * The sink structure contains EDID and other display device properties 2112 */ 2113 struct dc_sink { 2114 enum signal_type sink_signal; 2115 struct dc_edid dc_edid; /* raw edid */ 2116 struct dc_edid_caps edid_caps; /* parse display caps */ 2117 struct dc_container_id *dc_container_id; 2118 uint32_t dongle_max_pix_clk; 2119 void *priv; 2120 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2121 bool converter_disable_audio; 2122 2123 struct scdc_caps scdc_caps; 2124 struct dc_sink_dsc_caps dsc_caps; 2125 struct dc_sink_fec_caps fec_caps; 2126 2127 bool is_vsc_sdp_colorimetry_supported; 2128 2129 /* private to DC core */ 2130 struct dc_link *link; 2131 struct dc_context *ctx; 2132 2133 uint32_t sink_id; 2134 2135 /* private to dc_sink.c */ 2136 // refcount must be the last member in dc_sink, since we want the 2137 // sink structure to be logically cloneable up to (but not including) 2138 // refcount 2139 struct kref refcount; 2140 }; 2141 2142 void dc_sink_retain(struct dc_sink *sink); 2143 void dc_sink_release(struct dc_sink *sink); 2144 2145 struct dc_sink_init_data { 2146 enum signal_type sink_signal; 2147 struct dc_link *link; 2148 uint32_t dongle_max_pix_clk; 2149 bool converter_disable_audio; 2150 }; 2151 2152 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2153 2154 /* Newer interfaces */ 2155 struct dc_cursor { 2156 struct dc_plane_address address; 2157 struct dc_cursor_attributes attributes; 2158 }; 2159 2160 2161 /* Interrupt interfaces */ 2162 enum dc_irq_source dc_interrupt_to_irq_source( 2163 struct dc *dc, 2164 uint32_t src_id, 2165 uint32_t ext_id); 2166 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2167 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2168 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2169 struct dc *dc, uint32_t link_index); 2170 2171 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2172 2173 /* Power Interfaces */ 2174 2175 void dc_set_power_state( 2176 struct dc *dc, 2177 enum dc_acpi_cm_power_state power_state); 2178 void dc_resume(struct dc *dc); 2179 2180 void dc_power_down_on_boot(struct dc *dc); 2181 2182 /* 2183 * HDCP Interfaces 2184 */ 2185 enum hdcp_message_status dc_process_hdcp_msg( 2186 enum signal_type signal, 2187 struct dc_link *link, 2188 struct hdcp_protection_message *message_info); 2189 bool dc_is_dmcu_initialized(struct dc *dc); 2190 2191 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2192 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2193 2194 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 2195 struct dc_cursor_attributes *cursor_attr); 2196 2197 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 2198 2199 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2200 void dc_unlock_memory_clock_frequency(struct dc *dc); 2201 2202 /* set min memory clock to the min required for current mode, max to maxDPM */ 2203 void dc_lock_memory_clock_frequency(struct dc *dc); 2204 2205 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2206 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2207 2208 /* cleanup on driver unload */ 2209 void dc_hardware_release(struct dc *dc); 2210 2211 /* disables fw based mclk switch */ 2212 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2213 2214 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2215 void dc_z10_restore(const struct dc *dc); 2216 void dc_z10_save_init(struct dc *dc); 2217 2218 bool dc_is_dmub_outbox_supported(struct dc *dc); 2219 bool dc_enable_dmub_notifications(struct dc *dc); 2220 2221 void dc_enable_dmub_outbox(struct dc *dc); 2222 2223 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2224 uint32_t link_index, 2225 struct aux_payload *payload); 2226 2227 /* Get dc link index from dpia port index */ 2228 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2229 uint8_t dpia_port_index); 2230 2231 bool dc_process_dmub_set_config_async(struct dc *dc, 2232 uint32_t link_index, 2233 struct set_config_cmd_payload *payload, 2234 struct dmub_notification *notify); 2235 2236 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2237 uint32_t link_index, 2238 uint8_t mst_alloc_slots, 2239 uint8_t *mst_slots_in_use); 2240 2241 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2242 uint32_t hpd_int_enable); 2243 2244 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2245 2246 /* DSC Interfaces */ 2247 #include "dc_dsc.h" 2248 2249 /* Disable acc mode Interfaces */ 2250 void dc_disable_accelerated_mode(struct dc *dc); 2251 2252 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2253 struct dc_stream_state *new_stream); 2254 2255 #endif /* DC_INTERFACE_H_ */ 2256