1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.167" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 // Sizes defined as multiples of 64KB 79 enum det_size { 80 DET_SIZE_DEFAULT = 0, 81 DET_SIZE_192KB = 3, 82 DET_SIZE_256KB = 4, 83 DET_SIZE_320KB = 5, 84 DET_SIZE_384KB = 6 85 }; 86 87 88 struct dc_plane_cap { 89 enum dc_plane_type type; 90 uint32_t blends_with_above : 1; 91 uint32_t blends_with_below : 1; 92 uint32_t per_pixel_alpha : 1; 93 struct { 94 uint32_t argb8888 : 1; 95 uint32_t nv12 : 1; 96 uint32_t fp16 : 1; 97 uint32_t p010 : 1; 98 uint32_t ayuv : 1; 99 } pixel_format_support; 100 // max upscaling factor x1000 101 // upscaling factors are always >= 1 102 // for example, 1080p -> 8K is 4.0, or 4000 raw value 103 struct { 104 uint32_t argb8888; 105 uint32_t nv12; 106 uint32_t fp16; 107 } max_upscale_factor; 108 // max downscale factor x1000 109 // downscale factors are always <= 1 110 // for example, 8K -> 1080p is 0.25, or 250 raw value 111 struct { 112 uint32_t argb8888; 113 uint32_t nv12; 114 uint32_t fp16; 115 } max_downscale_factor; 116 // minimal width/height 117 uint32_t min_width; 118 uint32_t min_height; 119 }; 120 121 // Color management caps (DPP and MPC) 122 struct rom_curve_caps { 123 uint16_t srgb : 1; 124 uint16_t bt2020 : 1; 125 uint16_t gamma2_2 : 1; 126 uint16_t pq : 1; 127 uint16_t hlg : 1; 128 }; 129 130 struct dpp_color_caps { 131 uint16_t dcn_arch : 1; // all DCE generations treated the same 132 // input lut is different than most LUTs, just plain 256-entry lookup 133 uint16_t input_lut_shared : 1; // shared with DGAM 134 uint16_t icsc : 1; 135 uint16_t dgam_ram : 1; 136 uint16_t post_csc : 1; // before gamut remap 137 uint16_t gamma_corr : 1; 138 139 // hdr_mult and gamut remap always available in DPP (in that order) 140 // 3d lut implies shaper LUT, 141 // it may be shared with MPC - check MPC:shared_3d_lut flag 142 uint16_t hw_3d_lut : 1; 143 uint16_t ogam_ram : 1; // blnd gam 144 uint16_t ocsc : 1; 145 uint16_t dgam_rom_for_yuv : 1; 146 struct rom_curve_caps dgam_rom_caps; 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct mpc_color_caps { 151 uint16_t gamut_remap : 1; 152 uint16_t ogam_ram : 1; 153 uint16_t ocsc : 1; 154 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 155 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 156 157 struct rom_curve_caps ogam_rom_caps; 158 }; 159 160 struct dc_color_caps { 161 struct dpp_color_caps dpp; 162 struct mpc_color_caps mpc; 163 }; 164 165 struct dc_caps { 166 uint32_t max_streams; 167 uint32_t max_links; 168 uint32_t max_audios; 169 uint32_t max_slave_planes; 170 uint32_t max_slave_yuv_planes; 171 uint32_t max_slave_rgb_planes; 172 uint32_t max_planes; 173 uint32_t max_downscale_ratio; 174 uint32_t i2c_speed_in_khz; 175 uint32_t i2c_speed_in_khz_hdcp; 176 uint32_t dmdata_alloc_size; 177 unsigned int max_cursor_size; 178 unsigned int max_video_width; 179 unsigned int min_horizontal_blanking_period; 180 int linear_pitch_alignment; 181 bool dcc_const_color; 182 bool dynamic_audio; 183 bool is_apu; 184 bool dual_link_dvi; 185 bool post_blend_color_processing; 186 bool force_dp_tps4_for_cp2520; 187 bool disable_dp_clk_share; 188 bool psp_setup_panel_mode; 189 bool extended_aux_timeout_support; 190 bool dmcub_support; 191 uint32_t num_of_internal_disp; 192 enum dp_protocol_version max_dp_protocol_version; 193 unsigned int mall_size_per_mem_channel; 194 unsigned int mall_size_total; 195 unsigned int cursor_cache_size; 196 struct dc_plane_cap planes[MAX_PLANES]; 197 struct dc_color_caps color; 198 #if defined(CONFIG_DRM_AMD_DC_DCN) 199 bool dp_hpo; 200 bool hdmi_frl_pcon_support; 201 #endif 202 bool edp_dsc_support; 203 bool vbios_lttpr_aware; 204 bool vbios_lttpr_enable; 205 uint32_t max_otg_num; 206 }; 207 208 struct dc_bug_wa { 209 bool no_connect_phy_config; 210 bool dedcn20_305_wa; 211 bool skip_clock_update; 212 bool lt_early_cr_pattern; 213 }; 214 215 struct dc_dcc_surface_param { 216 struct dc_size surface_size; 217 enum surface_pixel_format format; 218 enum swizzle_mode_values swizzle_mode; 219 enum dc_scan_direction scan; 220 }; 221 222 struct dc_dcc_setting { 223 unsigned int max_compressed_blk_size; 224 unsigned int max_uncompressed_blk_size; 225 bool independent_64b_blks; 226 #if defined(CONFIG_DRM_AMD_DC_DCN) 227 //These bitfields to be used starting with DCN 228 struct { 229 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 230 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 231 uint32_t dcc_256_128_128 : 1; //available starting with DCN 232 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 233 } dcc_controls; 234 #endif 235 }; 236 237 struct dc_surface_dcc_cap { 238 union { 239 struct { 240 struct dc_dcc_setting rgb; 241 } grph; 242 243 struct { 244 struct dc_dcc_setting luma; 245 struct dc_dcc_setting chroma; 246 } video; 247 }; 248 249 bool capable; 250 bool const_color_support; 251 }; 252 253 struct dc_static_screen_params { 254 struct { 255 bool force_trigger; 256 bool cursor_update; 257 bool surface_update; 258 bool overlay_update; 259 } triggers; 260 unsigned int num_frames; 261 }; 262 263 264 /* Surface update type is used by dc_update_surfaces_and_stream 265 * The update type is determined at the very beginning of the function based 266 * on parameters passed in and decides how much programming (or updating) is 267 * going to be done during the call. 268 * 269 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 270 * logical calculations or hardware register programming. This update MUST be 271 * ISR safe on windows. Currently fast update will only be used to flip surface 272 * address. 273 * 274 * UPDATE_TYPE_MED is used for slower updates which require significant hw 275 * re-programming however do not affect bandwidth consumption or clock 276 * requirements. At present, this is the level at which front end updates 277 * that do not require us to run bw_calcs happen. These are in/out transfer func 278 * updates, viewport offset changes, recout size changes and pixel depth changes. 279 * This update can be done at ISR, but we want to minimize how often this happens. 280 * 281 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 282 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 283 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 284 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 285 * a full update. This cannot be done at ISR level and should be a rare event. 286 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 287 * underscan we don't expect to see this call at all. 288 */ 289 290 enum surface_update_type { 291 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 292 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 293 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 294 }; 295 296 /* Forward declaration*/ 297 struct dc; 298 struct dc_plane_state; 299 struct dc_state; 300 301 302 struct dc_cap_funcs { 303 bool (*get_dcc_compression_cap)(const struct dc *dc, 304 const struct dc_dcc_surface_param *input, 305 struct dc_surface_dcc_cap *output); 306 }; 307 308 struct link_training_settings; 309 310 #if defined(CONFIG_DRM_AMD_DC_DCN) 311 union allow_lttpr_non_transparent_mode { 312 struct { 313 bool DP1_4A : 1; 314 bool DP2_0 : 1; 315 } bits; 316 unsigned char raw; 317 }; 318 #endif 319 /* Structure to hold configuration flags set by dm at dc creation. */ 320 struct dc_config { 321 bool gpu_vm_support; 322 bool disable_disp_pll_sharing; 323 bool fbc_support; 324 bool disable_fractional_pwm; 325 bool allow_seamless_boot_optimization; 326 bool power_down_display_on_boot; 327 bool edp_not_connected; 328 bool edp_no_power_sequencing; 329 bool force_enum_edp; 330 bool forced_clocks; 331 #if defined(CONFIG_DRM_AMD_DC_DCN) 332 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 333 #else 334 bool allow_lttpr_non_transparent_mode; 335 #endif 336 bool multi_mon_pp_mclk_switch; 337 bool disable_dmcu; 338 bool enable_4to1MPC; 339 bool enable_windowed_mpo_odm; 340 bool allow_edp_hotplug_detection; 341 #if defined(CONFIG_DRM_AMD_DC_DCN) 342 bool clamp_min_dcfclk; 343 #endif 344 uint64_t vblank_alignment_dto_params; 345 uint8_t vblank_alignment_max_frame_time_diff; 346 bool is_asymmetric_memory; 347 bool is_single_rank_dimm; 348 bool use_pipe_ctx_sync_logic; 349 }; 350 351 enum visual_confirm { 352 VISUAL_CONFIRM_DISABLE = 0, 353 VISUAL_CONFIRM_SURFACE = 1, 354 VISUAL_CONFIRM_HDR = 2, 355 VISUAL_CONFIRM_MPCTREE = 4, 356 VISUAL_CONFIRM_PSR = 5, 357 VISUAL_CONFIRM_SWIZZLE = 9, 358 }; 359 360 enum dc_psr_power_opts { 361 psr_power_opt_invalid = 0x0, 362 psr_power_opt_smu_opt_static_screen = 0x1, 363 psr_power_opt_z10_static_screen = 0x10, 364 }; 365 366 enum dcc_option { 367 DCC_ENABLE = 0, 368 DCC_DISABLE = 1, 369 DCC_HALF_REQ_DISALBE = 2, 370 }; 371 372 enum pipe_split_policy { 373 MPC_SPLIT_DYNAMIC = 0, 374 MPC_SPLIT_AVOID = 1, 375 MPC_SPLIT_AVOID_MULT_DISP = 2, 376 }; 377 378 enum wm_report_mode { 379 WM_REPORT_DEFAULT = 0, 380 WM_REPORT_OVERRIDE = 1, 381 }; 382 enum dtm_pstate{ 383 dtm_level_p0 = 0,/*highest voltage*/ 384 dtm_level_p1, 385 dtm_level_p2, 386 dtm_level_p3, 387 dtm_level_p4,/*when active_display_count = 0*/ 388 }; 389 390 enum dcn_pwr_state { 391 DCN_PWR_STATE_UNKNOWN = -1, 392 DCN_PWR_STATE_MISSION_MODE = 0, 393 DCN_PWR_STATE_LOW_POWER = 3, 394 }; 395 396 #if defined(CONFIG_DRM_AMD_DC_DCN) 397 enum dcn_zstate_support_state { 398 DCN_ZSTATE_SUPPORT_UNKNOWN, 399 DCN_ZSTATE_SUPPORT_ALLOW, 400 DCN_ZSTATE_SUPPORT_DISALLOW, 401 }; 402 #endif 403 /* 404 * For any clocks that may differ per pipe 405 * only the max is stored in this structure 406 */ 407 struct dc_clocks { 408 int dispclk_khz; 409 int actual_dispclk_khz; 410 int dppclk_khz; 411 int actual_dppclk_khz; 412 int disp_dpp_voltage_level_khz; 413 int dcfclk_khz; 414 int socclk_khz; 415 int dcfclk_deep_sleep_khz; 416 int fclk_khz; 417 int phyclk_khz; 418 int dramclk_khz; 419 bool p_state_change_support; 420 #if defined(CONFIG_DRM_AMD_DC_DCN) 421 enum dcn_zstate_support_state zstate_support; 422 bool dtbclk_en; 423 #endif 424 enum dcn_pwr_state pwr_state; 425 /* 426 * Elements below are not compared for the purposes of 427 * optimization required 428 */ 429 bool prev_p_state_change_support; 430 enum dtm_pstate dtm_level; 431 int max_supported_dppclk_khz; 432 int max_supported_dispclk_khz; 433 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 434 int bw_dispclk_khz; 435 }; 436 437 struct dc_bw_validation_profile { 438 bool enable; 439 440 unsigned long long total_ticks; 441 unsigned long long voltage_level_ticks; 442 unsigned long long watermark_ticks; 443 unsigned long long rq_dlg_ticks; 444 445 unsigned long long total_count; 446 unsigned long long skip_fast_count; 447 unsigned long long skip_pass_count; 448 unsigned long long skip_fail_count; 449 }; 450 451 #define BW_VAL_TRACE_SETUP() \ 452 unsigned long long end_tick = 0; \ 453 unsigned long long voltage_level_tick = 0; \ 454 unsigned long long watermark_tick = 0; \ 455 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 456 dm_get_timestamp(dc->ctx) : 0 457 458 #define BW_VAL_TRACE_COUNT() \ 459 if (dc->debug.bw_val_profile.enable) \ 460 dc->debug.bw_val_profile.total_count++ 461 462 #define BW_VAL_TRACE_SKIP(status) \ 463 if (dc->debug.bw_val_profile.enable) { \ 464 if (!voltage_level_tick) \ 465 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 466 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 467 } 468 469 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 470 if (dc->debug.bw_val_profile.enable) \ 471 voltage_level_tick = dm_get_timestamp(dc->ctx) 472 473 #define BW_VAL_TRACE_END_WATERMARKS() \ 474 if (dc->debug.bw_val_profile.enable) \ 475 watermark_tick = dm_get_timestamp(dc->ctx) 476 477 #define BW_VAL_TRACE_FINISH() \ 478 if (dc->debug.bw_val_profile.enable) { \ 479 end_tick = dm_get_timestamp(dc->ctx); \ 480 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 481 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 482 if (watermark_tick) { \ 483 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 484 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 485 } \ 486 } 487 488 union mem_low_power_enable_options { 489 struct { 490 bool vga: 1; 491 bool i2c: 1; 492 bool dmcu: 1; 493 bool dscl: 1; 494 bool cm: 1; 495 bool mpc: 1; 496 bool optc: 1; 497 bool vpg: 1; 498 bool afmt: 1; 499 } bits; 500 uint32_t u32All; 501 }; 502 503 union root_clock_optimization_options { 504 struct { 505 bool dpp: 1; 506 bool dsc: 1; 507 bool hdmistream: 1; 508 bool hdmichar: 1; 509 bool dpstream: 1; 510 bool symclk32_se: 1; 511 bool symclk32_le: 1; 512 bool symclk_fe: 1; 513 bool physymclk: 1; 514 bool dpiasymclk: 1; 515 uint32_t reserved: 22; 516 } bits; 517 uint32_t u32All; 518 }; 519 520 union dpia_debug_options { 521 struct { 522 uint32_t disable_dpia:1; 523 uint32_t force_non_lttpr:1; 524 uint32_t extend_aux_rd_interval:1; 525 uint32_t disable_mst_dsc_work_around:1; 526 uint32_t hpd_delay_in_ms:12; 527 uint32_t reserved:16; 528 } bits; 529 uint32_t raw; 530 }; 531 532 struct dc_debug_data { 533 uint32_t ltFailCount; 534 uint32_t i2cErrorCount; 535 uint32_t auxErrorCount; 536 }; 537 538 struct dc_phy_addr_space_config { 539 struct { 540 uint64_t start_addr; 541 uint64_t end_addr; 542 uint64_t fb_top; 543 uint64_t fb_offset; 544 uint64_t fb_base; 545 uint64_t agp_top; 546 uint64_t agp_bot; 547 uint64_t agp_base; 548 } system_aperture; 549 550 struct { 551 uint64_t page_table_start_addr; 552 uint64_t page_table_end_addr; 553 uint64_t page_table_base_addr; 554 bool base_addr_is_mc_addr; 555 } gart_config; 556 557 bool valid; 558 bool is_hvm_enabled; 559 uint64_t page_table_default_page_addr; 560 }; 561 562 struct dc_virtual_addr_space_config { 563 uint64_t page_table_base_addr; 564 uint64_t page_table_start_addr; 565 uint64_t page_table_end_addr; 566 uint32_t page_table_block_size_in_bytes; 567 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 568 }; 569 570 struct dc_bounding_box_overrides { 571 int sr_exit_time_ns; 572 int sr_enter_plus_exit_time_ns; 573 int urgent_latency_ns; 574 int percent_of_ideal_drambw; 575 int dram_clock_change_latency_ns; 576 int dummy_clock_change_latency_ns; 577 /* This forces a hard min on the DCFCLK we use 578 * for DML. Unlike the debug option for forcing 579 * DCFCLK, this override affects watermark calculations 580 */ 581 int min_dcfclk_mhz; 582 }; 583 584 struct dc_state; 585 struct resource_pool; 586 struct dce_hwseq; 587 588 struct dc_debug_options { 589 bool native422_support; 590 bool disable_dsc; 591 enum visual_confirm visual_confirm; 592 int visual_confirm_rect_height; 593 594 bool sanity_checks; 595 bool max_disp_clk; 596 bool surface_trace; 597 bool timing_trace; 598 bool clock_trace; 599 bool validation_trace; 600 bool bandwidth_calcs_trace; 601 int max_downscale_src_width; 602 603 /* stutter efficiency related */ 604 bool disable_stutter; 605 bool use_max_lb; 606 enum dcc_option disable_dcc; 607 enum pipe_split_policy pipe_split_policy; 608 bool force_single_disp_pipe_split; 609 bool voltage_align_fclk; 610 bool disable_min_fclk; 611 612 bool disable_dfs_bypass; 613 bool disable_dpp_power_gate; 614 bool disable_hubp_power_gate; 615 bool disable_dsc_power_gate; 616 int dsc_min_slice_height_override; 617 int dsc_bpp_increment_div; 618 bool disable_pplib_wm_range; 619 enum wm_report_mode pplib_wm_report_mode; 620 unsigned int min_disp_clk_khz; 621 unsigned int min_dpp_clk_khz; 622 unsigned int min_dram_clk_khz; 623 int sr_exit_time_dpm0_ns; 624 int sr_enter_plus_exit_time_dpm0_ns; 625 int sr_exit_time_ns; 626 int sr_enter_plus_exit_time_ns; 627 int urgent_latency_ns; 628 uint32_t underflow_assert_delay_us; 629 int percent_of_ideal_drambw; 630 int dram_clock_change_latency_ns; 631 bool optimized_watermark; 632 int always_scale; 633 bool disable_pplib_clock_request; 634 bool disable_clock_gate; 635 bool disable_mem_low_power; 636 #if defined(CONFIG_DRM_AMD_DC_DCN) 637 bool pstate_enabled; 638 #endif 639 bool disable_dmcu; 640 bool disable_psr; 641 bool force_abm_enable; 642 bool disable_stereo_support; 643 bool vsr_support; 644 bool performance_trace; 645 bool az_endpoint_mute_only; 646 bool always_use_regamma; 647 bool recovery_enabled; 648 bool avoid_vbios_exec_table; 649 bool scl_reset_length10; 650 bool hdmi20_disable; 651 bool skip_detection_link_training; 652 uint32_t edid_read_retry_times; 653 bool remove_disconnect_edp; 654 unsigned int force_odm_combine; //bit vector based on otg inst 655 #if defined(CONFIG_DRM_AMD_DC_DCN) 656 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 657 bool disable_z9_mpc; 658 #endif 659 unsigned int force_fclk_khz; 660 bool enable_tri_buf; 661 bool dmub_offload_enabled; 662 bool dmcub_emulation; 663 #if defined(CONFIG_DRM_AMD_DC_DCN) 664 bool disable_idle_power_optimizations; 665 unsigned int mall_size_override; 666 unsigned int mall_additional_timer_percent; 667 bool mall_error_as_fatal; 668 #endif 669 bool dmub_command_table; /* for testing only */ 670 struct dc_bw_validation_profile bw_val_profile; 671 bool disable_fec; 672 bool disable_48mhz_pwrdwn; 673 /* This forces a hard min on the DCFCLK requested to SMU/PP 674 * watermarks are not affected. 675 */ 676 unsigned int force_min_dcfclk_mhz; 677 #if defined(CONFIG_DRM_AMD_DC_DCN) 678 int dwb_fi_phase; 679 #endif 680 bool disable_timing_sync; 681 bool cm_in_bypass; 682 int force_clock_mode;/*every mode change.*/ 683 684 bool disable_dram_clock_change_vactive_support; 685 bool validate_dml_output; 686 bool enable_dmcub_surface_flip; 687 bool usbc_combo_phy_reset_wa; 688 bool disable_dsc_edp; 689 unsigned int force_dsc_edp_policy; 690 bool enable_dram_clock_change_one_display_vactive; 691 #if defined(CONFIG_DRM_AMD_DC_DCN) 692 /* TODO - remove once tested */ 693 bool legacy_dp2_lt; 694 bool set_mst_en_for_sst; 695 bool disable_uhbr; 696 bool force_dp2_lt_fallback_method; 697 #endif 698 union mem_low_power_enable_options enable_mem_low_power; 699 union root_clock_optimization_options root_clock_optimization; 700 bool hpo_optimization; 701 bool force_vblank_alignment; 702 703 /* Enable dmub aux for legacy ddc */ 704 bool enable_dmub_aux_for_legacy_ddc; 705 bool optimize_edp_link_rate; /* eDP ILR */ 706 /* FEC/PSR1 sequence enable delay in 100us */ 707 uint8_t fec_enable_delay_in100us; 708 bool enable_driver_sequence_debug; 709 enum det_size crb_alloc_policy; 710 int crb_alloc_policy_min_disp_count; 711 #if defined(CONFIG_DRM_AMD_DC_DCN) 712 bool disable_z10; 713 bool enable_sw_cntl_psr; 714 union dpia_debug_options dpia_debug; 715 #endif 716 bool apply_vendor_specific_lttpr_wa; 717 }; 718 719 struct gpu_info_soc_bounding_box_v1_0; 720 struct dc { 721 struct dc_debug_options debug; 722 struct dc_versions versions; 723 struct dc_caps caps; 724 struct dc_cap_funcs cap_funcs; 725 struct dc_config config; 726 struct dc_bounding_box_overrides bb_overrides; 727 struct dc_bug_wa work_arounds; 728 struct dc_context *ctx; 729 struct dc_phy_addr_space_config vm_pa_config; 730 731 uint8_t link_count; 732 struct dc_link *links[MAX_PIPES * 2]; 733 734 struct dc_state *current_state; 735 struct resource_pool *res_pool; 736 737 struct clk_mgr *clk_mgr; 738 739 /* Display Engine Clock levels */ 740 struct dm_pp_clock_levels sclk_lvls; 741 742 /* Inputs into BW and WM calculations. */ 743 struct bw_calcs_dceip *bw_dceip; 744 struct bw_calcs_vbios *bw_vbios; 745 #ifdef CONFIG_DRM_AMD_DC_DCN 746 struct dcn_soc_bounding_box *dcn_soc; 747 struct dcn_ip_params *dcn_ip; 748 struct display_mode_lib dml; 749 #endif 750 751 /* HW functions */ 752 struct hw_sequencer_funcs hwss; 753 struct dce_hwseq *hwseq; 754 755 /* Require to optimize clocks and bandwidth for added/removed planes */ 756 bool optimized_required; 757 bool wm_optimized_required; 758 #if defined(CONFIG_DRM_AMD_DC_DCN) 759 bool idle_optimizations_allowed; 760 #endif 761 #if defined(CONFIG_DRM_AMD_DC_DCN) 762 bool enable_c20_dtm_b0; 763 #endif 764 765 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 766 767 /* FBC compressor */ 768 struct compressor *fbc_compressor; 769 770 struct dc_debug_data debug_data; 771 struct dpcd_vendor_signature vendor_signature; 772 773 const char *build_id; 774 struct vm_helper *vm_helper; 775 }; 776 777 enum frame_buffer_mode { 778 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 779 FRAME_BUFFER_MODE_ZFB_ONLY, 780 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 781 } ; 782 783 struct dchub_init_data { 784 int64_t zfb_phys_addr_base; 785 int64_t zfb_mc_base_addr; 786 uint64_t zfb_size_in_byte; 787 enum frame_buffer_mode fb_mode; 788 bool dchub_initialzied; 789 bool dchub_info_valid; 790 }; 791 792 struct dc_init_data { 793 struct hw_asic_id asic_id; 794 void *driver; /* ctx */ 795 struct cgs_device *cgs_device; 796 struct dc_bounding_box_overrides bb_overrides; 797 798 int num_virtual_links; 799 /* 800 * If 'vbios_override' not NULL, it will be called instead 801 * of the real VBIOS. Intended use is Diagnostics on FPGA. 802 */ 803 struct dc_bios *vbios_override; 804 enum dce_environment dce_environment; 805 806 struct dmub_offload_funcs *dmub_if; 807 struct dc_reg_helper_state *dmub_offload; 808 809 struct dc_config flags; 810 uint64_t log_mask; 811 812 struct dpcd_vendor_signature vendor_signature; 813 #if defined(CONFIG_DRM_AMD_DC_DCN) 814 bool force_smu_not_present; 815 #endif 816 }; 817 818 struct dc_callback_init { 819 #ifdef CONFIG_DRM_AMD_DC_HDCP 820 struct cp_psp cp_psp; 821 #else 822 uint8_t reserved; 823 #endif 824 }; 825 826 struct dc *dc_create(const struct dc_init_data *init_params); 827 void dc_hardware_init(struct dc *dc); 828 829 int dc_get_vmid_use_vector(struct dc *dc); 830 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 831 /* Returns the number of vmids supported */ 832 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 833 void dc_init_callbacks(struct dc *dc, 834 const struct dc_callback_init *init_params); 835 void dc_deinit_callbacks(struct dc *dc); 836 void dc_destroy(struct dc **dc); 837 838 /******************************************************************************* 839 * Surface Interfaces 840 ******************************************************************************/ 841 842 enum { 843 TRANSFER_FUNC_POINTS = 1025 844 }; 845 846 struct dc_hdr_static_metadata { 847 /* display chromaticities and white point in units of 0.00001 */ 848 unsigned int chromaticity_green_x; 849 unsigned int chromaticity_green_y; 850 unsigned int chromaticity_blue_x; 851 unsigned int chromaticity_blue_y; 852 unsigned int chromaticity_red_x; 853 unsigned int chromaticity_red_y; 854 unsigned int chromaticity_white_point_x; 855 unsigned int chromaticity_white_point_y; 856 857 uint32_t min_luminance; 858 uint32_t max_luminance; 859 uint32_t maximum_content_light_level; 860 uint32_t maximum_frame_average_light_level; 861 }; 862 863 enum dc_transfer_func_type { 864 TF_TYPE_PREDEFINED, 865 TF_TYPE_DISTRIBUTED_POINTS, 866 TF_TYPE_BYPASS, 867 TF_TYPE_HWPWL 868 }; 869 870 struct dc_transfer_func_distributed_points { 871 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 872 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 873 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 874 875 uint16_t end_exponent; 876 uint16_t x_point_at_y1_red; 877 uint16_t x_point_at_y1_green; 878 uint16_t x_point_at_y1_blue; 879 }; 880 881 enum dc_transfer_func_predefined { 882 TRANSFER_FUNCTION_SRGB, 883 TRANSFER_FUNCTION_BT709, 884 TRANSFER_FUNCTION_PQ, 885 TRANSFER_FUNCTION_LINEAR, 886 TRANSFER_FUNCTION_UNITY, 887 TRANSFER_FUNCTION_HLG, 888 TRANSFER_FUNCTION_HLG12, 889 TRANSFER_FUNCTION_GAMMA22, 890 TRANSFER_FUNCTION_GAMMA24, 891 TRANSFER_FUNCTION_GAMMA26 892 }; 893 894 895 struct dc_transfer_func { 896 struct kref refcount; 897 enum dc_transfer_func_type type; 898 enum dc_transfer_func_predefined tf; 899 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 900 uint32_t sdr_ref_white_level; 901 union { 902 struct pwl_params pwl; 903 struct dc_transfer_func_distributed_points tf_pts; 904 }; 905 }; 906 907 908 union dc_3dlut_state { 909 struct { 910 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 911 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 912 uint32_t rmu_mux_num:3; /*index of mux to use*/ 913 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 914 uint32_t mpc_rmu1_mux:4; 915 uint32_t mpc_rmu2_mux:4; 916 uint32_t reserved:15; 917 } bits; 918 uint32_t raw; 919 }; 920 921 922 struct dc_3dlut { 923 struct kref refcount; 924 struct tetrahedral_params lut_3d; 925 struct fixed31_32 hdr_multiplier; 926 union dc_3dlut_state state; 927 }; 928 /* 929 * This structure is filled in by dc_surface_get_status and contains 930 * the last requested address and the currently active address so the called 931 * can determine if there are any outstanding flips 932 */ 933 struct dc_plane_status { 934 struct dc_plane_address requested_address; 935 struct dc_plane_address current_address; 936 bool is_flip_pending; 937 bool is_right_eye; 938 }; 939 940 union surface_update_flags { 941 942 struct { 943 uint32_t addr_update:1; 944 /* Medium updates */ 945 uint32_t dcc_change:1; 946 uint32_t color_space_change:1; 947 uint32_t horizontal_mirror_change:1; 948 uint32_t per_pixel_alpha_change:1; 949 uint32_t global_alpha_change:1; 950 uint32_t hdr_mult:1; 951 uint32_t rotation_change:1; 952 uint32_t swizzle_change:1; 953 uint32_t scaling_change:1; 954 uint32_t position_change:1; 955 uint32_t in_transfer_func_change:1; 956 uint32_t input_csc_change:1; 957 uint32_t coeff_reduction_change:1; 958 uint32_t output_tf_change:1; 959 uint32_t pixel_format_change:1; 960 uint32_t plane_size_change:1; 961 uint32_t gamut_remap_change:1; 962 963 /* Full updates */ 964 uint32_t new_plane:1; 965 uint32_t bpp_change:1; 966 uint32_t gamma_change:1; 967 uint32_t bandwidth_change:1; 968 uint32_t clock_change:1; 969 uint32_t stereo_format_change:1; 970 uint32_t lut_3d:1; 971 uint32_t full_update:1; 972 } bits; 973 974 uint32_t raw; 975 }; 976 977 struct dc_plane_state { 978 struct dc_plane_address address; 979 struct dc_plane_flip_time time; 980 bool triplebuffer_flips; 981 struct scaling_taps scaling_quality; 982 struct rect src_rect; 983 struct rect dst_rect; 984 struct rect clip_rect; 985 986 struct plane_size plane_size; 987 union dc_tiling_info tiling_info; 988 989 struct dc_plane_dcc_param dcc; 990 991 struct dc_gamma *gamma_correction; 992 struct dc_transfer_func *in_transfer_func; 993 struct dc_bias_and_scale *bias_and_scale; 994 struct dc_csc_transform input_csc_color_matrix; 995 struct fixed31_32 coeff_reduction_factor; 996 struct fixed31_32 hdr_mult; 997 struct colorspace_transform gamut_remap_matrix; 998 999 // TODO: No longer used, remove 1000 struct dc_hdr_static_metadata hdr_static_ctx; 1001 1002 enum dc_color_space color_space; 1003 1004 struct dc_3dlut *lut3d_func; 1005 struct dc_transfer_func *in_shaper_func; 1006 struct dc_transfer_func *blend_tf; 1007 1008 #if defined(CONFIG_DRM_AMD_DC_DCN) 1009 struct dc_transfer_func *gamcor_tf; 1010 #endif 1011 enum surface_pixel_format format; 1012 enum dc_rotation_angle rotation; 1013 enum plane_stereo_format stereo_format; 1014 1015 bool is_tiling_rotated; 1016 bool per_pixel_alpha; 1017 bool global_alpha; 1018 int global_alpha_value; 1019 bool visible; 1020 bool flip_immediate; 1021 bool horizontal_mirror; 1022 int layer_index; 1023 1024 union surface_update_flags update_flags; 1025 bool flip_int_enabled; 1026 bool skip_manual_trigger; 1027 1028 /* private to DC core */ 1029 struct dc_plane_status status; 1030 struct dc_context *ctx; 1031 1032 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1033 bool force_full_update; 1034 1035 /* private to dc_surface.c */ 1036 enum dc_irq_source irq_source; 1037 struct kref refcount; 1038 }; 1039 1040 struct dc_plane_info { 1041 struct plane_size plane_size; 1042 union dc_tiling_info tiling_info; 1043 struct dc_plane_dcc_param dcc; 1044 enum surface_pixel_format format; 1045 enum dc_rotation_angle rotation; 1046 enum plane_stereo_format stereo_format; 1047 enum dc_color_space color_space; 1048 bool horizontal_mirror; 1049 bool visible; 1050 bool per_pixel_alpha; 1051 bool global_alpha; 1052 int global_alpha_value; 1053 bool input_csc_enabled; 1054 int layer_index; 1055 }; 1056 1057 struct dc_scaling_info { 1058 struct rect src_rect; 1059 struct rect dst_rect; 1060 struct rect clip_rect; 1061 struct scaling_taps scaling_quality; 1062 }; 1063 1064 struct dc_surface_update { 1065 struct dc_plane_state *surface; 1066 1067 /* isr safe update parameters. null means no updates */ 1068 const struct dc_flip_addrs *flip_addr; 1069 const struct dc_plane_info *plane_info; 1070 const struct dc_scaling_info *scaling_info; 1071 struct fixed31_32 hdr_mult; 1072 /* following updates require alloc/sleep/spin that is not isr safe, 1073 * null means no updates 1074 */ 1075 const struct dc_gamma *gamma; 1076 const struct dc_transfer_func *in_transfer_func; 1077 1078 const struct dc_csc_transform *input_csc_color_matrix; 1079 const struct fixed31_32 *coeff_reduction_factor; 1080 const struct dc_transfer_func *func_shaper; 1081 const struct dc_3dlut *lut3d_func; 1082 const struct dc_transfer_func *blend_tf; 1083 const struct colorspace_transform *gamut_remap_matrix; 1084 }; 1085 1086 /* 1087 * Create a new surface with default parameters; 1088 */ 1089 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1090 const struct dc_plane_status *dc_plane_get_status( 1091 const struct dc_plane_state *plane_state); 1092 1093 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1094 void dc_plane_state_release(struct dc_plane_state *plane_state); 1095 1096 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1097 void dc_gamma_release(struct dc_gamma **dc_gamma); 1098 struct dc_gamma *dc_create_gamma(void); 1099 1100 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1101 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1102 struct dc_transfer_func *dc_create_transfer_func(void); 1103 1104 struct dc_3dlut *dc_create_3dlut_func(void); 1105 void dc_3dlut_func_release(struct dc_3dlut *lut); 1106 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1107 /* 1108 * This structure holds a surface address. There could be multiple addresses 1109 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1110 * as frame durations and DCC format can also be set. 1111 */ 1112 struct dc_flip_addrs { 1113 struct dc_plane_address address; 1114 unsigned int flip_timestamp_in_us; 1115 bool flip_immediate; 1116 /* TODO: add flip duration for FreeSync */ 1117 bool triplebuffer_flips; 1118 }; 1119 1120 void dc_post_update_surfaces_to_stream( 1121 struct dc *dc); 1122 1123 #include "dc_stream.h" 1124 1125 /* 1126 * Structure to store surface/stream associations for validation 1127 */ 1128 struct dc_validation_set { 1129 struct dc_stream_state *stream; 1130 struct dc_plane_state *plane_states[MAX_SURFACES]; 1131 uint8_t plane_count; 1132 }; 1133 1134 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1135 const struct dc_sink *sink, 1136 struct dc_crtc_timing *crtc_timing); 1137 1138 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1139 1140 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1141 1142 bool dc_set_generic_gpio_for_stereo(bool enable, 1143 struct gpio_service *gpio_service); 1144 1145 /* 1146 * fast_validate: we return after determining if we can support the new state, 1147 * but before we populate the programming info 1148 */ 1149 enum dc_status dc_validate_global_state( 1150 struct dc *dc, 1151 struct dc_state *new_ctx, 1152 bool fast_validate); 1153 1154 1155 void dc_resource_state_construct( 1156 const struct dc *dc, 1157 struct dc_state *dst_ctx); 1158 1159 #if defined(CONFIG_DRM_AMD_DC_DCN) 1160 bool dc_acquire_release_mpc_3dlut( 1161 struct dc *dc, bool acquire, 1162 struct dc_stream_state *stream, 1163 struct dc_3dlut **lut, 1164 struct dc_transfer_func **shaper); 1165 #endif 1166 1167 void dc_resource_state_copy_construct( 1168 const struct dc_state *src_ctx, 1169 struct dc_state *dst_ctx); 1170 1171 void dc_resource_state_copy_construct_current( 1172 const struct dc *dc, 1173 struct dc_state *dst_ctx); 1174 1175 void dc_resource_state_destruct(struct dc_state *context); 1176 1177 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1178 1179 /* 1180 * TODO update to make it about validation sets 1181 * Set up streams and links associated to drive sinks 1182 * The streams parameter is an absolute set of all active streams. 1183 * 1184 * After this call: 1185 * Phy, Encoder, Timing Generator are programmed and enabled. 1186 * New streams are enabled with blank stream; no memory read. 1187 */ 1188 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1189 1190 struct dc_state *dc_create_state(struct dc *dc); 1191 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1192 void dc_retain_state(struct dc_state *context); 1193 void dc_release_state(struct dc_state *context); 1194 1195 /******************************************************************************* 1196 * Link Interfaces 1197 ******************************************************************************/ 1198 1199 struct dpcd_caps { 1200 union dpcd_rev dpcd_rev; 1201 union max_lane_count max_ln_count; 1202 union max_down_spread max_down_spread; 1203 union dprx_feature dprx_feature; 1204 1205 /* valid only for eDP v1.4 or higher*/ 1206 uint8_t edp_supported_link_rates_count; 1207 enum dc_link_rate edp_supported_link_rates[8]; 1208 1209 /* dongle type (DP converter, CV smart dongle) */ 1210 enum display_dongle_type dongle_type; 1211 /* branch device or sink device */ 1212 bool is_branch_dev; 1213 /* Dongle's downstream count. */ 1214 union sink_count sink_count; 1215 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1216 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1217 struct dc_dongle_caps dongle_caps; 1218 1219 uint32_t sink_dev_id; 1220 int8_t sink_dev_id_str[6]; 1221 int8_t sink_hw_revision; 1222 int8_t sink_fw_revision[2]; 1223 1224 uint32_t branch_dev_id; 1225 int8_t branch_dev_name[6]; 1226 int8_t branch_hw_revision; 1227 int8_t branch_fw_revision[2]; 1228 1229 bool allow_invalid_MSA_timing_param; 1230 bool panel_mode_edp; 1231 bool dpcd_display_control_capable; 1232 bool ext_receiver_cap_field_present; 1233 bool dynamic_backlight_capable_edp; 1234 union dpcd_fec_capability fec_cap; 1235 struct dpcd_dsc_capabilities dsc_caps; 1236 struct dc_lttpr_caps lttpr_caps; 1237 struct psr_caps psr_caps; 1238 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1239 1240 #if defined(CONFIG_DRM_AMD_DC_DCN) 1241 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1242 union dp_main_line_channel_coding_cap channel_coding_cap; 1243 union dp_sink_video_fallback_formats fallback_formats; 1244 union dp_fec_capability1 fec_cap1; 1245 #endif 1246 }; 1247 1248 union dpcd_sink_ext_caps { 1249 struct { 1250 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1251 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1252 */ 1253 uint8_t sdr_aux_backlight_control : 1; 1254 uint8_t hdr_aux_backlight_control : 1; 1255 uint8_t reserved_1 : 2; 1256 uint8_t oled : 1; 1257 uint8_t reserved : 3; 1258 } bits; 1259 uint8_t raw; 1260 }; 1261 1262 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1263 union hdcp_rx_caps { 1264 struct { 1265 uint8_t version; 1266 uint8_t reserved; 1267 struct { 1268 uint8_t repeater : 1; 1269 uint8_t hdcp_capable : 1; 1270 uint8_t reserved : 6; 1271 } byte0; 1272 } fields; 1273 uint8_t raw[3]; 1274 }; 1275 1276 union hdcp_bcaps { 1277 struct { 1278 uint8_t HDCP_CAPABLE:1; 1279 uint8_t REPEATER:1; 1280 uint8_t RESERVED:6; 1281 } bits; 1282 uint8_t raw; 1283 }; 1284 1285 struct hdcp_caps { 1286 union hdcp_rx_caps rx_caps; 1287 union hdcp_bcaps bcaps; 1288 }; 1289 #endif 1290 1291 #include "dc_link.h" 1292 1293 #if defined(CONFIG_DRM_AMD_DC_DCN) 1294 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1295 1296 #endif 1297 /******************************************************************************* 1298 * Sink Interfaces - A sink corresponds to a display output device 1299 ******************************************************************************/ 1300 1301 struct dc_container_id { 1302 // 128bit GUID in binary form 1303 unsigned char guid[16]; 1304 // 8 byte port ID -> ELD.PortID 1305 unsigned int portId[2]; 1306 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1307 unsigned short manufacturerName; 1308 // 2 byte product code -> ELD.ProductCode 1309 unsigned short productCode; 1310 }; 1311 1312 1313 struct dc_sink_dsc_caps { 1314 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1315 // 'false' if they are sink's DSC caps 1316 bool is_virtual_dpcd_dsc; 1317 #if defined(CONFIG_DRM_AMD_DC_DCN) 1318 // 'true' if MST topology supports DSC passthrough for sink 1319 // 'false' if MST topology does not support DSC passthrough 1320 bool is_dsc_passthrough_supported; 1321 #endif 1322 struct dsc_dec_dpcd_caps dsc_dec_caps; 1323 }; 1324 1325 struct dc_sink_fec_caps { 1326 bool is_rx_fec_supported; 1327 bool is_topology_fec_supported; 1328 }; 1329 1330 /* 1331 * The sink structure contains EDID and other display device properties 1332 */ 1333 struct dc_sink { 1334 enum signal_type sink_signal; 1335 struct dc_edid dc_edid; /* raw edid */ 1336 struct dc_edid_caps edid_caps; /* parse display caps */ 1337 struct dc_container_id *dc_container_id; 1338 uint32_t dongle_max_pix_clk; 1339 void *priv; 1340 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1341 bool converter_disable_audio; 1342 1343 struct dc_sink_dsc_caps dsc_caps; 1344 struct dc_sink_fec_caps fec_caps; 1345 1346 bool is_vsc_sdp_colorimetry_supported; 1347 1348 /* private to DC core */ 1349 struct dc_link *link; 1350 struct dc_context *ctx; 1351 1352 uint32_t sink_id; 1353 1354 /* private to dc_sink.c */ 1355 // refcount must be the last member in dc_sink, since we want the 1356 // sink structure to be logically cloneable up to (but not including) 1357 // refcount 1358 struct kref refcount; 1359 }; 1360 1361 void dc_sink_retain(struct dc_sink *sink); 1362 void dc_sink_release(struct dc_sink *sink); 1363 1364 struct dc_sink_init_data { 1365 enum signal_type sink_signal; 1366 struct dc_link *link; 1367 uint32_t dongle_max_pix_clk; 1368 bool converter_disable_audio; 1369 }; 1370 1371 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1372 1373 /* Newer interfaces */ 1374 struct dc_cursor { 1375 struct dc_plane_address address; 1376 struct dc_cursor_attributes attributes; 1377 }; 1378 1379 1380 /******************************************************************************* 1381 * Interrupt interfaces 1382 ******************************************************************************/ 1383 enum dc_irq_source dc_interrupt_to_irq_source( 1384 struct dc *dc, 1385 uint32_t src_id, 1386 uint32_t ext_id); 1387 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1388 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1389 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1390 struct dc *dc, uint32_t link_index); 1391 1392 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1393 1394 /******************************************************************************* 1395 * Power Interfaces 1396 ******************************************************************************/ 1397 1398 void dc_set_power_state( 1399 struct dc *dc, 1400 enum dc_acpi_cm_power_state power_state); 1401 void dc_resume(struct dc *dc); 1402 1403 void dc_power_down_on_boot(struct dc *dc); 1404 1405 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1406 /* 1407 * HDCP Interfaces 1408 */ 1409 enum hdcp_message_status dc_process_hdcp_msg( 1410 enum signal_type signal, 1411 struct dc_link *link, 1412 struct hdcp_protection_message *message_info); 1413 #endif 1414 bool dc_is_dmcu_initialized(struct dc *dc); 1415 1416 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1417 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1418 #if defined(CONFIG_DRM_AMD_DC_DCN) 1419 1420 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1421 struct dc_cursor_attributes *cursor_attr); 1422 1423 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1424 1425 /* 1426 * blank all streams, and set min and max memory clock to 1427 * lowest and highest DPM level, respectively 1428 */ 1429 void dc_unlock_memory_clock_frequency(struct dc *dc); 1430 1431 /* 1432 * set min memory clock to the min required for current mode, 1433 * max to maxDPM, and unblank streams 1434 */ 1435 void dc_lock_memory_clock_frequency(struct dc *dc); 1436 1437 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1438 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1439 1440 /* cleanup on driver unload */ 1441 void dc_hardware_release(struct dc *dc); 1442 1443 #endif 1444 1445 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1446 #if defined(CONFIG_DRM_AMD_DC_DCN) 1447 void dc_z10_restore(const struct dc *dc); 1448 void dc_z10_save_init(struct dc *dc); 1449 #endif 1450 1451 bool dc_enable_dmub_notifications(struct dc *dc); 1452 1453 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1454 uint32_t link_index, 1455 struct aux_payload *payload); 1456 1457 /* Get dc link index from dpia port index */ 1458 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1459 uint8_t dpia_port_index); 1460 1461 bool dc_process_dmub_set_config_async(struct dc *dc, 1462 uint32_t link_index, 1463 struct set_config_cmd_payload *payload, 1464 struct dmub_notification *notify); 1465 1466 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1467 uint32_t link_index, 1468 uint8_t mst_alloc_slots, 1469 uint8_t *mst_slots_in_use); 1470 1471 /******************************************************************************* 1472 * DSC Interfaces 1473 ******************************************************************************/ 1474 #include "dc_dsc.h" 1475 1476 /******************************************************************************* 1477 * Disable acc mode Interfaces 1478 ******************************************************************************/ 1479 void dc_disable_accelerated_mode(struct dc *dc); 1480 1481 #endif /* DC_INTERFACE_H_ */ 1482