1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 48 #define DC_VER "3.2.133" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MAX_SINKS_PER_LINK 4 54 #define MIN_VIEWPORT_SIZE 12 55 #define MAX_NUM_EDP 2 56 57 /******************************************************************************* 58 * Display Core Interfaces 59 ******************************************************************************/ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 struct dc_plane_cap { 77 enum dc_plane_type type; 78 uint32_t blends_with_above : 1; 79 uint32_t blends_with_below : 1; 80 uint32_t per_pixel_alpha : 1; 81 struct { 82 uint32_t argb8888 : 1; 83 uint32_t nv12 : 1; 84 uint32_t fp16 : 1; 85 uint32_t p010 : 1; 86 uint32_t ayuv : 1; 87 } pixel_format_support; 88 // max upscaling factor x1000 89 // upscaling factors are always >= 1 90 // for example, 1080p -> 8K is 4.0, or 4000 raw value 91 struct { 92 uint32_t argb8888; 93 uint32_t nv12; 94 uint32_t fp16; 95 } max_upscale_factor; 96 // max downscale factor x1000 97 // downscale factors are always <= 1 98 // for example, 8K -> 1080p is 0.25, or 250 raw value 99 struct { 100 uint32_t argb8888; 101 uint32_t nv12; 102 uint32_t fp16; 103 } max_downscale_factor; 104 // minimal width/height 105 uint32_t min_width; 106 uint32_t min_height; 107 }; 108 109 // Color management caps (DPP and MPC) 110 struct rom_curve_caps { 111 uint16_t srgb : 1; 112 uint16_t bt2020 : 1; 113 uint16_t gamma2_2 : 1; 114 uint16_t pq : 1; 115 uint16_t hlg : 1; 116 }; 117 118 struct dpp_color_caps { 119 uint16_t dcn_arch : 1; // all DCE generations treated the same 120 // input lut is different than most LUTs, just plain 256-entry lookup 121 uint16_t input_lut_shared : 1; // shared with DGAM 122 uint16_t icsc : 1; 123 uint16_t dgam_ram : 1; 124 uint16_t post_csc : 1; // before gamut remap 125 uint16_t gamma_corr : 1; 126 127 // hdr_mult and gamut remap always available in DPP (in that order) 128 // 3d lut implies shaper LUT, 129 // it may be shared with MPC - check MPC:shared_3d_lut flag 130 uint16_t hw_3d_lut : 1; 131 uint16_t ogam_ram : 1; // blnd gam 132 uint16_t ocsc : 1; 133 uint16_t dgam_rom_for_yuv : 1; 134 struct rom_curve_caps dgam_rom_caps; 135 struct rom_curve_caps ogam_rom_caps; 136 }; 137 138 struct mpc_color_caps { 139 uint16_t gamut_remap : 1; 140 uint16_t ogam_ram : 1; 141 uint16_t ocsc : 1; 142 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 143 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 144 145 struct rom_curve_caps ogam_rom_caps; 146 }; 147 148 struct dc_color_caps { 149 struct dpp_color_caps dpp; 150 struct mpc_color_caps mpc; 151 }; 152 153 struct dc_caps { 154 uint32_t max_streams; 155 uint32_t max_links; 156 uint32_t max_audios; 157 uint32_t max_slave_planes; 158 uint32_t max_slave_yuv_planes; 159 uint32_t max_slave_rgb_planes; 160 uint32_t max_planes; 161 uint32_t max_downscale_ratio; 162 uint32_t i2c_speed_in_khz; 163 uint32_t i2c_speed_in_khz_hdcp; 164 uint32_t dmdata_alloc_size; 165 unsigned int max_cursor_size; 166 unsigned int max_video_width; 167 unsigned int min_horizontal_blanking_period; 168 int linear_pitch_alignment; 169 bool dcc_const_color; 170 bool dynamic_audio; 171 bool is_apu; 172 bool dual_link_dvi; 173 bool post_blend_color_processing; 174 bool force_dp_tps4_for_cp2520; 175 bool disable_dp_clk_share; 176 bool psp_setup_panel_mode; 177 bool extended_aux_timeout_support; 178 bool dmcub_support; 179 uint32_t num_of_internal_disp; 180 enum dp_protocol_version max_dp_protocol_version; 181 unsigned int mall_size_per_mem_channel; 182 unsigned int mall_size_total; 183 unsigned int cursor_cache_size; 184 struct dc_plane_cap planes[MAX_PLANES]; 185 struct dc_color_caps color; 186 }; 187 188 struct dc_bug_wa { 189 bool no_connect_phy_config; 190 bool dedcn20_305_wa; 191 bool skip_clock_update; 192 bool lt_early_cr_pattern; 193 }; 194 195 struct dc_dcc_surface_param { 196 struct dc_size surface_size; 197 enum surface_pixel_format format; 198 enum swizzle_mode_values swizzle_mode; 199 enum dc_scan_direction scan; 200 }; 201 202 struct dc_dcc_setting { 203 unsigned int max_compressed_blk_size; 204 unsigned int max_uncompressed_blk_size; 205 bool independent_64b_blks; 206 #if defined(CONFIG_DRM_AMD_DC_DCN) 207 //These bitfields to be used starting with DCN 3.0 208 struct { 209 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 210 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 211 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 212 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 213 } dcc_controls; 214 #endif 215 }; 216 217 struct dc_surface_dcc_cap { 218 union { 219 struct { 220 struct dc_dcc_setting rgb; 221 } grph; 222 223 struct { 224 struct dc_dcc_setting luma; 225 struct dc_dcc_setting chroma; 226 } video; 227 }; 228 229 bool capable; 230 bool const_color_support; 231 }; 232 233 struct dc_static_screen_params { 234 struct { 235 bool force_trigger; 236 bool cursor_update; 237 bool surface_update; 238 bool overlay_update; 239 } triggers; 240 unsigned int num_frames; 241 }; 242 243 244 /* Surface update type is used by dc_update_surfaces_and_stream 245 * The update type is determined at the very beginning of the function based 246 * on parameters passed in and decides how much programming (or updating) is 247 * going to be done during the call. 248 * 249 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 250 * logical calculations or hardware register programming. This update MUST be 251 * ISR safe on windows. Currently fast update will only be used to flip surface 252 * address. 253 * 254 * UPDATE_TYPE_MED is used for slower updates which require significant hw 255 * re-programming however do not affect bandwidth consumption or clock 256 * requirements. At present, this is the level at which front end updates 257 * that do not require us to run bw_calcs happen. These are in/out transfer func 258 * updates, viewport offset changes, recout size changes and pixel depth changes. 259 * This update can be done at ISR, but we want to minimize how often this happens. 260 * 261 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 262 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 263 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 264 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 265 * a full update. This cannot be done at ISR level and should be a rare event. 266 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 267 * underscan we don't expect to see this call at all. 268 */ 269 270 enum surface_update_type { 271 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 272 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 273 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 274 }; 275 276 /* Forward declaration*/ 277 struct dc; 278 struct dc_plane_state; 279 struct dc_state; 280 281 282 struct dc_cap_funcs { 283 bool (*get_dcc_compression_cap)(const struct dc *dc, 284 const struct dc_dcc_surface_param *input, 285 struct dc_surface_dcc_cap *output); 286 }; 287 288 struct link_training_settings; 289 290 291 /* Structure to hold configuration flags set by dm at dc creation. */ 292 struct dc_config { 293 bool gpu_vm_support; 294 bool disable_disp_pll_sharing; 295 bool fbc_support; 296 bool disable_fractional_pwm; 297 bool allow_seamless_boot_optimization; 298 bool power_down_display_on_boot; 299 bool edp_not_connected; 300 bool force_enum_edp; 301 bool forced_clocks; 302 bool allow_lttpr_non_transparent_mode; 303 bool multi_mon_pp_mclk_switch; 304 bool disable_dmcu; 305 bool enable_4to1MPC; 306 #if defined(CONFIG_DRM_AMD_DC_DCN) 307 bool clamp_min_dcfclk; 308 #endif 309 uint64_t vblank_alignment_dto_params; 310 uint8_t vblank_alignment_max_frame_time_diff; 311 }; 312 313 enum visual_confirm { 314 VISUAL_CONFIRM_DISABLE = 0, 315 VISUAL_CONFIRM_SURFACE = 1, 316 VISUAL_CONFIRM_HDR = 2, 317 VISUAL_CONFIRM_MPCTREE = 4, 318 VISUAL_CONFIRM_PSR = 5, 319 }; 320 321 enum dcc_option { 322 DCC_ENABLE = 0, 323 DCC_DISABLE = 1, 324 DCC_HALF_REQ_DISALBE = 2, 325 }; 326 327 enum pipe_split_policy { 328 MPC_SPLIT_DYNAMIC = 0, 329 MPC_SPLIT_AVOID = 1, 330 MPC_SPLIT_AVOID_MULT_DISP = 2, 331 }; 332 333 enum wm_report_mode { 334 WM_REPORT_DEFAULT = 0, 335 WM_REPORT_OVERRIDE = 1, 336 }; 337 enum dtm_pstate{ 338 dtm_level_p0 = 0,/*highest voltage*/ 339 dtm_level_p1, 340 dtm_level_p2, 341 dtm_level_p3, 342 dtm_level_p4,/*when active_display_count = 0*/ 343 }; 344 345 enum dcn_pwr_state { 346 DCN_PWR_STATE_UNKNOWN = -1, 347 DCN_PWR_STATE_MISSION_MODE = 0, 348 DCN_PWR_STATE_LOW_POWER = 3, 349 }; 350 351 /* 352 * For any clocks that may differ per pipe 353 * only the max is stored in this structure 354 */ 355 struct dc_clocks { 356 int dispclk_khz; 357 int actual_dispclk_khz; 358 int dppclk_khz; 359 int actual_dppclk_khz; 360 int disp_dpp_voltage_level_khz; 361 int dcfclk_khz; 362 int socclk_khz; 363 int dcfclk_deep_sleep_khz; 364 int fclk_khz; 365 int phyclk_khz; 366 int dramclk_khz; 367 bool p_state_change_support; 368 enum dcn_pwr_state pwr_state; 369 /* 370 * Elements below are not compared for the purposes of 371 * optimization required 372 */ 373 bool prev_p_state_change_support; 374 enum dtm_pstate dtm_level; 375 int max_supported_dppclk_khz; 376 int max_supported_dispclk_khz; 377 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 378 int bw_dispclk_khz; 379 }; 380 381 struct dc_bw_validation_profile { 382 bool enable; 383 384 unsigned long long total_ticks; 385 unsigned long long voltage_level_ticks; 386 unsigned long long watermark_ticks; 387 unsigned long long rq_dlg_ticks; 388 389 unsigned long long total_count; 390 unsigned long long skip_fast_count; 391 unsigned long long skip_pass_count; 392 unsigned long long skip_fail_count; 393 }; 394 395 #define BW_VAL_TRACE_SETUP() \ 396 unsigned long long end_tick = 0; \ 397 unsigned long long voltage_level_tick = 0; \ 398 unsigned long long watermark_tick = 0; \ 399 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 400 dm_get_timestamp(dc->ctx) : 0 401 402 #define BW_VAL_TRACE_COUNT() \ 403 if (dc->debug.bw_val_profile.enable) \ 404 dc->debug.bw_val_profile.total_count++ 405 406 #define BW_VAL_TRACE_SKIP(status) \ 407 if (dc->debug.bw_val_profile.enable) { \ 408 if (!voltage_level_tick) \ 409 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 410 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 411 } 412 413 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 414 if (dc->debug.bw_val_profile.enable) \ 415 voltage_level_tick = dm_get_timestamp(dc->ctx) 416 417 #define BW_VAL_TRACE_END_WATERMARKS() \ 418 if (dc->debug.bw_val_profile.enable) \ 419 watermark_tick = dm_get_timestamp(dc->ctx) 420 421 #define BW_VAL_TRACE_FINISH() \ 422 if (dc->debug.bw_val_profile.enable) { \ 423 end_tick = dm_get_timestamp(dc->ctx); \ 424 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 425 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 426 if (watermark_tick) { \ 427 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 428 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 429 } \ 430 } 431 432 union mem_low_power_enable_options { 433 struct { 434 bool i2c: 1; 435 bool dmcu: 1; 436 bool dscl: 1; 437 bool cm: 1; 438 bool mpc: 1; 439 bool optc: 1; 440 } bits; 441 uint32_t u32All; 442 }; 443 444 struct dc_debug_options { 445 enum visual_confirm visual_confirm; 446 bool sanity_checks; 447 bool max_disp_clk; 448 bool surface_trace; 449 bool timing_trace; 450 bool clock_trace; 451 bool validation_trace; 452 bool bandwidth_calcs_trace; 453 int max_downscale_src_width; 454 455 /* stutter efficiency related */ 456 bool disable_stutter; 457 bool use_max_lb; 458 enum dcc_option disable_dcc; 459 enum pipe_split_policy pipe_split_policy; 460 bool force_single_disp_pipe_split; 461 bool voltage_align_fclk; 462 bool disable_min_fclk; 463 464 bool disable_dfs_bypass; 465 bool disable_dpp_power_gate; 466 bool disable_hubp_power_gate; 467 bool disable_dsc_power_gate; 468 int dsc_min_slice_height_override; 469 int dsc_bpp_increment_div; 470 bool native422_support; 471 bool disable_pplib_wm_range; 472 enum wm_report_mode pplib_wm_report_mode; 473 unsigned int min_disp_clk_khz; 474 unsigned int min_dpp_clk_khz; 475 int sr_exit_time_dpm0_ns; 476 int sr_enter_plus_exit_time_dpm0_ns; 477 int sr_exit_time_ns; 478 int sr_enter_plus_exit_time_ns; 479 int urgent_latency_ns; 480 uint32_t underflow_assert_delay_us; 481 int percent_of_ideal_drambw; 482 int dram_clock_change_latency_ns; 483 bool optimized_watermark; 484 int always_scale; 485 bool disable_pplib_clock_request; 486 bool disable_clock_gate; 487 bool disable_mem_low_power; 488 bool disable_dmcu; 489 bool disable_psr; 490 bool force_abm_enable; 491 bool disable_stereo_support; 492 bool vsr_support; 493 bool performance_trace; 494 bool az_endpoint_mute_only; 495 bool always_use_regamma; 496 bool recovery_enabled; 497 bool avoid_vbios_exec_table; 498 bool scl_reset_length10; 499 bool hdmi20_disable; 500 bool skip_detection_link_training; 501 uint32_t edid_read_retry_times; 502 bool remove_disconnect_edp; 503 unsigned int force_odm_combine; //bit vector based on otg inst 504 #if defined(CONFIG_DRM_AMD_DC_DCN) 505 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 506 #endif 507 unsigned int force_fclk_khz; 508 bool enable_tri_buf; 509 bool dmub_offload_enabled; 510 bool dmcub_emulation; 511 #if defined(CONFIG_DRM_AMD_DC_DCN) 512 bool disable_idle_power_optimizations; 513 unsigned int mall_size_override; 514 unsigned int mall_additional_timer_percent; 515 bool mall_error_as_fatal; 516 #endif 517 bool dmub_command_table; /* for testing only */ 518 struct dc_bw_validation_profile bw_val_profile; 519 bool disable_fec; 520 bool disable_48mhz_pwrdwn; 521 /* This forces a hard min on the DCFCLK requested to SMU/PP 522 * watermarks are not affected. 523 */ 524 unsigned int force_min_dcfclk_mhz; 525 #if defined(CONFIG_DRM_AMD_DC_DCN) 526 int dwb_fi_phase; 527 #endif 528 bool disable_timing_sync; 529 bool cm_in_bypass; 530 int force_clock_mode;/*every mode change.*/ 531 532 bool disable_dram_clock_change_vactive_support; 533 bool validate_dml_output; 534 bool enable_dmcub_surface_flip; 535 bool usbc_combo_phy_reset_wa; 536 bool disable_dsc; 537 bool enable_dram_clock_change_one_display_vactive; 538 union mem_low_power_enable_options enable_mem_low_power; 539 bool force_vblank_alignment; 540 541 /* Enable dmub aux for legacy ddc */ 542 bool enable_dmub_aux_for_legacy_ddc; 543 bool optimize_edp_link_rate; /* eDP ILR */ 544 /* force enable edp FEC */ 545 bool force_enable_edp_fec; 546 /* FEC/PSR1 sequence enable delay in 100us */ 547 uint8_t fec_enable_delay_in100us; 548 }; 549 550 struct dc_debug_data { 551 uint32_t ltFailCount; 552 uint32_t i2cErrorCount; 553 uint32_t auxErrorCount; 554 }; 555 556 struct dc_phy_addr_space_config { 557 struct { 558 uint64_t start_addr; 559 uint64_t end_addr; 560 uint64_t fb_top; 561 uint64_t fb_offset; 562 uint64_t fb_base; 563 uint64_t agp_top; 564 uint64_t agp_bot; 565 uint64_t agp_base; 566 } system_aperture; 567 568 struct { 569 uint64_t page_table_start_addr; 570 uint64_t page_table_end_addr; 571 uint64_t page_table_base_addr; 572 } gart_config; 573 574 bool valid; 575 bool is_hvm_enabled; 576 uint64_t page_table_default_page_addr; 577 }; 578 579 struct dc_virtual_addr_space_config { 580 uint64_t page_table_base_addr; 581 uint64_t page_table_start_addr; 582 uint64_t page_table_end_addr; 583 uint32_t page_table_block_size_in_bytes; 584 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 585 }; 586 587 struct dc_bounding_box_overrides { 588 int sr_exit_time_ns; 589 int sr_enter_plus_exit_time_ns; 590 int urgent_latency_ns; 591 int percent_of_ideal_drambw; 592 int dram_clock_change_latency_ns; 593 int dummy_clock_change_latency_ns; 594 /* This forces a hard min on the DCFCLK we use 595 * for DML. Unlike the debug option for forcing 596 * DCFCLK, this override affects watermark calculations 597 */ 598 int min_dcfclk_mhz; 599 }; 600 601 struct resource_pool; 602 struct dce_hwseq; 603 struct gpu_info_soc_bounding_box_v1_0; 604 struct dc { 605 struct dc_versions versions; 606 struct dc_caps caps; 607 struct dc_cap_funcs cap_funcs; 608 struct dc_config config; 609 struct dc_debug_options debug; 610 struct dc_bounding_box_overrides bb_overrides; 611 struct dc_bug_wa work_arounds; 612 struct dc_context *ctx; 613 struct dc_phy_addr_space_config vm_pa_config; 614 615 uint8_t link_count; 616 struct dc_link *links[MAX_PIPES * 2]; 617 618 struct dc_state *current_state; 619 struct resource_pool *res_pool; 620 621 struct clk_mgr *clk_mgr; 622 623 /* Display Engine Clock levels */ 624 struct dm_pp_clock_levels sclk_lvls; 625 626 /* Inputs into BW and WM calculations. */ 627 struct bw_calcs_dceip *bw_dceip; 628 struct bw_calcs_vbios *bw_vbios; 629 #ifdef CONFIG_DRM_AMD_DC_DCN 630 struct dcn_soc_bounding_box *dcn_soc; 631 struct dcn_ip_params *dcn_ip; 632 struct display_mode_lib dml; 633 #endif 634 635 /* HW functions */ 636 struct hw_sequencer_funcs hwss; 637 struct dce_hwseq *hwseq; 638 639 /* Require to optimize clocks and bandwidth for added/removed planes */ 640 bool optimized_required; 641 bool wm_optimized_required; 642 #if defined(CONFIG_DRM_AMD_DC_DCN) 643 bool idle_optimizations_allowed; 644 #endif 645 646 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 647 648 /* FBC compressor */ 649 struct compressor *fbc_compressor; 650 651 struct dc_debug_data debug_data; 652 struct dpcd_vendor_signature vendor_signature; 653 654 const char *build_id; 655 struct vm_helper *vm_helper; 656 }; 657 658 enum frame_buffer_mode { 659 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 660 FRAME_BUFFER_MODE_ZFB_ONLY, 661 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 662 } ; 663 664 struct dchub_init_data { 665 int64_t zfb_phys_addr_base; 666 int64_t zfb_mc_base_addr; 667 uint64_t zfb_size_in_byte; 668 enum frame_buffer_mode fb_mode; 669 bool dchub_initialzied; 670 bool dchub_info_valid; 671 }; 672 673 struct dc_init_data { 674 struct hw_asic_id asic_id; 675 void *driver; /* ctx */ 676 struct cgs_device *cgs_device; 677 struct dc_bounding_box_overrides bb_overrides; 678 679 int num_virtual_links; 680 /* 681 * If 'vbios_override' not NULL, it will be called instead 682 * of the real VBIOS. Intended use is Diagnostics on FPGA. 683 */ 684 struct dc_bios *vbios_override; 685 enum dce_environment dce_environment; 686 687 struct dmub_offload_funcs *dmub_if; 688 struct dc_reg_helper_state *dmub_offload; 689 690 struct dc_config flags; 691 uint64_t log_mask; 692 693 struct dpcd_vendor_signature vendor_signature; 694 #if defined(CONFIG_DRM_AMD_DC_DCN) 695 bool force_smu_not_present; 696 #endif 697 }; 698 699 struct dc_callback_init { 700 #ifdef CONFIG_DRM_AMD_DC_HDCP 701 struct cp_psp cp_psp; 702 #else 703 uint8_t reserved; 704 #endif 705 }; 706 707 struct dc *dc_create(const struct dc_init_data *init_params); 708 void dc_hardware_init(struct dc *dc); 709 710 int dc_get_vmid_use_vector(struct dc *dc); 711 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 712 /* Returns the number of vmids supported */ 713 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 714 void dc_init_callbacks(struct dc *dc, 715 const struct dc_callback_init *init_params); 716 void dc_deinit_callbacks(struct dc *dc); 717 void dc_destroy(struct dc **dc); 718 719 /******************************************************************************* 720 * Surface Interfaces 721 ******************************************************************************/ 722 723 enum { 724 TRANSFER_FUNC_POINTS = 1025 725 }; 726 727 struct dc_hdr_static_metadata { 728 /* display chromaticities and white point in units of 0.00001 */ 729 unsigned int chromaticity_green_x; 730 unsigned int chromaticity_green_y; 731 unsigned int chromaticity_blue_x; 732 unsigned int chromaticity_blue_y; 733 unsigned int chromaticity_red_x; 734 unsigned int chromaticity_red_y; 735 unsigned int chromaticity_white_point_x; 736 unsigned int chromaticity_white_point_y; 737 738 uint32_t min_luminance; 739 uint32_t max_luminance; 740 uint32_t maximum_content_light_level; 741 uint32_t maximum_frame_average_light_level; 742 }; 743 744 enum dc_transfer_func_type { 745 TF_TYPE_PREDEFINED, 746 TF_TYPE_DISTRIBUTED_POINTS, 747 TF_TYPE_BYPASS, 748 TF_TYPE_HWPWL 749 }; 750 751 struct dc_transfer_func_distributed_points { 752 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 753 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 754 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 755 756 uint16_t end_exponent; 757 uint16_t x_point_at_y1_red; 758 uint16_t x_point_at_y1_green; 759 uint16_t x_point_at_y1_blue; 760 }; 761 762 enum dc_transfer_func_predefined { 763 TRANSFER_FUNCTION_SRGB, 764 TRANSFER_FUNCTION_BT709, 765 TRANSFER_FUNCTION_PQ, 766 TRANSFER_FUNCTION_LINEAR, 767 TRANSFER_FUNCTION_UNITY, 768 TRANSFER_FUNCTION_HLG, 769 TRANSFER_FUNCTION_HLG12, 770 TRANSFER_FUNCTION_GAMMA22, 771 TRANSFER_FUNCTION_GAMMA24, 772 TRANSFER_FUNCTION_GAMMA26 773 }; 774 775 776 struct dc_transfer_func { 777 struct kref refcount; 778 enum dc_transfer_func_type type; 779 enum dc_transfer_func_predefined tf; 780 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 781 uint32_t sdr_ref_white_level; 782 union { 783 struct pwl_params pwl; 784 struct dc_transfer_func_distributed_points tf_pts; 785 }; 786 }; 787 788 789 union dc_3dlut_state { 790 struct { 791 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 792 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 793 uint32_t rmu_mux_num:3; /*index of mux to use*/ 794 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 795 uint32_t mpc_rmu1_mux:4; 796 uint32_t mpc_rmu2_mux:4; 797 uint32_t reserved:15; 798 } bits; 799 uint32_t raw; 800 }; 801 802 803 struct dc_3dlut { 804 struct kref refcount; 805 struct tetrahedral_params lut_3d; 806 struct fixed31_32 hdr_multiplier; 807 union dc_3dlut_state state; 808 }; 809 /* 810 * This structure is filled in by dc_surface_get_status and contains 811 * the last requested address and the currently active address so the called 812 * can determine if there are any outstanding flips 813 */ 814 struct dc_plane_status { 815 struct dc_plane_address requested_address; 816 struct dc_plane_address current_address; 817 bool is_flip_pending; 818 bool is_right_eye; 819 }; 820 821 union surface_update_flags { 822 823 struct { 824 uint32_t addr_update:1; 825 /* Medium updates */ 826 uint32_t dcc_change:1; 827 uint32_t color_space_change:1; 828 uint32_t horizontal_mirror_change:1; 829 uint32_t per_pixel_alpha_change:1; 830 uint32_t global_alpha_change:1; 831 uint32_t hdr_mult:1; 832 uint32_t rotation_change:1; 833 uint32_t swizzle_change:1; 834 uint32_t scaling_change:1; 835 uint32_t position_change:1; 836 uint32_t in_transfer_func_change:1; 837 uint32_t input_csc_change:1; 838 uint32_t coeff_reduction_change:1; 839 uint32_t output_tf_change:1; 840 uint32_t pixel_format_change:1; 841 uint32_t plane_size_change:1; 842 uint32_t gamut_remap_change:1; 843 844 /* Full updates */ 845 uint32_t new_plane:1; 846 uint32_t bpp_change:1; 847 uint32_t gamma_change:1; 848 uint32_t bandwidth_change:1; 849 uint32_t clock_change:1; 850 uint32_t stereo_format_change:1; 851 uint32_t full_update:1; 852 } bits; 853 854 uint32_t raw; 855 }; 856 857 struct dc_plane_state { 858 struct dc_plane_address address; 859 struct dc_plane_flip_time time; 860 bool triplebuffer_flips; 861 struct scaling_taps scaling_quality; 862 struct rect src_rect; 863 struct rect dst_rect; 864 struct rect clip_rect; 865 866 struct plane_size plane_size; 867 union dc_tiling_info tiling_info; 868 869 struct dc_plane_dcc_param dcc; 870 871 struct dc_gamma *gamma_correction; 872 struct dc_transfer_func *in_transfer_func; 873 struct dc_bias_and_scale *bias_and_scale; 874 struct dc_csc_transform input_csc_color_matrix; 875 struct fixed31_32 coeff_reduction_factor; 876 struct fixed31_32 hdr_mult; 877 struct colorspace_transform gamut_remap_matrix; 878 879 // TODO: No longer used, remove 880 struct dc_hdr_static_metadata hdr_static_ctx; 881 882 enum dc_color_space color_space; 883 884 struct dc_3dlut *lut3d_func; 885 struct dc_transfer_func *in_shaper_func; 886 struct dc_transfer_func *blend_tf; 887 888 #if defined(CONFIG_DRM_AMD_DC_DCN) 889 struct dc_transfer_func *gamcor_tf; 890 #endif 891 enum surface_pixel_format format; 892 enum dc_rotation_angle rotation; 893 enum plane_stereo_format stereo_format; 894 895 bool is_tiling_rotated; 896 bool per_pixel_alpha; 897 bool global_alpha; 898 int global_alpha_value; 899 bool visible; 900 bool flip_immediate; 901 bool horizontal_mirror; 902 int layer_index; 903 904 union surface_update_flags update_flags; 905 bool flip_int_enabled; 906 bool skip_manual_trigger; 907 908 /* private to DC core */ 909 struct dc_plane_status status; 910 struct dc_context *ctx; 911 912 /* HACK: Workaround for forcing full reprogramming under some conditions */ 913 bool force_full_update; 914 915 /* private to dc_surface.c */ 916 enum dc_irq_source irq_source; 917 struct kref refcount; 918 }; 919 920 struct dc_plane_info { 921 struct plane_size plane_size; 922 union dc_tiling_info tiling_info; 923 struct dc_plane_dcc_param dcc; 924 enum surface_pixel_format format; 925 enum dc_rotation_angle rotation; 926 enum plane_stereo_format stereo_format; 927 enum dc_color_space color_space; 928 bool horizontal_mirror; 929 bool visible; 930 bool per_pixel_alpha; 931 bool global_alpha; 932 int global_alpha_value; 933 bool input_csc_enabled; 934 int layer_index; 935 }; 936 937 struct dc_scaling_info { 938 struct rect src_rect; 939 struct rect dst_rect; 940 struct rect clip_rect; 941 struct scaling_taps scaling_quality; 942 }; 943 944 struct dc_surface_update { 945 struct dc_plane_state *surface; 946 947 /* isr safe update parameters. null means no updates */ 948 const struct dc_flip_addrs *flip_addr; 949 const struct dc_plane_info *plane_info; 950 const struct dc_scaling_info *scaling_info; 951 struct fixed31_32 hdr_mult; 952 /* following updates require alloc/sleep/spin that is not isr safe, 953 * null means no updates 954 */ 955 const struct dc_gamma *gamma; 956 const struct dc_transfer_func *in_transfer_func; 957 958 const struct dc_csc_transform *input_csc_color_matrix; 959 const struct fixed31_32 *coeff_reduction_factor; 960 const struct dc_transfer_func *func_shaper; 961 const struct dc_3dlut *lut3d_func; 962 const struct dc_transfer_func *blend_tf; 963 const struct colorspace_transform *gamut_remap_matrix; 964 }; 965 966 /* 967 * Create a new surface with default parameters; 968 */ 969 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 970 const struct dc_plane_status *dc_plane_get_status( 971 const struct dc_plane_state *plane_state); 972 973 void dc_plane_state_retain(struct dc_plane_state *plane_state); 974 void dc_plane_state_release(struct dc_plane_state *plane_state); 975 976 void dc_gamma_retain(struct dc_gamma *dc_gamma); 977 void dc_gamma_release(struct dc_gamma **dc_gamma); 978 struct dc_gamma *dc_create_gamma(void); 979 980 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 981 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 982 struct dc_transfer_func *dc_create_transfer_func(void); 983 984 struct dc_3dlut *dc_create_3dlut_func(void); 985 void dc_3dlut_func_release(struct dc_3dlut *lut); 986 void dc_3dlut_func_retain(struct dc_3dlut *lut); 987 /* 988 * This structure holds a surface address. There could be multiple addresses 989 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 990 * as frame durations and DCC format can also be set. 991 */ 992 struct dc_flip_addrs { 993 struct dc_plane_address address; 994 unsigned int flip_timestamp_in_us; 995 bool flip_immediate; 996 /* TODO: add flip duration for FreeSync */ 997 bool triplebuffer_flips; 998 }; 999 1000 void dc_post_update_surfaces_to_stream( 1001 struct dc *dc); 1002 1003 #include "dc_stream.h" 1004 1005 /* 1006 * Structure to store surface/stream associations for validation 1007 */ 1008 struct dc_validation_set { 1009 struct dc_stream_state *stream; 1010 struct dc_plane_state *plane_states[MAX_SURFACES]; 1011 uint8_t plane_count; 1012 }; 1013 1014 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1015 const struct dc_sink *sink, 1016 struct dc_crtc_timing *crtc_timing); 1017 1018 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1019 1020 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1021 1022 bool dc_set_generic_gpio_for_stereo(bool enable, 1023 struct gpio_service *gpio_service); 1024 1025 /* 1026 * fast_validate: we return after determining if we can support the new state, 1027 * but before we populate the programming info 1028 */ 1029 enum dc_status dc_validate_global_state( 1030 struct dc *dc, 1031 struct dc_state *new_ctx, 1032 bool fast_validate); 1033 1034 1035 void dc_resource_state_construct( 1036 const struct dc *dc, 1037 struct dc_state *dst_ctx); 1038 1039 #if defined(CONFIG_DRM_AMD_DC_DCN) 1040 bool dc_acquire_release_mpc_3dlut( 1041 struct dc *dc, bool acquire, 1042 struct dc_stream_state *stream, 1043 struct dc_3dlut **lut, 1044 struct dc_transfer_func **shaper); 1045 #endif 1046 1047 void dc_resource_state_copy_construct( 1048 const struct dc_state *src_ctx, 1049 struct dc_state *dst_ctx); 1050 1051 void dc_resource_state_copy_construct_current( 1052 const struct dc *dc, 1053 struct dc_state *dst_ctx); 1054 1055 void dc_resource_state_destruct(struct dc_state *context); 1056 1057 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1058 1059 /* 1060 * TODO update to make it about validation sets 1061 * Set up streams and links associated to drive sinks 1062 * The streams parameter is an absolute set of all active streams. 1063 * 1064 * After this call: 1065 * Phy, Encoder, Timing Generator are programmed and enabled. 1066 * New streams are enabled with blank stream; no memory read. 1067 */ 1068 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1069 1070 void dc_power_down_on_boot(struct dc *dc); 1071 1072 struct dc_state *dc_create_state(struct dc *dc); 1073 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1074 void dc_retain_state(struct dc_state *context); 1075 void dc_release_state(struct dc_state *context); 1076 1077 /******************************************************************************* 1078 * Link Interfaces 1079 ******************************************************************************/ 1080 1081 struct dpcd_caps { 1082 union dpcd_rev dpcd_rev; 1083 union max_lane_count max_ln_count; 1084 union max_down_spread max_down_spread; 1085 union dprx_feature dprx_feature; 1086 1087 /* valid only for eDP v1.4 or higher*/ 1088 uint8_t edp_supported_link_rates_count; 1089 enum dc_link_rate edp_supported_link_rates[8]; 1090 1091 /* dongle type (DP converter, CV smart dongle) */ 1092 enum display_dongle_type dongle_type; 1093 /* branch device or sink device */ 1094 bool is_branch_dev; 1095 /* Dongle's downstream count. */ 1096 union sink_count sink_count; 1097 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1098 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1099 struct dc_dongle_caps dongle_caps; 1100 1101 uint32_t sink_dev_id; 1102 int8_t sink_dev_id_str[6]; 1103 int8_t sink_hw_revision; 1104 int8_t sink_fw_revision[2]; 1105 1106 uint32_t branch_dev_id; 1107 int8_t branch_dev_name[6]; 1108 int8_t branch_hw_revision; 1109 int8_t branch_fw_revision[2]; 1110 1111 bool allow_invalid_MSA_timing_param; 1112 bool panel_mode_edp; 1113 bool dpcd_display_control_capable; 1114 bool ext_receiver_cap_field_present; 1115 bool dynamic_backlight_capable_edp; 1116 union dpcd_fec_capability fec_cap; 1117 struct dpcd_dsc_capabilities dsc_caps; 1118 struct dc_lttpr_caps lttpr_caps; 1119 struct psr_caps psr_caps; 1120 1121 }; 1122 1123 union dpcd_sink_ext_caps { 1124 struct { 1125 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1126 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1127 */ 1128 uint8_t sdr_aux_backlight_control : 1; 1129 uint8_t hdr_aux_backlight_control : 1; 1130 uint8_t reserved_1 : 2; 1131 uint8_t oled : 1; 1132 uint8_t reserved : 3; 1133 } bits; 1134 uint8_t raw; 1135 }; 1136 1137 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1138 union hdcp_rx_caps { 1139 struct { 1140 uint8_t version; 1141 uint8_t reserved; 1142 struct { 1143 uint8_t repeater : 1; 1144 uint8_t hdcp_capable : 1; 1145 uint8_t reserved : 6; 1146 } byte0; 1147 } fields; 1148 uint8_t raw[3]; 1149 }; 1150 1151 union hdcp_bcaps { 1152 struct { 1153 uint8_t HDCP_CAPABLE:1; 1154 uint8_t REPEATER:1; 1155 uint8_t RESERVED:6; 1156 } bits; 1157 uint8_t raw; 1158 }; 1159 1160 struct hdcp_caps { 1161 union hdcp_rx_caps rx_caps; 1162 union hdcp_bcaps bcaps; 1163 }; 1164 #endif 1165 1166 #include "dc_link.h" 1167 1168 #if defined(CONFIG_DRM_AMD_DC_DCN) 1169 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1170 1171 #endif 1172 /******************************************************************************* 1173 * Sink Interfaces - A sink corresponds to a display output device 1174 ******************************************************************************/ 1175 1176 struct dc_container_id { 1177 // 128bit GUID in binary form 1178 unsigned char guid[16]; 1179 // 8 byte port ID -> ELD.PortID 1180 unsigned int portId[2]; 1181 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1182 unsigned short manufacturerName; 1183 // 2 byte product code -> ELD.ProductCode 1184 unsigned short productCode; 1185 }; 1186 1187 1188 struct dc_sink_dsc_caps { 1189 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1190 // 'false' if they are sink's DSC caps 1191 bool is_virtual_dpcd_dsc; 1192 struct dsc_dec_dpcd_caps dsc_dec_caps; 1193 }; 1194 1195 struct dc_sink_fec_caps { 1196 bool is_rx_fec_supported; 1197 bool is_topology_fec_supported; 1198 }; 1199 1200 /* 1201 * The sink structure contains EDID and other display device properties 1202 */ 1203 struct dc_sink { 1204 enum signal_type sink_signal; 1205 struct dc_edid dc_edid; /* raw edid */ 1206 struct dc_edid_caps edid_caps; /* parse display caps */ 1207 struct dc_container_id *dc_container_id; 1208 uint32_t dongle_max_pix_clk; 1209 void *priv; 1210 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1211 bool converter_disable_audio; 1212 1213 struct dc_sink_dsc_caps dsc_caps; 1214 struct dc_sink_fec_caps fec_caps; 1215 1216 bool is_vsc_sdp_colorimetry_supported; 1217 1218 /* private to DC core */ 1219 struct dc_link *link; 1220 struct dc_context *ctx; 1221 1222 uint32_t sink_id; 1223 1224 /* private to dc_sink.c */ 1225 // refcount must be the last member in dc_sink, since we want the 1226 // sink structure to be logically cloneable up to (but not including) 1227 // refcount 1228 struct kref refcount; 1229 }; 1230 1231 void dc_sink_retain(struct dc_sink *sink); 1232 void dc_sink_release(struct dc_sink *sink); 1233 1234 struct dc_sink_init_data { 1235 enum signal_type sink_signal; 1236 struct dc_link *link; 1237 uint32_t dongle_max_pix_clk; 1238 bool converter_disable_audio; 1239 }; 1240 1241 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1242 1243 /* Newer interfaces */ 1244 struct dc_cursor { 1245 struct dc_plane_address address; 1246 struct dc_cursor_attributes attributes; 1247 }; 1248 1249 1250 /******************************************************************************* 1251 * Interrupt interfaces 1252 ******************************************************************************/ 1253 enum dc_irq_source dc_interrupt_to_irq_source( 1254 struct dc *dc, 1255 uint32_t src_id, 1256 uint32_t ext_id); 1257 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1258 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1259 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1260 struct dc *dc, uint32_t link_index); 1261 1262 /******************************************************************************* 1263 * Power Interfaces 1264 ******************************************************************************/ 1265 1266 void dc_set_power_state( 1267 struct dc *dc, 1268 enum dc_acpi_cm_power_state power_state); 1269 void dc_resume(struct dc *dc); 1270 1271 void dc_power_down_on_boot(struct dc *dc); 1272 1273 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1274 /* 1275 * HDCP Interfaces 1276 */ 1277 enum hdcp_message_status dc_process_hdcp_msg( 1278 enum signal_type signal, 1279 struct dc_link *link, 1280 struct hdcp_protection_message *message_info); 1281 #endif 1282 bool dc_is_dmcu_initialized(struct dc *dc); 1283 1284 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1285 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1286 #if defined(CONFIG_DRM_AMD_DC_DCN) 1287 1288 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1289 struct dc_cursor_attributes *cursor_attr); 1290 1291 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1292 1293 /* 1294 * blank all streams, and set min and max memory clock to 1295 * lowest and highest DPM level, respectively 1296 */ 1297 void dc_unlock_memory_clock_frequency(struct dc *dc); 1298 1299 /* 1300 * set min memory clock to the min required for current mode, 1301 * max to maxDPM, and unblank streams 1302 */ 1303 void dc_lock_memory_clock_frequency(struct dc *dc); 1304 1305 /* cleanup on driver unload */ 1306 void dc_hardware_release(struct dc *dc); 1307 1308 #endif 1309 1310 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1311 1312 bool dc_enable_dmub_notifications(struct dc *dc); 1313 1314 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1315 uint32_t link_index, 1316 struct aux_payload *payload); 1317 1318 /******************************************************************************* 1319 * DSC Interfaces 1320 ******************************************************************************/ 1321 #include "dc_dsc.h" 1322 1323 /******************************************************************************* 1324 * Disable acc mode Interfaces 1325 ******************************************************************************/ 1326 void dc_disable_accelerated_mode(struct dc *dc); 1327 1328 #endif /* DC_INTERFACE_H_ */ 1329