1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "dml/display_mode_lib.h" 40 41 #define DC_VER "3.1.52" 42 43 #define MAX_SURFACES 3 44 #define MAX_STREAMS 6 45 #define MAX_SINKS_PER_LINK 4 46 47 48 /******************************************************************************* 49 * Display Core Interfaces 50 ******************************************************************************/ 51 struct dmcu_version { 52 unsigned int date; 53 unsigned int month; 54 unsigned int year; 55 unsigned int interface_version; 56 }; 57 58 struct dc_versions { 59 const char *dc_ver; 60 struct dmcu_version dmcu_version; 61 }; 62 63 struct dc_caps { 64 uint32_t max_streams; 65 uint32_t max_links; 66 uint32_t max_audios; 67 uint32_t max_slave_planes; 68 uint32_t max_planes; 69 uint32_t max_downscale_ratio; 70 uint32_t i2c_speed_in_khz; 71 uint32_t dmdata_alloc_size; 72 unsigned int max_cursor_size; 73 unsigned int max_video_width; 74 int linear_pitch_alignment; 75 bool dcc_const_color; 76 bool dynamic_audio; 77 bool is_apu; 78 bool dual_link_dvi; 79 bool post_blend_color_processing; 80 }; 81 82 struct dc_dcc_surface_param { 83 struct dc_size surface_size; 84 enum surface_pixel_format format; 85 enum swizzle_mode_values swizzle_mode; 86 enum dc_scan_direction scan; 87 }; 88 89 struct dc_dcc_setting { 90 unsigned int max_compressed_blk_size; 91 unsigned int max_uncompressed_blk_size; 92 bool independent_64b_blks; 93 }; 94 95 struct dc_surface_dcc_cap { 96 union { 97 struct { 98 struct dc_dcc_setting rgb; 99 } grph; 100 101 struct { 102 struct dc_dcc_setting luma; 103 struct dc_dcc_setting chroma; 104 } video; 105 }; 106 107 bool capable; 108 bool const_color_support; 109 }; 110 111 struct dc_static_screen_events { 112 bool force_trigger; 113 bool cursor_update; 114 bool surface_update; 115 bool overlay_update; 116 }; 117 118 119 /* Surface update type is used by dc_update_surfaces_and_stream 120 * The update type is determined at the very beginning of the function based 121 * on parameters passed in and decides how much programming (or updating) is 122 * going to be done during the call. 123 * 124 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 125 * logical calculations or hardware register programming. This update MUST be 126 * ISR safe on windows. Currently fast update will only be used to flip surface 127 * address. 128 * 129 * UPDATE_TYPE_MED is used for slower updates which require significant hw 130 * re-programming however do not affect bandwidth consumption or clock 131 * requirements. At present, this is the level at which front end updates 132 * that do not require us to run bw_calcs happen. These are in/out transfer func 133 * updates, viewport offset changes, recout size changes and pixel depth changes. 134 * This update can be done at ISR, but we want to minimize how often this happens. 135 * 136 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 137 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 138 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 139 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 140 * a full update. This cannot be done at ISR level and should be a rare event. 141 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 142 * underscan we don't expect to see this call at all. 143 */ 144 145 enum surface_update_type { 146 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 147 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 148 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 149 }; 150 151 /* Forward declaration*/ 152 struct dc; 153 struct dc_plane_state; 154 struct dc_state; 155 156 157 struct dc_cap_funcs { 158 bool (*get_dcc_compression_cap)(const struct dc *dc, 159 const struct dc_dcc_surface_param *input, 160 struct dc_surface_dcc_cap *output); 161 }; 162 163 struct link_training_settings; 164 165 166 /* Structure to hold configuration flags set by dm at dc creation. */ 167 struct dc_config { 168 bool gpu_vm_support; 169 bool disable_disp_pll_sharing; 170 }; 171 172 enum dcc_option { 173 DCC_ENABLE = 0, 174 DCC_DISABLE = 1, 175 DCC_HALF_REQ_DISALBE = 2, 176 }; 177 178 enum pipe_split_policy { 179 MPC_SPLIT_DYNAMIC = 0, 180 MPC_SPLIT_AVOID = 1, 181 MPC_SPLIT_AVOID_MULT_DISP = 2, 182 }; 183 184 enum wm_report_mode { 185 WM_REPORT_DEFAULT = 0, 186 WM_REPORT_OVERRIDE = 1, 187 }; 188 189 /* 190 * For any clocks that may differ per pipe 191 * only the max is stored in this structure 192 */ 193 struct dc_clocks { 194 int dispclk_khz; 195 int max_supported_dppclk_khz; 196 int dppclk_khz; 197 int dcfclk_khz; 198 int socclk_khz; 199 int dcfclk_deep_sleep_khz; 200 int fclk_khz; 201 int phyclk_khz; 202 }; 203 204 struct dc_debug { 205 bool surface_visual_confirm; 206 bool sanity_checks; 207 bool max_disp_clk; 208 bool surface_trace; 209 bool timing_trace; 210 bool clock_trace; 211 bool validation_trace; 212 bool bandwidth_calcs_trace; 213 int max_downscale_src_width; 214 215 /* stutter efficiency related */ 216 bool disable_stutter; 217 bool use_max_lb; 218 enum dcc_option disable_dcc; 219 enum pipe_split_policy pipe_split_policy; 220 bool force_single_disp_pipe_split; 221 bool voltage_align_fclk; 222 223 bool disable_dfs_bypass; 224 bool disable_dpp_power_gate; 225 bool disable_hubp_power_gate; 226 bool disable_pplib_wm_range; 227 enum wm_report_mode pplib_wm_report_mode; 228 unsigned int min_disp_clk_khz; 229 int sr_exit_time_dpm0_ns; 230 int sr_enter_plus_exit_time_dpm0_ns; 231 int sr_exit_time_ns; 232 int sr_enter_plus_exit_time_ns; 233 int urgent_latency_ns; 234 int percent_of_ideal_drambw; 235 int dram_clock_change_latency_ns; 236 bool optimized_watermark; 237 int always_scale; 238 bool disable_pplib_clock_request; 239 bool disable_clock_gate; 240 bool disable_dmcu; 241 bool disable_psr; 242 bool force_abm_enable; 243 bool disable_hbup_pg; 244 bool disable_dpp_pg; 245 bool disable_stereo_support; 246 bool vsr_support; 247 bool performance_trace; 248 bool az_endpoint_mute_only; 249 bool always_use_regamma; 250 bool p010_mpo_support; 251 bool recovery_enabled; 252 253 }; 254 struct dc_state; 255 struct resource_pool; 256 struct dce_hwseq; 257 struct dc { 258 struct dc_versions versions; 259 struct dc_caps caps; 260 struct dc_cap_funcs cap_funcs; 261 struct dc_config config; 262 struct dc_debug debug; 263 264 struct dc_context *ctx; 265 266 uint8_t link_count; 267 struct dc_link *links[MAX_PIPES * 2]; 268 269 struct dc_state *current_state; 270 struct resource_pool *res_pool; 271 272 /* Display Engine Clock levels */ 273 struct dm_pp_clock_levels sclk_lvls; 274 275 /* Inputs into BW and WM calculations. */ 276 struct bw_calcs_dceip *bw_dceip; 277 struct bw_calcs_vbios *bw_vbios; 278 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 279 struct dcn_soc_bounding_box *dcn_soc; 280 struct dcn_ip_params *dcn_ip; 281 struct display_mode_lib dml; 282 #endif 283 284 /* HW functions */ 285 struct hw_sequencer_funcs hwss; 286 struct dce_hwseq *hwseq; 287 288 /* temp store of dm_pp_display_configuration 289 * to compare to see if display config changed 290 */ 291 struct dm_pp_display_configuration prev_display_config; 292 293 bool optimized_required; 294 295 bool apply_edp_fast_boot_optimization; 296 297 /* FBC compressor */ 298 struct compressor *fbc_compressor; 299 }; 300 301 enum frame_buffer_mode { 302 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 303 FRAME_BUFFER_MODE_ZFB_ONLY, 304 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 305 } ; 306 307 struct dchub_init_data { 308 int64_t zfb_phys_addr_base; 309 int64_t zfb_mc_base_addr; 310 uint64_t zfb_size_in_byte; 311 enum frame_buffer_mode fb_mode; 312 bool dchub_initialzied; 313 bool dchub_info_valid; 314 }; 315 316 struct dc_init_data { 317 struct hw_asic_id asic_id; 318 void *driver; /* ctx */ 319 struct cgs_device *cgs_device; 320 321 int num_virtual_links; 322 /* 323 * If 'vbios_override' not NULL, it will be called instead 324 * of the real VBIOS. Intended use is Diagnostics on FPGA. 325 */ 326 struct dc_bios *vbios_override; 327 enum dce_environment dce_environment; 328 329 struct dc_config flags; 330 uint32_t log_mask; 331 }; 332 333 struct dc *dc_create(const struct dc_init_data *init_params); 334 335 void dc_destroy(struct dc **dc); 336 337 /******************************************************************************* 338 * Surface Interfaces 339 ******************************************************************************/ 340 341 enum { 342 TRANSFER_FUNC_POINTS = 1025 343 }; 344 345 struct dc_hdr_static_metadata { 346 /* display chromaticities and white point in units of 0.00001 */ 347 unsigned int chromaticity_green_x; 348 unsigned int chromaticity_green_y; 349 unsigned int chromaticity_blue_x; 350 unsigned int chromaticity_blue_y; 351 unsigned int chromaticity_red_x; 352 unsigned int chromaticity_red_y; 353 unsigned int chromaticity_white_point_x; 354 unsigned int chromaticity_white_point_y; 355 356 uint32_t min_luminance; 357 uint32_t max_luminance; 358 uint32_t maximum_content_light_level; 359 uint32_t maximum_frame_average_light_level; 360 }; 361 362 enum dc_transfer_func_type { 363 TF_TYPE_PREDEFINED, 364 TF_TYPE_DISTRIBUTED_POINTS, 365 TF_TYPE_BYPASS, 366 TF_TYPE_HWPWL 367 }; 368 369 struct dc_transfer_func_distributed_points { 370 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 371 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 372 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 373 374 uint16_t end_exponent; 375 uint16_t x_point_at_y1_red; 376 uint16_t x_point_at_y1_green; 377 uint16_t x_point_at_y1_blue; 378 }; 379 380 enum dc_transfer_func_predefined { 381 TRANSFER_FUNCTION_SRGB, 382 TRANSFER_FUNCTION_BT709, 383 TRANSFER_FUNCTION_PQ, 384 TRANSFER_FUNCTION_LINEAR, 385 TRANSFER_FUNCTION_UNITY, 386 TRANSFER_FUNCTION_HLG, 387 TRANSFER_FUNCTION_HLG12 388 }; 389 390 struct dc_transfer_func { 391 struct kref refcount; 392 enum dc_transfer_func_type type; 393 enum dc_transfer_func_predefined tf; 394 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 395 uint32_t sdr_ref_white_level; 396 struct dc_context *ctx; 397 union { 398 struct pwl_params pwl; 399 struct dc_transfer_func_distributed_points tf_pts; 400 }; 401 }; 402 403 /* 404 * This structure is filled in by dc_surface_get_status and contains 405 * the last requested address and the currently active address so the called 406 * can determine if there are any outstanding flips 407 */ 408 struct dc_plane_status { 409 struct dc_plane_address requested_address; 410 struct dc_plane_address current_address; 411 bool is_flip_pending; 412 bool is_right_eye; 413 }; 414 415 union surface_update_flags { 416 417 struct { 418 /* Medium updates */ 419 uint32_t dcc_change:1; 420 uint32_t color_space_change:1; 421 uint32_t horizontal_mirror_change:1; 422 uint32_t per_pixel_alpha_change:1; 423 uint32_t rotation_change:1; 424 uint32_t swizzle_change:1; 425 uint32_t scaling_change:1; 426 uint32_t position_change:1; 427 uint32_t in_transfer_func_change:1; 428 uint32_t input_csc_change:1; 429 uint32_t coeff_reduction_change:1; 430 uint32_t output_tf_change:1; 431 uint32_t pixel_format_change:1; 432 433 /* Full updates */ 434 uint32_t new_plane:1; 435 uint32_t bpp_change:1; 436 uint32_t gamma_change:1; 437 uint32_t bandwidth_change:1; 438 uint32_t clock_change:1; 439 uint32_t stereo_format_change:1; 440 uint32_t full_update:1; 441 } bits; 442 443 uint32_t raw; 444 }; 445 446 struct dc_plane_state { 447 struct dc_plane_address address; 448 struct dc_plane_flip_time time; 449 struct scaling_taps scaling_quality; 450 struct rect src_rect; 451 struct rect dst_rect; 452 struct rect clip_rect; 453 454 union plane_size plane_size; 455 union dc_tiling_info tiling_info; 456 457 struct dc_plane_dcc_param dcc; 458 459 struct dc_gamma *gamma_correction; 460 struct dc_transfer_func *in_transfer_func; 461 struct dc_bias_and_scale *bias_and_scale; 462 struct dc_csc_transform input_csc_color_matrix; 463 struct fixed31_32 coeff_reduction_factor; 464 uint32_t sdr_white_level; 465 466 // TODO: No longer used, remove 467 struct dc_hdr_static_metadata hdr_static_ctx; 468 469 enum dc_color_space color_space; 470 471 enum surface_pixel_format format; 472 enum dc_rotation_angle rotation; 473 enum plane_stereo_format stereo_format; 474 475 bool is_tiling_rotated; 476 bool per_pixel_alpha; 477 bool visible; 478 bool flip_immediate; 479 bool horizontal_mirror; 480 481 union surface_update_flags update_flags; 482 /* private to DC core */ 483 struct dc_plane_status status; 484 struct dc_context *ctx; 485 486 /* private to dc_surface.c */ 487 enum dc_irq_source irq_source; 488 struct kref refcount; 489 }; 490 491 struct dc_plane_info { 492 union plane_size plane_size; 493 union dc_tiling_info tiling_info; 494 struct dc_plane_dcc_param dcc; 495 enum surface_pixel_format format; 496 enum dc_rotation_angle rotation; 497 enum plane_stereo_format stereo_format; 498 enum dc_color_space color_space; 499 unsigned int sdr_white_level; 500 bool horizontal_mirror; 501 bool visible; 502 bool per_pixel_alpha; 503 bool input_csc_enabled; 504 }; 505 506 struct dc_scaling_info { 507 struct rect src_rect; 508 struct rect dst_rect; 509 struct rect clip_rect; 510 struct scaling_taps scaling_quality; 511 }; 512 513 struct dc_surface_update { 514 struct dc_plane_state *surface; 515 516 /* isr safe update parameters. null means no updates */ 517 const struct dc_flip_addrs *flip_addr; 518 const struct dc_plane_info *plane_info; 519 const struct dc_scaling_info *scaling_info; 520 521 /* following updates require alloc/sleep/spin that is not isr safe, 522 * null means no updates 523 */ 524 const struct dc_gamma *gamma; 525 const struct dc_transfer_func *in_transfer_func; 526 527 const struct dc_csc_transform *input_csc_color_matrix; 528 const struct fixed31_32 *coeff_reduction_factor; 529 }; 530 531 /* 532 * Create a new surface with default parameters; 533 */ 534 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 535 const struct dc_plane_status *dc_plane_get_status( 536 const struct dc_plane_state *plane_state); 537 538 void dc_plane_state_retain(struct dc_plane_state *plane_state); 539 void dc_plane_state_release(struct dc_plane_state *plane_state); 540 541 void dc_gamma_retain(struct dc_gamma *dc_gamma); 542 void dc_gamma_release(struct dc_gamma **dc_gamma); 543 struct dc_gamma *dc_create_gamma(void); 544 545 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 546 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 547 struct dc_transfer_func *dc_create_transfer_func(void); 548 549 /* 550 * This structure holds a surface address. There could be multiple addresses 551 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 552 * as frame durations and DCC format can also be set. 553 */ 554 struct dc_flip_addrs { 555 struct dc_plane_address address; 556 unsigned int flip_timestamp_in_us; 557 bool flip_immediate; 558 /* TODO: add flip duration for FreeSync */ 559 }; 560 561 bool dc_post_update_surfaces_to_stream( 562 struct dc *dc); 563 564 #include "dc_stream.h" 565 566 /* 567 * Structure to store surface/stream associations for validation 568 */ 569 struct dc_validation_set { 570 struct dc_stream_state *stream; 571 struct dc_plane_state *plane_states[MAX_SURFACES]; 572 uint8_t plane_count; 573 }; 574 575 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 576 577 enum dc_status dc_validate_global_state( 578 struct dc *dc, 579 struct dc_state *new_ctx); 580 581 582 void dc_resource_state_construct( 583 const struct dc *dc, 584 struct dc_state *dst_ctx); 585 586 void dc_resource_state_copy_construct( 587 const struct dc_state *src_ctx, 588 struct dc_state *dst_ctx); 589 590 void dc_resource_state_copy_construct_current( 591 const struct dc *dc, 592 struct dc_state *dst_ctx); 593 594 void dc_resource_state_destruct(struct dc_state *context); 595 596 /* 597 * TODO update to make it about validation sets 598 * Set up streams and links associated to drive sinks 599 * The streams parameter is an absolute set of all active streams. 600 * 601 * After this call: 602 * Phy, Encoder, Timing Generator are programmed and enabled. 603 * New streams are enabled with blank stream; no memory read. 604 */ 605 bool dc_commit_state(struct dc *dc, struct dc_state *context); 606 607 608 struct dc_state *dc_create_state(void); 609 void dc_retain_state(struct dc_state *context); 610 void dc_release_state(struct dc_state *context); 611 612 /******************************************************************************* 613 * Link Interfaces 614 ******************************************************************************/ 615 616 struct dpcd_caps { 617 union dpcd_rev dpcd_rev; 618 union max_lane_count max_ln_count; 619 union max_down_spread max_down_spread; 620 621 /* dongle type (DP converter, CV smart dongle) */ 622 enum display_dongle_type dongle_type; 623 /* Dongle's downstream count. */ 624 union sink_count sink_count; 625 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 626 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 627 struct dc_dongle_caps dongle_caps; 628 629 uint32_t sink_dev_id; 630 uint32_t branch_dev_id; 631 int8_t branch_dev_name[6]; 632 int8_t branch_hw_revision; 633 634 bool allow_invalid_MSA_timing_param; 635 bool panel_mode_edp; 636 bool dpcd_display_control_capable; 637 }; 638 639 #include "dc_link.h" 640 641 /******************************************************************************* 642 * Sink Interfaces - A sink corresponds to a display output device 643 ******************************************************************************/ 644 645 struct dc_container_id { 646 // 128bit GUID in binary form 647 unsigned char guid[16]; 648 // 8 byte port ID -> ELD.PortID 649 unsigned int portId[2]; 650 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 651 unsigned short manufacturerName; 652 // 2 byte product code -> ELD.ProductCode 653 unsigned short productCode; 654 }; 655 656 657 658 /* 659 * The sink structure contains EDID and other display device properties 660 */ 661 struct dc_sink { 662 enum signal_type sink_signal; 663 struct dc_edid dc_edid; /* raw edid */ 664 struct dc_edid_caps edid_caps; /* parse display caps */ 665 struct dc_container_id *dc_container_id; 666 uint32_t dongle_max_pix_clk; 667 void *priv; 668 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 669 bool converter_disable_audio; 670 671 /* private to DC core */ 672 struct dc_link *link; 673 struct dc_context *ctx; 674 675 uint32_t sink_id; 676 677 /* private to dc_sink.c */ 678 // refcount must be the last member in dc_sink, since we want the 679 // sink structure to be logically cloneable up to (but not including) 680 // refcount 681 struct kref refcount; 682 }; 683 684 void dc_sink_retain(struct dc_sink *sink); 685 void dc_sink_release(struct dc_sink *sink); 686 687 struct dc_sink_init_data { 688 enum signal_type sink_signal; 689 struct dc_link *link; 690 uint32_t dongle_max_pix_clk; 691 bool converter_disable_audio; 692 }; 693 694 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 695 696 /* Newer interfaces */ 697 struct dc_cursor { 698 struct dc_plane_address address; 699 struct dc_cursor_attributes attributes; 700 }; 701 702 703 /******************************************************************************* 704 * Interrupt interfaces 705 ******************************************************************************/ 706 enum dc_irq_source dc_interrupt_to_irq_source( 707 struct dc *dc, 708 uint32_t src_id, 709 uint32_t ext_id); 710 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 711 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 712 enum dc_irq_source dc_get_hpd_irq_source_at_index( 713 struct dc *dc, uint32_t link_index); 714 715 /******************************************************************************* 716 * Power Interfaces 717 ******************************************************************************/ 718 719 void dc_set_power_state( 720 struct dc *dc, 721 enum dc_acpi_cm_power_state power_state); 722 void dc_resume(struct dc *dc); 723 724 #endif /* DC_INTERFACE_H_ */ 725