1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 48 #define DC_VER "3.2.125" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MAX_SINKS_PER_LINK 4 54 #define MIN_VIEWPORT_SIZE 12 55 #define MAX_NUM_EDP 2 56 57 /******************************************************************************* 58 * Display Core Interfaces 59 ******************************************************************************/ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 struct dc_plane_cap { 77 enum dc_plane_type type; 78 uint32_t blends_with_above : 1; 79 uint32_t blends_with_below : 1; 80 uint32_t per_pixel_alpha : 1; 81 struct { 82 uint32_t argb8888 : 1; 83 uint32_t nv12 : 1; 84 uint32_t fp16 : 1; 85 uint32_t p010 : 1; 86 uint32_t ayuv : 1; 87 } pixel_format_support; 88 // max upscaling factor x1000 89 // upscaling factors are always >= 1 90 // for example, 1080p -> 8K is 4.0, or 4000 raw value 91 struct { 92 uint32_t argb8888; 93 uint32_t nv12; 94 uint32_t fp16; 95 } max_upscale_factor; 96 // max downscale factor x1000 97 // downscale factors are always <= 1 98 // for example, 8K -> 1080p is 0.25, or 250 raw value 99 struct { 100 uint32_t argb8888; 101 uint32_t nv12; 102 uint32_t fp16; 103 } max_downscale_factor; 104 // minimal width/height 105 uint32_t min_width; 106 uint32_t min_height; 107 }; 108 109 // Color management caps (DPP and MPC) 110 struct rom_curve_caps { 111 uint16_t srgb : 1; 112 uint16_t bt2020 : 1; 113 uint16_t gamma2_2 : 1; 114 uint16_t pq : 1; 115 uint16_t hlg : 1; 116 }; 117 118 struct dpp_color_caps { 119 uint16_t dcn_arch : 1; // all DCE generations treated the same 120 // input lut is different than most LUTs, just plain 256-entry lookup 121 uint16_t input_lut_shared : 1; // shared with DGAM 122 uint16_t icsc : 1; 123 uint16_t dgam_ram : 1; 124 uint16_t post_csc : 1; // before gamut remap 125 uint16_t gamma_corr : 1; 126 127 // hdr_mult and gamut remap always available in DPP (in that order) 128 // 3d lut implies shaper LUT, 129 // it may be shared with MPC - check MPC:shared_3d_lut flag 130 uint16_t hw_3d_lut : 1; 131 uint16_t ogam_ram : 1; // blnd gam 132 uint16_t ocsc : 1; 133 uint16_t dgam_rom_for_yuv : 1; 134 struct rom_curve_caps dgam_rom_caps; 135 struct rom_curve_caps ogam_rom_caps; 136 }; 137 138 struct mpc_color_caps { 139 uint16_t gamut_remap : 1; 140 uint16_t ogam_ram : 1; 141 uint16_t ocsc : 1; 142 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 143 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 144 145 struct rom_curve_caps ogam_rom_caps; 146 }; 147 148 struct dc_color_caps { 149 struct dpp_color_caps dpp; 150 struct mpc_color_caps mpc; 151 }; 152 153 struct dc_caps { 154 uint32_t max_streams; 155 uint32_t max_links; 156 uint32_t max_audios; 157 uint32_t max_slave_planes; 158 uint32_t max_planes; 159 uint32_t max_downscale_ratio; 160 uint32_t i2c_speed_in_khz; 161 uint32_t i2c_speed_in_khz_hdcp; 162 uint32_t dmdata_alloc_size; 163 unsigned int max_cursor_size; 164 unsigned int max_video_width; 165 unsigned int min_horizontal_blanking_period; 166 int linear_pitch_alignment; 167 bool dcc_const_color; 168 bool dynamic_audio; 169 bool is_apu; 170 bool dual_link_dvi; 171 bool post_blend_color_processing; 172 bool force_dp_tps4_for_cp2520; 173 bool disable_dp_clk_share; 174 bool psp_setup_panel_mode; 175 bool extended_aux_timeout_support; 176 bool dmcub_support; 177 uint32_t num_of_internal_disp; 178 enum dp_protocol_version max_dp_protocol_version; 179 unsigned int mall_size_per_mem_channel; 180 unsigned int mall_size_total; 181 unsigned int cursor_cache_size; 182 struct dc_plane_cap planes[MAX_PLANES]; 183 struct dc_color_caps color; 184 }; 185 186 struct dc_bug_wa { 187 bool no_connect_phy_config; 188 bool dedcn20_305_wa; 189 bool skip_clock_update; 190 bool lt_early_cr_pattern; 191 }; 192 193 struct dc_dcc_surface_param { 194 struct dc_size surface_size; 195 enum surface_pixel_format format; 196 enum swizzle_mode_values swizzle_mode; 197 enum dc_scan_direction scan; 198 }; 199 200 struct dc_dcc_setting { 201 unsigned int max_compressed_blk_size; 202 unsigned int max_uncompressed_blk_size; 203 bool independent_64b_blks; 204 #if defined(CONFIG_DRM_AMD_DC_DCN) 205 //These bitfields to be used starting with DCN 3.0 206 struct { 207 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 208 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 209 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 210 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 211 } dcc_controls; 212 #endif 213 }; 214 215 struct dc_surface_dcc_cap { 216 union { 217 struct { 218 struct dc_dcc_setting rgb; 219 } grph; 220 221 struct { 222 struct dc_dcc_setting luma; 223 struct dc_dcc_setting chroma; 224 } video; 225 }; 226 227 bool capable; 228 bool const_color_support; 229 }; 230 231 struct dc_static_screen_params { 232 struct { 233 bool force_trigger; 234 bool cursor_update; 235 bool surface_update; 236 bool overlay_update; 237 } triggers; 238 unsigned int num_frames; 239 }; 240 241 242 /* Surface update type is used by dc_update_surfaces_and_stream 243 * The update type is determined at the very beginning of the function based 244 * on parameters passed in and decides how much programming (or updating) is 245 * going to be done during the call. 246 * 247 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 248 * logical calculations or hardware register programming. This update MUST be 249 * ISR safe on windows. Currently fast update will only be used to flip surface 250 * address. 251 * 252 * UPDATE_TYPE_MED is used for slower updates which require significant hw 253 * re-programming however do not affect bandwidth consumption or clock 254 * requirements. At present, this is the level at which front end updates 255 * that do not require us to run bw_calcs happen. These are in/out transfer func 256 * updates, viewport offset changes, recout size changes and pixel depth changes. 257 * This update can be done at ISR, but we want to minimize how often this happens. 258 * 259 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 260 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 261 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 262 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 263 * a full update. This cannot be done at ISR level and should be a rare event. 264 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 265 * underscan we don't expect to see this call at all. 266 */ 267 268 enum surface_update_type { 269 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 270 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 271 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 272 }; 273 274 /* Forward declaration*/ 275 struct dc; 276 struct dc_plane_state; 277 struct dc_state; 278 279 280 struct dc_cap_funcs { 281 bool (*get_dcc_compression_cap)(const struct dc *dc, 282 const struct dc_dcc_surface_param *input, 283 struct dc_surface_dcc_cap *output); 284 }; 285 286 struct link_training_settings; 287 288 289 /* Structure to hold configuration flags set by dm at dc creation. */ 290 struct dc_config { 291 bool gpu_vm_support; 292 bool disable_disp_pll_sharing; 293 bool fbc_support; 294 bool optimize_edp_link_rate; 295 bool disable_fractional_pwm; 296 bool allow_seamless_boot_optimization; 297 bool power_down_display_on_boot; 298 bool edp_not_connected; 299 bool force_enum_edp; 300 bool forced_clocks; 301 bool allow_lttpr_non_transparent_mode; 302 bool multi_mon_pp_mclk_switch; 303 bool disable_dmcu; 304 bool enable_4to1MPC; 305 #if defined(CONFIG_DRM_AMD_DC_DCN) 306 bool clamp_min_dcfclk; 307 #endif 308 uint64_t vblank_alignment_dto_params; 309 uint8_t vblank_alignment_max_frame_time_diff; 310 bool is_asymmetric_memory; 311 bool is_single_rank_dimm; 312 }; 313 314 enum visual_confirm { 315 VISUAL_CONFIRM_DISABLE = 0, 316 VISUAL_CONFIRM_SURFACE = 1, 317 VISUAL_CONFIRM_HDR = 2, 318 VISUAL_CONFIRM_MPCTREE = 4, 319 VISUAL_CONFIRM_PSR = 5, 320 }; 321 322 enum dcc_option { 323 DCC_ENABLE = 0, 324 DCC_DISABLE = 1, 325 DCC_HALF_REQ_DISALBE = 2, 326 }; 327 328 enum pipe_split_policy { 329 MPC_SPLIT_DYNAMIC = 0, 330 MPC_SPLIT_AVOID = 1, 331 MPC_SPLIT_AVOID_MULT_DISP = 2, 332 }; 333 334 enum wm_report_mode { 335 WM_REPORT_DEFAULT = 0, 336 WM_REPORT_OVERRIDE = 1, 337 }; 338 enum dtm_pstate{ 339 dtm_level_p0 = 0,/*highest voltage*/ 340 dtm_level_p1, 341 dtm_level_p2, 342 dtm_level_p3, 343 dtm_level_p4,/*when active_display_count = 0*/ 344 }; 345 346 enum dcn_pwr_state { 347 DCN_PWR_STATE_UNKNOWN = -1, 348 DCN_PWR_STATE_MISSION_MODE = 0, 349 DCN_PWR_STATE_LOW_POWER = 3, 350 }; 351 352 /* 353 * For any clocks that may differ per pipe 354 * only the max is stored in this structure 355 */ 356 struct dc_clocks { 357 int dispclk_khz; 358 int actual_dispclk_khz; 359 int dppclk_khz; 360 int actual_dppclk_khz; 361 int disp_dpp_voltage_level_khz; 362 int dcfclk_khz; 363 int socclk_khz; 364 int dcfclk_deep_sleep_khz; 365 int fclk_khz; 366 int phyclk_khz; 367 int dramclk_khz; 368 bool p_state_change_support; 369 enum dcn_pwr_state pwr_state; 370 /* 371 * Elements below are not compared for the purposes of 372 * optimization required 373 */ 374 bool prev_p_state_change_support; 375 enum dtm_pstate dtm_level; 376 int max_supported_dppclk_khz; 377 int max_supported_dispclk_khz; 378 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 379 int bw_dispclk_khz; 380 }; 381 382 struct dc_bw_validation_profile { 383 bool enable; 384 385 unsigned long long total_ticks; 386 unsigned long long voltage_level_ticks; 387 unsigned long long watermark_ticks; 388 unsigned long long rq_dlg_ticks; 389 390 unsigned long long total_count; 391 unsigned long long skip_fast_count; 392 unsigned long long skip_pass_count; 393 unsigned long long skip_fail_count; 394 }; 395 396 #define BW_VAL_TRACE_SETUP() \ 397 unsigned long long end_tick = 0; \ 398 unsigned long long voltage_level_tick = 0; \ 399 unsigned long long watermark_tick = 0; \ 400 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 401 dm_get_timestamp(dc->ctx) : 0 402 403 #define BW_VAL_TRACE_COUNT() \ 404 if (dc->debug.bw_val_profile.enable) \ 405 dc->debug.bw_val_profile.total_count++ 406 407 #define BW_VAL_TRACE_SKIP(status) \ 408 if (dc->debug.bw_val_profile.enable) { \ 409 if (!voltage_level_tick) \ 410 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 411 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 412 } 413 414 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 415 if (dc->debug.bw_val_profile.enable) \ 416 voltage_level_tick = dm_get_timestamp(dc->ctx) 417 418 #define BW_VAL_TRACE_END_WATERMARKS() \ 419 if (dc->debug.bw_val_profile.enable) \ 420 watermark_tick = dm_get_timestamp(dc->ctx) 421 422 #define BW_VAL_TRACE_FINISH() \ 423 if (dc->debug.bw_val_profile.enable) { \ 424 end_tick = dm_get_timestamp(dc->ctx); \ 425 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 426 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 427 if (watermark_tick) { \ 428 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 429 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 430 } \ 431 } 432 433 union mem_low_power_enable_options { 434 struct { 435 bool i2c: 1; 436 bool dmcu: 1; 437 bool dscl: 1; 438 bool cm: 1; 439 bool mpc: 1; 440 bool optc: 1; 441 } bits; 442 uint32_t u32All; 443 }; 444 445 struct dc_debug_options { 446 enum visual_confirm visual_confirm; 447 bool sanity_checks; 448 bool max_disp_clk; 449 bool surface_trace; 450 bool timing_trace; 451 bool clock_trace; 452 bool validation_trace; 453 bool bandwidth_calcs_trace; 454 int max_downscale_src_width; 455 456 /* stutter efficiency related */ 457 bool disable_stutter; 458 bool use_max_lb; 459 enum dcc_option disable_dcc; 460 enum pipe_split_policy pipe_split_policy; 461 bool force_single_disp_pipe_split; 462 bool voltage_align_fclk; 463 464 bool disable_dfs_bypass; 465 bool disable_dpp_power_gate; 466 bool disable_hubp_power_gate; 467 bool disable_dsc_power_gate; 468 int dsc_min_slice_height_override; 469 int dsc_bpp_increment_div; 470 bool native422_support; 471 bool disable_pplib_wm_range; 472 enum wm_report_mode pplib_wm_report_mode; 473 unsigned int min_disp_clk_khz; 474 unsigned int min_dpp_clk_khz; 475 int sr_exit_time_dpm0_ns; 476 int sr_enter_plus_exit_time_dpm0_ns; 477 int sr_exit_time_ns; 478 int sr_enter_plus_exit_time_ns; 479 int urgent_latency_ns; 480 uint32_t underflow_assert_delay_us; 481 int percent_of_ideal_drambw; 482 int dram_clock_change_latency_ns; 483 bool optimized_watermark; 484 int always_scale; 485 bool disable_pplib_clock_request; 486 bool disable_clock_gate; 487 bool disable_mem_low_power; 488 bool disable_dmcu; 489 bool disable_psr; 490 bool force_abm_enable; 491 bool disable_stereo_support; 492 bool vsr_support; 493 bool performance_trace; 494 bool az_endpoint_mute_only; 495 bool always_use_regamma; 496 bool recovery_enabled; 497 bool avoid_vbios_exec_table; 498 bool scl_reset_length10; 499 bool hdmi20_disable; 500 bool skip_detection_link_training; 501 uint32_t edid_read_retry_times; 502 bool remove_disconnect_edp; 503 unsigned int force_odm_combine; //bit vector based on otg inst 504 #if defined(CONFIG_DRM_AMD_DC_DCN) 505 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 506 #endif 507 unsigned int force_fclk_khz; 508 bool enable_tri_buf; 509 bool dmub_offload_enabled; 510 bool dmcub_emulation; 511 #if defined(CONFIG_DRM_AMD_DC_DCN) 512 bool disable_idle_power_optimizations; 513 unsigned int mall_size_override; 514 unsigned int mall_additional_timer_percent; 515 bool mall_error_as_fatal; 516 #endif 517 bool dmub_command_table; /* for testing only */ 518 struct dc_bw_validation_profile bw_val_profile; 519 bool disable_fec; 520 bool disable_48mhz_pwrdwn; 521 /* This forces a hard min on the DCFCLK requested to SMU/PP 522 * watermarks are not affected. 523 */ 524 unsigned int force_min_dcfclk_mhz; 525 #if defined(CONFIG_DRM_AMD_DC_DCN) 526 int dwb_fi_phase; 527 #endif 528 bool disable_timing_sync; 529 bool cm_in_bypass; 530 int force_clock_mode;/*every mode change.*/ 531 532 bool disable_dram_clock_change_vactive_support; 533 bool validate_dml_output; 534 bool enable_dmcub_surface_flip; 535 bool usbc_combo_phy_reset_wa; 536 bool disable_dsc; 537 bool enable_dram_clock_change_one_display_vactive; 538 union mem_low_power_enable_options enable_mem_low_power; 539 bool force_vblank_alignment; 540 541 /* Enable dmub aux for legacy ddc */ 542 bool enable_dmub_aux_for_legacy_ddc; 543 }; 544 545 struct dc_debug_data { 546 uint32_t ltFailCount; 547 uint32_t i2cErrorCount; 548 uint32_t auxErrorCount; 549 }; 550 551 struct dc_phy_addr_space_config { 552 struct { 553 uint64_t start_addr; 554 uint64_t end_addr; 555 uint64_t fb_top; 556 uint64_t fb_offset; 557 uint64_t fb_base; 558 uint64_t agp_top; 559 uint64_t agp_bot; 560 uint64_t agp_base; 561 } system_aperture; 562 563 struct { 564 uint64_t page_table_start_addr; 565 uint64_t page_table_end_addr; 566 uint64_t page_table_base_addr; 567 } gart_config; 568 569 bool valid; 570 bool is_hvm_enabled; 571 uint64_t page_table_default_page_addr; 572 }; 573 574 struct dc_virtual_addr_space_config { 575 uint64_t page_table_base_addr; 576 uint64_t page_table_start_addr; 577 uint64_t page_table_end_addr; 578 uint32_t page_table_block_size_in_bytes; 579 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 580 }; 581 582 struct dc_bounding_box_overrides { 583 int sr_exit_time_ns; 584 int sr_enter_plus_exit_time_ns; 585 int urgent_latency_ns; 586 int percent_of_ideal_drambw; 587 int dram_clock_change_latency_ns; 588 int dummy_clock_change_latency_ns; 589 /* This forces a hard min on the DCFCLK we use 590 * for DML. Unlike the debug option for forcing 591 * DCFCLK, this override affects watermark calculations 592 */ 593 int min_dcfclk_mhz; 594 }; 595 596 struct dc_state; 597 struct resource_pool; 598 struct dce_hwseq; 599 struct gpu_info_soc_bounding_box_v1_0; 600 struct dc { 601 struct dc_versions versions; 602 struct dc_caps caps; 603 struct dc_cap_funcs cap_funcs; 604 struct dc_config config; 605 struct dc_debug_options debug; 606 struct dc_bounding_box_overrides bb_overrides; 607 struct dc_bug_wa work_arounds; 608 struct dc_context *ctx; 609 struct dc_phy_addr_space_config vm_pa_config; 610 611 uint8_t link_count; 612 struct dc_link *links[MAX_PIPES * 2]; 613 614 struct dc_state *current_state; 615 struct resource_pool *res_pool; 616 617 struct clk_mgr *clk_mgr; 618 619 /* Display Engine Clock levels */ 620 struct dm_pp_clock_levels sclk_lvls; 621 622 /* Inputs into BW and WM calculations. */ 623 struct bw_calcs_dceip *bw_dceip; 624 struct bw_calcs_vbios *bw_vbios; 625 #ifdef CONFIG_DRM_AMD_DC_DCN 626 struct dcn_soc_bounding_box *dcn_soc; 627 struct dcn_ip_params *dcn_ip; 628 struct display_mode_lib dml; 629 #endif 630 631 /* HW functions */ 632 struct hw_sequencer_funcs hwss; 633 struct dce_hwseq *hwseq; 634 635 /* Require to optimize clocks and bandwidth for added/removed planes */ 636 bool optimized_required; 637 bool wm_optimized_required; 638 #if defined(CONFIG_DRM_AMD_DC_DCN) 639 bool idle_optimizations_allowed; 640 #endif 641 642 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 643 644 /* FBC compressor */ 645 struct compressor *fbc_compressor; 646 647 struct dc_debug_data debug_data; 648 struct dpcd_vendor_signature vendor_signature; 649 650 const char *build_id; 651 struct vm_helper *vm_helper; 652 }; 653 654 enum frame_buffer_mode { 655 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 656 FRAME_BUFFER_MODE_ZFB_ONLY, 657 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 658 } ; 659 660 struct dchub_init_data { 661 int64_t zfb_phys_addr_base; 662 int64_t zfb_mc_base_addr; 663 uint64_t zfb_size_in_byte; 664 enum frame_buffer_mode fb_mode; 665 bool dchub_initialzied; 666 bool dchub_info_valid; 667 }; 668 669 struct dc_init_data { 670 struct hw_asic_id asic_id; 671 void *driver; /* ctx */ 672 struct cgs_device *cgs_device; 673 struct dc_bounding_box_overrides bb_overrides; 674 675 int num_virtual_links; 676 /* 677 * If 'vbios_override' not NULL, it will be called instead 678 * of the real VBIOS. Intended use is Diagnostics on FPGA. 679 */ 680 struct dc_bios *vbios_override; 681 enum dce_environment dce_environment; 682 683 struct dmub_offload_funcs *dmub_if; 684 struct dc_reg_helper_state *dmub_offload; 685 686 struct dc_config flags; 687 uint64_t log_mask; 688 689 struct dpcd_vendor_signature vendor_signature; 690 #if defined(CONFIG_DRM_AMD_DC_DCN) 691 bool force_smu_not_present; 692 #endif 693 }; 694 695 struct dc_callback_init { 696 #ifdef CONFIG_DRM_AMD_DC_HDCP 697 struct cp_psp cp_psp; 698 #else 699 uint8_t reserved; 700 #endif 701 }; 702 703 struct dc *dc_create(const struct dc_init_data *init_params); 704 void dc_hardware_init(struct dc *dc); 705 706 int dc_get_vmid_use_vector(struct dc *dc); 707 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 708 /* Returns the number of vmids supported */ 709 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 710 void dc_init_callbacks(struct dc *dc, 711 const struct dc_callback_init *init_params); 712 void dc_deinit_callbacks(struct dc *dc); 713 void dc_destroy(struct dc **dc); 714 715 /******************************************************************************* 716 * Surface Interfaces 717 ******************************************************************************/ 718 719 enum { 720 TRANSFER_FUNC_POINTS = 1025 721 }; 722 723 struct dc_hdr_static_metadata { 724 /* display chromaticities and white point in units of 0.00001 */ 725 unsigned int chromaticity_green_x; 726 unsigned int chromaticity_green_y; 727 unsigned int chromaticity_blue_x; 728 unsigned int chromaticity_blue_y; 729 unsigned int chromaticity_red_x; 730 unsigned int chromaticity_red_y; 731 unsigned int chromaticity_white_point_x; 732 unsigned int chromaticity_white_point_y; 733 734 uint32_t min_luminance; 735 uint32_t max_luminance; 736 uint32_t maximum_content_light_level; 737 uint32_t maximum_frame_average_light_level; 738 }; 739 740 enum dc_transfer_func_type { 741 TF_TYPE_PREDEFINED, 742 TF_TYPE_DISTRIBUTED_POINTS, 743 TF_TYPE_BYPASS, 744 TF_TYPE_HWPWL 745 }; 746 747 struct dc_transfer_func_distributed_points { 748 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 749 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 750 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 751 752 uint16_t end_exponent; 753 uint16_t x_point_at_y1_red; 754 uint16_t x_point_at_y1_green; 755 uint16_t x_point_at_y1_blue; 756 }; 757 758 enum dc_transfer_func_predefined { 759 TRANSFER_FUNCTION_SRGB, 760 TRANSFER_FUNCTION_BT709, 761 TRANSFER_FUNCTION_PQ, 762 TRANSFER_FUNCTION_LINEAR, 763 TRANSFER_FUNCTION_UNITY, 764 TRANSFER_FUNCTION_HLG, 765 TRANSFER_FUNCTION_HLG12, 766 TRANSFER_FUNCTION_GAMMA22, 767 TRANSFER_FUNCTION_GAMMA24, 768 TRANSFER_FUNCTION_GAMMA26 769 }; 770 771 772 struct dc_transfer_func { 773 struct kref refcount; 774 enum dc_transfer_func_type type; 775 enum dc_transfer_func_predefined tf; 776 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 777 uint32_t sdr_ref_white_level; 778 union { 779 struct pwl_params pwl; 780 struct dc_transfer_func_distributed_points tf_pts; 781 }; 782 }; 783 784 785 union dc_3dlut_state { 786 struct { 787 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 788 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 789 uint32_t rmu_mux_num:3; /*index of mux to use*/ 790 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 791 uint32_t mpc_rmu1_mux:4; 792 uint32_t mpc_rmu2_mux:4; 793 uint32_t reserved:15; 794 } bits; 795 uint32_t raw; 796 }; 797 798 799 struct dc_3dlut { 800 struct kref refcount; 801 struct tetrahedral_params lut_3d; 802 struct fixed31_32 hdr_multiplier; 803 union dc_3dlut_state state; 804 }; 805 /* 806 * This structure is filled in by dc_surface_get_status and contains 807 * the last requested address and the currently active address so the called 808 * can determine if there are any outstanding flips 809 */ 810 struct dc_plane_status { 811 struct dc_plane_address requested_address; 812 struct dc_plane_address current_address; 813 bool is_flip_pending; 814 bool is_right_eye; 815 }; 816 817 union surface_update_flags { 818 819 struct { 820 uint32_t addr_update:1; 821 /* Medium updates */ 822 uint32_t dcc_change:1; 823 uint32_t color_space_change:1; 824 uint32_t horizontal_mirror_change:1; 825 uint32_t per_pixel_alpha_change:1; 826 uint32_t global_alpha_change:1; 827 uint32_t hdr_mult:1; 828 uint32_t rotation_change:1; 829 uint32_t swizzle_change:1; 830 uint32_t scaling_change:1; 831 uint32_t position_change:1; 832 uint32_t in_transfer_func_change:1; 833 uint32_t input_csc_change:1; 834 uint32_t coeff_reduction_change:1; 835 uint32_t output_tf_change:1; 836 uint32_t pixel_format_change:1; 837 uint32_t plane_size_change:1; 838 uint32_t gamut_remap_change:1; 839 840 /* Full updates */ 841 uint32_t new_plane:1; 842 uint32_t bpp_change:1; 843 uint32_t gamma_change:1; 844 uint32_t bandwidth_change:1; 845 uint32_t clock_change:1; 846 uint32_t stereo_format_change:1; 847 uint32_t full_update:1; 848 } bits; 849 850 uint32_t raw; 851 }; 852 853 struct dc_plane_state { 854 struct dc_plane_address address; 855 struct dc_plane_flip_time time; 856 bool triplebuffer_flips; 857 struct scaling_taps scaling_quality; 858 struct rect src_rect; 859 struct rect dst_rect; 860 struct rect clip_rect; 861 862 struct plane_size plane_size; 863 union dc_tiling_info tiling_info; 864 865 struct dc_plane_dcc_param dcc; 866 867 struct dc_gamma *gamma_correction; 868 struct dc_transfer_func *in_transfer_func; 869 struct dc_bias_and_scale *bias_and_scale; 870 struct dc_csc_transform input_csc_color_matrix; 871 struct fixed31_32 coeff_reduction_factor; 872 struct fixed31_32 hdr_mult; 873 struct colorspace_transform gamut_remap_matrix; 874 875 // TODO: No longer used, remove 876 struct dc_hdr_static_metadata hdr_static_ctx; 877 878 enum dc_color_space color_space; 879 880 struct dc_3dlut *lut3d_func; 881 struct dc_transfer_func *in_shaper_func; 882 struct dc_transfer_func *blend_tf; 883 884 #if defined(CONFIG_DRM_AMD_DC_DCN) 885 struct dc_transfer_func *gamcor_tf; 886 #endif 887 enum surface_pixel_format format; 888 enum dc_rotation_angle rotation; 889 enum plane_stereo_format stereo_format; 890 891 bool is_tiling_rotated; 892 bool per_pixel_alpha; 893 bool global_alpha; 894 int global_alpha_value; 895 bool visible; 896 bool flip_immediate; 897 bool horizontal_mirror; 898 int layer_index; 899 900 union surface_update_flags update_flags; 901 /* private to DC core */ 902 struct dc_plane_status status; 903 struct dc_context *ctx; 904 905 /* HACK: Workaround for forcing full reprogramming under some conditions */ 906 bool force_full_update; 907 908 /* private to dc_surface.c */ 909 enum dc_irq_source irq_source; 910 struct kref refcount; 911 }; 912 913 struct dc_plane_info { 914 struct plane_size plane_size; 915 union dc_tiling_info tiling_info; 916 struct dc_plane_dcc_param dcc; 917 enum surface_pixel_format format; 918 enum dc_rotation_angle rotation; 919 enum plane_stereo_format stereo_format; 920 enum dc_color_space color_space; 921 bool horizontal_mirror; 922 bool visible; 923 bool per_pixel_alpha; 924 bool global_alpha; 925 int global_alpha_value; 926 bool input_csc_enabled; 927 int layer_index; 928 }; 929 930 struct dc_scaling_info { 931 struct rect src_rect; 932 struct rect dst_rect; 933 struct rect clip_rect; 934 struct scaling_taps scaling_quality; 935 }; 936 937 struct dc_surface_update { 938 struct dc_plane_state *surface; 939 940 /* isr safe update parameters. null means no updates */ 941 const struct dc_flip_addrs *flip_addr; 942 const struct dc_plane_info *plane_info; 943 const struct dc_scaling_info *scaling_info; 944 struct fixed31_32 hdr_mult; 945 /* following updates require alloc/sleep/spin that is not isr safe, 946 * null means no updates 947 */ 948 const struct dc_gamma *gamma; 949 const struct dc_transfer_func *in_transfer_func; 950 951 const struct dc_csc_transform *input_csc_color_matrix; 952 const struct fixed31_32 *coeff_reduction_factor; 953 const struct dc_transfer_func *func_shaper; 954 const struct dc_3dlut *lut3d_func; 955 const struct dc_transfer_func *blend_tf; 956 const struct colorspace_transform *gamut_remap_matrix; 957 }; 958 959 /* 960 * Create a new surface with default parameters; 961 */ 962 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 963 const struct dc_plane_status *dc_plane_get_status( 964 const struct dc_plane_state *plane_state); 965 966 void dc_plane_state_retain(struct dc_plane_state *plane_state); 967 void dc_plane_state_release(struct dc_plane_state *plane_state); 968 969 void dc_gamma_retain(struct dc_gamma *dc_gamma); 970 void dc_gamma_release(struct dc_gamma **dc_gamma); 971 struct dc_gamma *dc_create_gamma(void); 972 973 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 974 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 975 struct dc_transfer_func *dc_create_transfer_func(void); 976 977 struct dc_3dlut *dc_create_3dlut_func(void); 978 void dc_3dlut_func_release(struct dc_3dlut *lut); 979 void dc_3dlut_func_retain(struct dc_3dlut *lut); 980 /* 981 * This structure holds a surface address. There could be multiple addresses 982 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 983 * as frame durations and DCC format can also be set. 984 */ 985 struct dc_flip_addrs { 986 struct dc_plane_address address; 987 unsigned int flip_timestamp_in_us; 988 bool flip_immediate; 989 /* TODO: add flip duration for FreeSync */ 990 bool triplebuffer_flips; 991 }; 992 993 void dc_post_update_surfaces_to_stream( 994 struct dc *dc); 995 996 #include "dc_stream.h" 997 998 /* 999 * Structure to store surface/stream associations for validation 1000 */ 1001 struct dc_validation_set { 1002 struct dc_stream_state *stream; 1003 struct dc_plane_state *plane_states[MAX_SURFACES]; 1004 uint8_t plane_count; 1005 }; 1006 1007 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1008 const struct dc_sink *sink, 1009 struct dc_crtc_timing *crtc_timing); 1010 1011 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1012 1013 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1014 1015 bool dc_set_generic_gpio_for_stereo(bool enable, 1016 struct gpio_service *gpio_service); 1017 1018 /* 1019 * fast_validate: we return after determining if we can support the new state, 1020 * but before we populate the programming info 1021 */ 1022 enum dc_status dc_validate_global_state( 1023 struct dc *dc, 1024 struct dc_state *new_ctx, 1025 bool fast_validate); 1026 1027 1028 void dc_resource_state_construct( 1029 const struct dc *dc, 1030 struct dc_state *dst_ctx); 1031 1032 #if defined(CONFIG_DRM_AMD_DC_DCN) 1033 bool dc_acquire_release_mpc_3dlut( 1034 struct dc *dc, bool acquire, 1035 struct dc_stream_state *stream, 1036 struct dc_3dlut **lut, 1037 struct dc_transfer_func **shaper); 1038 #endif 1039 1040 void dc_resource_state_copy_construct( 1041 const struct dc_state *src_ctx, 1042 struct dc_state *dst_ctx); 1043 1044 void dc_resource_state_copy_construct_current( 1045 const struct dc *dc, 1046 struct dc_state *dst_ctx); 1047 1048 void dc_resource_state_destruct(struct dc_state *context); 1049 1050 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1051 1052 /* 1053 * TODO update to make it about validation sets 1054 * Set up streams and links associated to drive sinks 1055 * The streams parameter is an absolute set of all active streams. 1056 * 1057 * After this call: 1058 * Phy, Encoder, Timing Generator are programmed and enabled. 1059 * New streams are enabled with blank stream; no memory read. 1060 */ 1061 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1062 1063 void dc_power_down_on_boot(struct dc *dc); 1064 1065 struct dc_state *dc_create_state(struct dc *dc); 1066 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1067 void dc_retain_state(struct dc_state *context); 1068 void dc_release_state(struct dc_state *context); 1069 1070 /******************************************************************************* 1071 * Link Interfaces 1072 ******************************************************************************/ 1073 1074 struct dpcd_caps { 1075 union dpcd_rev dpcd_rev; 1076 union max_lane_count max_ln_count; 1077 union max_down_spread max_down_spread; 1078 union dprx_feature dprx_feature; 1079 1080 /* valid only for eDP v1.4 or higher*/ 1081 uint8_t edp_supported_link_rates_count; 1082 enum dc_link_rate edp_supported_link_rates[8]; 1083 1084 /* dongle type (DP converter, CV smart dongle) */ 1085 enum display_dongle_type dongle_type; 1086 /* branch device or sink device */ 1087 bool is_branch_dev; 1088 /* Dongle's downstream count. */ 1089 union sink_count sink_count; 1090 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1091 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1092 struct dc_dongle_caps dongle_caps; 1093 1094 uint32_t sink_dev_id; 1095 int8_t sink_dev_id_str[6]; 1096 int8_t sink_hw_revision; 1097 int8_t sink_fw_revision[2]; 1098 1099 uint32_t branch_dev_id; 1100 int8_t branch_dev_name[6]; 1101 int8_t branch_hw_revision; 1102 int8_t branch_fw_revision[2]; 1103 1104 bool allow_invalid_MSA_timing_param; 1105 bool panel_mode_edp; 1106 bool dpcd_display_control_capable; 1107 bool ext_receiver_cap_field_present; 1108 bool dynamic_backlight_capable_edp; 1109 union dpcd_fec_capability fec_cap; 1110 struct dpcd_dsc_capabilities dsc_caps; 1111 struct dc_lttpr_caps lttpr_caps; 1112 struct psr_caps psr_caps; 1113 1114 }; 1115 1116 union dpcd_sink_ext_caps { 1117 struct { 1118 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1119 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1120 */ 1121 uint8_t sdr_aux_backlight_control : 1; 1122 uint8_t hdr_aux_backlight_control : 1; 1123 uint8_t reserved_1 : 2; 1124 uint8_t oled : 1; 1125 uint8_t reserved : 3; 1126 } bits; 1127 uint8_t raw; 1128 }; 1129 1130 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1131 union hdcp_rx_caps { 1132 struct { 1133 uint8_t version; 1134 uint8_t reserved; 1135 struct { 1136 uint8_t repeater : 1; 1137 uint8_t hdcp_capable : 1; 1138 uint8_t reserved : 6; 1139 } byte0; 1140 } fields; 1141 uint8_t raw[3]; 1142 }; 1143 1144 union hdcp_bcaps { 1145 struct { 1146 uint8_t HDCP_CAPABLE:1; 1147 uint8_t REPEATER:1; 1148 uint8_t RESERVED:6; 1149 } bits; 1150 uint8_t raw; 1151 }; 1152 1153 struct hdcp_caps { 1154 union hdcp_rx_caps rx_caps; 1155 union hdcp_bcaps bcaps; 1156 }; 1157 #endif 1158 1159 #include "dc_link.h" 1160 1161 #if defined(CONFIG_DRM_AMD_DC_DCN) 1162 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1163 1164 #endif 1165 /******************************************************************************* 1166 * Sink Interfaces - A sink corresponds to a display output device 1167 ******************************************************************************/ 1168 1169 struct dc_container_id { 1170 // 128bit GUID in binary form 1171 unsigned char guid[16]; 1172 // 8 byte port ID -> ELD.PortID 1173 unsigned int portId[2]; 1174 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1175 unsigned short manufacturerName; 1176 // 2 byte product code -> ELD.ProductCode 1177 unsigned short productCode; 1178 }; 1179 1180 1181 struct dc_sink_dsc_caps { 1182 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1183 // 'false' if they are sink's DSC caps 1184 bool is_virtual_dpcd_dsc; 1185 struct dsc_dec_dpcd_caps dsc_dec_caps; 1186 }; 1187 1188 struct dc_sink_fec_caps { 1189 bool is_rx_fec_supported; 1190 bool is_topology_fec_supported; 1191 }; 1192 1193 /* 1194 * The sink structure contains EDID and other display device properties 1195 */ 1196 struct dc_sink { 1197 enum signal_type sink_signal; 1198 struct dc_edid dc_edid; /* raw edid */ 1199 struct dc_edid_caps edid_caps; /* parse display caps */ 1200 struct dc_container_id *dc_container_id; 1201 uint32_t dongle_max_pix_clk; 1202 void *priv; 1203 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1204 bool converter_disable_audio; 1205 1206 struct dc_sink_dsc_caps dsc_caps; 1207 struct dc_sink_fec_caps fec_caps; 1208 1209 bool is_vsc_sdp_colorimetry_supported; 1210 1211 /* private to DC core */ 1212 struct dc_link *link; 1213 struct dc_context *ctx; 1214 1215 uint32_t sink_id; 1216 1217 /* private to dc_sink.c */ 1218 // refcount must be the last member in dc_sink, since we want the 1219 // sink structure to be logically cloneable up to (but not including) 1220 // refcount 1221 struct kref refcount; 1222 }; 1223 1224 void dc_sink_retain(struct dc_sink *sink); 1225 void dc_sink_release(struct dc_sink *sink); 1226 1227 struct dc_sink_init_data { 1228 enum signal_type sink_signal; 1229 struct dc_link *link; 1230 uint32_t dongle_max_pix_clk; 1231 bool converter_disable_audio; 1232 }; 1233 1234 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1235 1236 /* Newer interfaces */ 1237 struct dc_cursor { 1238 struct dc_plane_address address; 1239 struct dc_cursor_attributes attributes; 1240 }; 1241 1242 1243 /******************************************************************************* 1244 * Interrupt interfaces 1245 ******************************************************************************/ 1246 enum dc_irq_source dc_interrupt_to_irq_source( 1247 struct dc *dc, 1248 uint32_t src_id, 1249 uint32_t ext_id); 1250 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1251 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1252 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1253 struct dc *dc, uint32_t link_index); 1254 1255 /******************************************************************************* 1256 * Power Interfaces 1257 ******************************************************************************/ 1258 1259 void dc_set_power_state( 1260 struct dc *dc, 1261 enum dc_acpi_cm_power_state power_state); 1262 void dc_resume(struct dc *dc); 1263 1264 void dc_power_down_on_boot(struct dc *dc); 1265 1266 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1267 /* 1268 * HDCP Interfaces 1269 */ 1270 enum hdcp_message_status dc_process_hdcp_msg( 1271 enum signal_type signal, 1272 struct dc_link *link, 1273 struct hdcp_protection_message *message_info); 1274 #endif 1275 bool dc_is_dmcu_initialized(struct dc *dc); 1276 1277 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1278 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1279 #if defined(CONFIG_DRM_AMD_DC_DCN) 1280 1281 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1282 struct dc_cursor_attributes *cursor_attr); 1283 1284 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1285 1286 /* 1287 * blank all streams, and set min and max memory clock to 1288 * lowest and highest DPM level, respectively 1289 */ 1290 void dc_unlock_memory_clock_frequency(struct dc *dc); 1291 1292 /* 1293 * set min memory clock to the min required for current mode, 1294 * max to maxDPM, and unblank streams 1295 */ 1296 void dc_lock_memory_clock_frequency(struct dc *dc); 1297 1298 /* cleanup on driver unload */ 1299 void dc_hardware_release(struct dc *dc); 1300 1301 #endif 1302 1303 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1304 1305 bool dc_enable_dmub_notifications(struct dc *dc); 1306 1307 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1308 uint32_t link_index, 1309 struct aux_payload *payload); 1310 1311 /******************************************************************************* 1312 * DSC Interfaces 1313 ******************************************************************************/ 1314 #include "dc_dsc.h" 1315 #endif /* DC_INTERFACE_H_ */ 1316