1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.48" 43 44 #define MAX_SURFACES 3 45 #define MAX_PLANES 6 46 #define MAX_STREAMS 6 47 #define MAX_SINKS_PER_LINK 4 48 49 /******************************************************************************* 50 * Display Core Interfaces 51 ******************************************************************************/ 52 struct dc_versions { 53 const char *dc_ver; 54 struct dmcu_version dmcu_version; 55 }; 56 57 enum dc_plane_type { 58 DC_PLANE_TYPE_INVALID, 59 DC_PLANE_TYPE_DCE_RGB, 60 DC_PLANE_TYPE_DCE_UNDERLAY, 61 DC_PLANE_TYPE_DCN_UNIVERSAL, 62 }; 63 64 struct dc_plane_cap { 65 enum dc_plane_type type; 66 uint32_t blends_with_above : 1; 67 uint32_t blends_with_below : 1; 68 uint32_t per_pixel_alpha : 1; 69 struct { 70 uint32_t argb8888 : 1; 71 uint32_t nv12 : 1; 72 uint32_t fp16 : 1; 73 uint32_t p010 : 1; 74 uint32_t ayuv : 1; 75 } pixel_format_support; 76 // max upscaling factor x1000 77 // upscaling factors are always >= 1 78 // for example, 1080p -> 8K is 4.0, or 4000 raw value 79 struct { 80 uint32_t argb8888; 81 uint32_t nv12; 82 uint32_t fp16; 83 } max_upscale_factor; 84 // max downscale factor x1000 85 // downscale factors are always <= 1 86 // for example, 8K -> 1080p is 0.25, or 250 raw value 87 struct { 88 uint32_t argb8888; 89 uint32_t nv12; 90 uint32_t fp16; 91 } max_downscale_factor; 92 }; 93 94 struct dc_caps { 95 uint32_t max_streams; 96 uint32_t max_links; 97 uint32_t max_audios; 98 uint32_t max_slave_planes; 99 uint32_t max_planes; 100 uint32_t max_downscale_ratio; 101 uint32_t i2c_speed_in_khz; 102 uint32_t dmdata_alloc_size; 103 unsigned int max_cursor_size; 104 unsigned int max_video_width; 105 int linear_pitch_alignment; 106 bool dcc_const_color; 107 bool dynamic_audio; 108 bool is_apu; 109 bool dual_link_dvi; 110 bool post_blend_color_processing; 111 bool force_dp_tps4_for_cp2520; 112 bool disable_dp_clk_share; 113 bool psp_setup_panel_mode; 114 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 115 bool hw_3d_lut; 116 #endif 117 struct dc_plane_cap planes[MAX_PLANES]; 118 }; 119 120 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 121 struct dc_bug_wa { 122 bool no_connect_phy_config; 123 bool dedcn20_305_wa; 124 bool skip_clock_update; 125 }; 126 #endif 127 128 struct dc_dcc_surface_param { 129 struct dc_size surface_size; 130 enum surface_pixel_format format; 131 enum swizzle_mode_values swizzle_mode; 132 enum dc_scan_direction scan; 133 }; 134 135 struct dc_dcc_setting { 136 unsigned int max_compressed_blk_size; 137 unsigned int max_uncompressed_blk_size; 138 bool independent_64b_blks; 139 }; 140 141 struct dc_surface_dcc_cap { 142 union { 143 struct { 144 struct dc_dcc_setting rgb; 145 } grph; 146 147 struct { 148 struct dc_dcc_setting luma; 149 struct dc_dcc_setting chroma; 150 } video; 151 }; 152 153 bool capable; 154 bool const_color_support; 155 }; 156 157 struct dc_static_screen_events { 158 bool force_trigger; 159 bool cursor_update; 160 bool surface_update; 161 bool overlay_update; 162 }; 163 164 165 /* Surface update type is used by dc_update_surfaces_and_stream 166 * The update type is determined at the very beginning of the function based 167 * on parameters passed in and decides how much programming (or updating) is 168 * going to be done during the call. 169 * 170 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 171 * logical calculations or hardware register programming. This update MUST be 172 * ISR safe on windows. Currently fast update will only be used to flip surface 173 * address. 174 * 175 * UPDATE_TYPE_MED is used for slower updates which require significant hw 176 * re-programming however do not affect bandwidth consumption or clock 177 * requirements. At present, this is the level at which front end updates 178 * that do not require us to run bw_calcs happen. These are in/out transfer func 179 * updates, viewport offset changes, recout size changes and pixel depth changes. 180 * This update can be done at ISR, but we want to minimize how often this happens. 181 * 182 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 183 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 184 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 185 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 186 * a full update. This cannot be done at ISR level and should be a rare event. 187 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 188 * underscan we don't expect to see this call at all. 189 */ 190 191 enum surface_update_type { 192 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 193 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 194 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 195 }; 196 197 /* Forward declaration*/ 198 struct dc; 199 struct dc_plane_state; 200 struct dc_state; 201 202 203 struct dc_cap_funcs { 204 bool (*get_dcc_compression_cap)(const struct dc *dc, 205 const struct dc_dcc_surface_param *input, 206 struct dc_surface_dcc_cap *output); 207 }; 208 209 struct link_training_settings; 210 211 212 /* Structure to hold configuration flags set by dm at dc creation. */ 213 struct dc_config { 214 bool gpu_vm_support; 215 bool disable_disp_pll_sharing; 216 bool fbc_support; 217 bool optimize_edp_link_rate; 218 bool disable_fractional_pwm; 219 bool allow_seamless_boot_optimization; 220 bool power_down_display_on_boot; 221 bool edp_not_connected; 222 bool forced_clocks; 223 bool multi_mon_pp_mclk_switch; 224 }; 225 226 enum visual_confirm { 227 VISUAL_CONFIRM_DISABLE = 0, 228 VISUAL_CONFIRM_SURFACE = 1, 229 VISUAL_CONFIRM_HDR = 2, 230 }; 231 232 enum dcc_option { 233 DCC_ENABLE = 0, 234 DCC_DISABLE = 1, 235 DCC_HALF_REQ_DISALBE = 2, 236 }; 237 238 enum pipe_split_policy { 239 MPC_SPLIT_DYNAMIC = 0, 240 MPC_SPLIT_AVOID = 1, 241 MPC_SPLIT_AVOID_MULT_DISP = 2, 242 }; 243 244 enum wm_report_mode { 245 WM_REPORT_DEFAULT = 0, 246 WM_REPORT_OVERRIDE = 1, 247 }; 248 249 /* 250 * For any clocks that may differ per pipe 251 * only the max is stored in this structure 252 */ 253 struct dc_clocks { 254 int dispclk_khz; 255 int max_supported_dppclk_khz; 256 int max_supported_dispclk_khz; 257 int dppclk_khz; 258 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 259 int bw_dispclk_khz; 260 int dcfclk_khz; 261 int socclk_khz; 262 int dcfclk_deep_sleep_khz; 263 int fclk_khz; 264 int phyclk_khz; 265 int dramclk_khz; 266 bool p_state_change_support; 267 268 /* 269 * Elements below are not compared for the purposes of 270 * optimization required 271 */ 272 bool prev_p_state_change_support; 273 }; 274 275 struct dc_bw_validation_profile { 276 bool enable; 277 278 unsigned long long total_ticks; 279 unsigned long long voltage_level_ticks; 280 unsigned long long watermark_ticks; 281 unsigned long long rq_dlg_ticks; 282 283 unsigned long long total_count; 284 unsigned long long skip_fast_count; 285 unsigned long long skip_pass_count; 286 unsigned long long skip_fail_count; 287 }; 288 289 #define BW_VAL_TRACE_SETUP() \ 290 unsigned long long end_tick = 0; \ 291 unsigned long long voltage_level_tick = 0; \ 292 unsigned long long watermark_tick = 0; \ 293 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 294 dm_get_timestamp(dc->ctx) : 0 295 296 #define BW_VAL_TRACE_COUNT() \ 297 if (dc->debug.bw_val_profile.enable) \ 298 dc->debug.bw_val_profile.total_count++ 299 300 #define BW_VAL_TRACE_SKIP(status) \ 301 if (dc->debug.bw_val_profile.enable) { \ 302 if (!voltage_level_tick) \ 303 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 304 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 305 } 306 307 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 308 if (dc->debug.bw_val_profile.enable) \ 309 voltage_level_tick = dm_get_timestamp(dc->ctx) 310 311 #define BW_VAL_TRACE_END_WATERMARKS() \ 312 if (dc->debug.bw_val_profile.enable) \ 313 watermark_tick = dm_get_timestamp(dc->ctx) 314 315 #define BW_VAL_TRACE_FINISH() \ 316 if (dc->debug.bw_val_profile.enable) { \ 317 end_tick = dm_get_timestamp(dc->ctx); \ 318 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 319 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 320 if (watermark_tick) { \ 321 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 322 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 323 } \ 324 } 325 326 struct dc_debug_options { 327 enum visual_confirm visual_confirm; 328 bool sanity_checks; 329 bool max_disp_clk; 330 bool surface_trace; 331 bool timing_trace; 332 bool clock_trace; 333 bool validation_trace; 334 bool bandwidth_calcs_trace; 335 int max_downscale_src_width; 336 337 /* stutter efficiency related */ 338 bool disable_stutter; 339 bool use_max_lb; 340 enum dcc_option disable_dcc; 341 enum pipe_split_policy pipe_split_policy; 342 bool force_single_disp_pipe_split; 343 bool voltage_align_fclk; 344 345 bool disable_dfs_bypass; 346 bool disable_dpp_power_gate; 347 bool disable_hubp_power_gate; 348 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 349 bool disable_dsc_power_gate; 350 #endif 351 bool disable_pplib_wm_range; 352 enum wm_report_mode pplib_wm_report_mode; 353 unsigned int min_disp_clk_khz; 354 unsigned int min_dpp_clk_khz; 355 int sr_exit_time_dpm0_ns; 356 int sr_enter_plus_exit_time_dpm0_ns; 357 int sr_exit_time_ns; 358 int sr_enter_plus_exit_time_ns; 359 int urgent_latency_ns; 360 uint32_t underflow_assert_delay_us; 361 int percent_of_ideal_drambw; 362 int dram_clock_change_latency_ns; 363 bool optimized_watermark; 364 int always_scale; 365 bool disable_pplib_clock_request; 366 bool disable_clock_gate; 367 bool disable_dmcu; 368 bool disable_psr; 369 bool force_abm_enable; 370 bool disable_stereo_support; 371 bool vsr_support; 372 bool performance_trace; 373 bool az_endpoint_mute_only; 374 bool always_use_regamma; 375 bool p010_mpo_support; 376 bool recovery_enabled; 377 bool avoid_vbios_exec_table; 378 bool scl_reset_length10; 379 bool hdmi20_disable; 380 bool skip_detection_link_training; 381 bool remove_disconnect_edp; 382 unsigned int force_odm_combine; //bit vector based on otg inst 383 unsigned int force_fclk_khz; 384 bool disable_tri_buf; 385 struct dc_bw_validation_profile bw_val_profile; 386 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 387 bool disable_fec; 388 #endif 389 /* This forces a hard min on the DCFCLK requested to SMU/PP 390 * watermarks are not affected. 391 */ 392 unsigned int force_min_dcfclk_mhz; 393 bool disable_timing_sync; 394 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 395 bool cm_in_bypass; 396 #endif 397 int force_clock_mode;/*every mode change.*/ 398 }; 399 400 struct dc_debug_data { 401 uint32_t ltFailCount; 402 uint32_t i2cErrorCount; 403 uint32_t auxErrorCount; 404 }; 405 406 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 407 struct dc_phy_addr_space_config { 408 struct { 409 uint64_t start_addr; 410 uint64_t end_addr; 411 uint64_t fb_top; 412 uint64_t fb_offset; 413 uint64_t fb_base; 414 uint64_t agp_top; 415 uint64_t agp_bot; 416 uint64_t agp_base; 417 } system_aperture; 418 419 struct { 420 uint64_t page_table_start_addr; 421 uint64_t page_table_end_addr; 422 uint64_t page_table_base_addr; 423 } gart_config; 424 425 bool valid; 426 uint64_t page_table_default_page_addr; 427 }; 428 429 struct dc_virtual_addr_space_config { 430 uint64_t page_table_base_addr; 431 uint64_t page_table_start_addr; 432 uint64_t page_table_end_addr; 433 uint32_t page_table_block_size_in_bytes; 434 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 435 }; 436 #endif 437 438 struct dc_bounding_box_overrides { 439 int sr_exit_time_ns; 440 int sr_enter_plus_exit_time_ns; 441 int urgent_latency_ns; 442 int percent_of_ideal_drambw; 443 int dram_clock_change_latency_ns; 444 /* This forces a hard min on the DCFCLK we use 445 * for DML. Unlike the debug option for forcing 446 * DCFCLK, this override affects watermark calculations 447 */ 448 int min_dcfclk_mhz; 449 }; 450 451 struct dc_state; 452 struct resource_pool; 453 struct dce_hwseq; 454 struct gpu_info_soc_bounding_box_v1_0; 455 struct dc { 456 struct dc_versions versions; 457 struct dc_caps caps; 458 struct dc_cap_funcs cap_funcs; 459 struct dc_config config; 460 struct dc_debug_options debug; 461 struct dc_bounding_box_overrides bb_overrides; 462 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 463 struct dc_bug_wa work_arounds; 464 #endif 465 struct dc_context *ctx; 466 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 467 struct dc_phy_addr_space_config vm_pa_config; 468 #endif 469 470 uint8_t link_count; 471 struct dc_link *links[MAX_PIPES * 2]; 472 473 struct dc_state *current_state; 474 struct resource_pool *res_pool; 475 476 struct clk_mgr *clk_mgr; 477 478 /* Display Engine Clock levels */ 479 struct dm_pp_clock_levels sclk_lvls; 480 481 /* Inputs into BW and WM calculations. */ 482 struct bw_calcs_dceip *bw_dceip; 483 struct bw_calcs_vbios *bw_vbios; 484 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 485 struct dcn_soc_bounding_box *dcn_soc; 486 struct dcn_ip_params *dcn_ip; 487 struct display_mode_lib dml; 488 #endif 489 490 /* HW functions */ 491 struct hw_sequencer_funcs hwss; 492 struct dce_hwseq *hwseq; 493 494 /* Require to optimize clocks and bandwidth for added/removed planes */ 495 bool optimized_required; 496 497 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 498 bool optimize_seamless_boot; 499 500 /* FBC compressor */ 501 struct compressor *fbc_compressor; 502 503 struct dc_debug_data debug_data; 504 505 const char *build_id; 506 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 507 struct vm_helper *vm_helper; 508 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 509 #endif 510 }; 511 512 enum frame_buffer_mode { 513 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 514 FRAME_BUFFER_MODE_ZFB_ONLY, 515 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 516 } ; 517 518 struct dchub_init_data { 519 int64_t zfb_phys_addr_base; 520 int64_t zfb_mc_base_addr; 521 uint64_t zfb_size_in_byte; 522 enum frame_buffer_mode fb_mode; 523 bool dchub_initialzied; 524 bool dchub_info_valid; 525 }; 526 527 struct dc_init_data { 528 struct hw_asic_id asic_id; 529 void *driver; /* ctx */ 530 struct cgs_device *cgs_device; 531 struct dc_bounding_box_overrides bb_overrides; 532 533 int num_virtual_links; 534 /* 535 * If 'vbios_override' not NULL, it will be called instead 536 * of the real VBIOS. Intended use is Diagnostics on FPGA. 537 */ 538 struct dc_bios *vbios_override; 539 enum dce_environment dce_environment; 540 541 struct dc_config flags; 542 uint32_t log_mask; 543 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 544 /** 545 * gpu_info FW provided soc bounding box struct or 0 if not 546 * available in FW 547 */ 548 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 549 #endif 550 }; 551 552 struct dc_callback_init { 553 uint8_t reserved; 554 }; 555 556 struct dc *dc_create(const struct dc_init_data *init_params); 557 int dc_get_vmid_use_vector(struct dc *dc); 558 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 559 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 560 /* Returns the number of vmids supported */ 561 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 562 #endif 563 void dc_init_callbacks(struct dc *dc, 564 const struct dc_callback_init *init_params); 565 void dc_destroy(struct dc **dc); 566 567 /******************************************************************************* 568 * Surface Interfaces 569 ******************************************************************************/ 570 571 enum { 572 TRANSFER_FUNC_POINTS = 1025 573 }; 574 575 struct dc_hdr_static_metadata { 576 /* display chromaticities and white point in units of 0.00001 */ 577 unsigned int chromaticity_green_x; 578 unsigned int chromaticity_green_y; 579 unsigned int chromaticity_blue_x; 580 unsigned int chromaticity_blue_y; 581 unsigned int chromaticity_red_x; 582 unsigned int chromaticity_red_y; 583 unsigned int chromaticity_white_point_x; 584 unsigned int chromaticity_white_point_y; 585 586 uint32_t min_luminance; 587 uint32_t max_luminance; 588 uint32_t maximum_content_light_level; 589 uint32_t maximum_frame_average_light_level; 590 }; 591 592 enum dc_transfer_func_type { 593 TF_TYPE_PREDEFINED, 594 TF_TYPE_DISTRIBUTED_POINTS, 595 TF_TYPE_BYPASS, 596 TF_TYPE_HWPWL 597 }; 598 599 struct dc_transfer_func_distributed_points { 600 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 601 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 602 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 603 604 uint16_t end_exponent; 605 uint16_t x_point_at_y1_red; 606 uint16_t x_point_at_y1_green; 607 uint16_t x_point_at_y1_blue; 608 }; 609 610 enum dc_transfer_func_predefined { 611 TRANSFER_FUNCTION_SRGB, 612 TRANSFER_FUNCTION_BT709, 613 TRANSFER_FUNCTION_PQ, 614 TRANSFER_FUNCTION_LINEAR, 615 TRANSFER_FUNCTION_UNITY, 616 TRANSFER_FUNCTION_HLG, 617 TRANSFER_FUNCTION_HLG12, 618 TRANSFER_FUNCTION_GAMMA22, 619 TRANSFER_FUNCTION_GAMMA24, 620 TRANSFER_FUNCTION_GAMMA26 621 }; 622 623 624 struct dc_transfer_func { 625 struct kref refcount; 626 enum dc_transfer_func_type type; 627 enum dc_transfer_func_predefined tf; 628 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 629 uint32_t sdr_ref_white_level; 630 struct dc_context *ctx; 631 union { 632 struct pwl_params pwl; 633 struct dc_transfer_func_distributed_points tf_pts; 634 }; 635 }; 636 637 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 638 639 union dc_3dlut_state { 640 struct { 641 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 642 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 643 uint32_t rmu_mux_num:3; /*index of mux to use*/ 644 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 645 uint32_t mpc_rmu1_mux:4; 646 uint32_t mpc_rmu2_mux:4; 647 uint32_t reserved:15; 648 } bits; 649 uint32_t raw; 650 }; 651 652 653 struct dc_3dlut { 654 struct kref refcount; 655 struct tetrahedral_params lut_3d; 656 uint32_t hdr_multiplier; 657 bool initialized; /*remove after diag fix*/ 658 union dc_3dlut_state state; 659 struct dc_context *ctx; 660 }; 661 #endif 662 /* 663 * This structure is filled in by dc_surface_get_status and contains 664 * the last requested address and the currently active address so the called 665 * can determine if there are any outstanding flips 666 */ 667 struct dc_plane_status { 668 struct dc_plane_address requested_address; 669 struct dc_plane_address current_address; 670 bool is_flip_pending; 671 bool is_right_eye; 672 }; 673 674 union surface_update_flags { 675 676 struct { 677 uint32_t addr_update:1; 678 /* Medium updates */ 679 uint32_t dcc_change:1; 680 uint32_t color_space_change:1; 681 uint32_t horizontal_mirror_change:1; 682 uint32_t per_pixel_alpha_change:1; 683 uint32_t global_alpha_change:1; 684 uint32_t sdr_white_level:1; 685 uint32_t rotation_change:1; 686 uint32_t swizzle_change:1; 687 uint32_t scaling_change:1; 688 uint32_t position_change:1; 689 uint32_t in_transfer_func_change:1; 690 uint32_t input_csc_change:1; 691 uint32_t coeff_reduction_change:1; 692 uint32_t output_tf_change:1; 693 uint32_t pixel_format_change:1; 694 uint32_t plane_size_change:1; 695 696 /* Full updates */ 697 uint32_t new_plane:1; 698 uint32_t bpp_change:1; 699 uint32_t gamma_change:1; 700 uint32_t bandwidth_change:1; 701 uint32_t clock_change:1; 702 uint32_t stereo_format_change:1; 703 uint32_t full_update:1; 704 } bits; 705 706 uint32_t raw; 707 }; 708 709 struct dc_plane_state { 710 struct dc_plane_address address; 711 struct dc_plane_flip_time time; 712 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 713 bool triplebuffer_flips; 714 #endif 715 struct scaling_taps scaling_quality; 716 struct rect src_rect; 717 struct rect dst_rect; 718 struct rect clip_rect; 719 720 struct plane_size plane_size; 721 union dc_tiling_info tiling_info; 722 723 struct dc_plane_dcc_param dcc; 724 725 struct dc_gamma *gamma_correction; 726 struct dc_transfer_func *in_transfer_func; 727 struct dc_bias_and_scale *bias_and_scale; 728 struct dc_csc_transform input_csc_color_matrix; 729 struct fixed31_32 coeff_reduction_factor; 730 uint32_t sdr_white_level; 731 732 // TODO: No longer used, remove 733 struct dc_hdr_static_metadata hdr_static_ctx; 734 735 enum dc_color_space color_space; 736 737 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 738 struct dc_3dlut *lut3d_func; 739 struct dc_transfer_func *in_shaper_func; 740 struct dc_transfer_func *blend_tf; 741 #endif 742 743 enum surface_pixel_format format; 744 enum dc_rotation_angle rotation; 745 enum plane_stereo_format stereo_format; 746 747 bool is_tiling_rotated; 748 bool per_pixel_alpha; 749 bool global_alpha; 750 int global_alpha_value; 751 bool visible; 752 bool flip_immediate; 753 bool horizontal_mirror; 754 int layer_index; 755 756 union surface_update_flags update_flags; 757 /* private to DC core */ 758 struct dc_plane_status status; 759 struct dc_context *ctx; 760 761 /* HACK: Workaround for forcing full reprogramming under some conditions */ 762 bool force_full_update; 763 764 /* private to dc_surface.c */ 765 enum dc_irq_source irq_source; 766 struct kref refcount; 767 }; 768 769 struct dc_plane_info { 770 struct plane_size plane_size; 771 union dc_tiling_info tiling_info; 772 struct dc_plane_dcc_param dcc; 773 enum surface_pixel_format format; 774 enum dc_rotation_angle rotation; 775 enum plane_stereo_format stereo_format; 776 enum dc_color_space color_space; 777 unsigned int sdr_white_level; 778 bool horizontal_mirror; 779 bool visible; 780 bool per_pixel_alpha; 781 bool global_alpha; 782 int global_alpha_value; 783 bool input_csc_enabled; 784 int layer_index; 785 }; 786 787 struct dc_scaling_info { 788 struct rect src_rect; 789 struct rect dst_rect; 790 struct rect clip_rect; 791 struct scaling_taps scaling_quality; 792 }; 793 794 struct dc_surface_update { 795 struct dc_plane_state *surface; 796 797 /* isr safe update parameters. null means no updates */ 798 const struct dc_flip_addrs *flip_addr; 799 const struct dc_plane_info *plane_info; 800 const struct dc_scaling_info *scaling_info; 801 802 /* following updates require alloc/sleep/spin that is not isr safe, 803 * null means no updates 804 */ 805 const struct dc_gamma *gamma; 806 const struct dc_transfer_func *in_transfer_func; 807 808 const struct dc_csc_transform *input_csc_color_matrix; 809 const struct fixed31_32 *coeff_reduction_factor; 810 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 811 const struct dc_transfer_func *func_shaper; 812 const struct dc_3dlut *lut3d_func; 813 const struct dc_transfer_func *blend_tf; 814 #endif 815 }; 816 817 /* 818 * Create a new surface with default parameters; 819 */ 820 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 821 const struct dc_plane_status *dc_plane_get_status( 822 const struct dc_plane_state *plane_state); 823 824 void dc_plane_state_retain(struct dc_plane_state *plane_state); 825 void dc_plane_state_release(struct dc_plane_state *plane_state); 826 827 void dc_gamma_retain(struct dc_gamma *dc_gamma); 828 void dc_gamma_release(struct dc_gamma **dc_gamma); 829 struct dc_gamma *dc_create_gamma(void); 830 831 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 832 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 833 struct dc_transfer_func *dc_create_transfer_func(void); 834 835 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 836 struct dc_3dlut *dc_create_3dlut_func(void); 837 void dc_3dlut_func_release(struct dc_3dlut *lut); 838 void dc_3dlut_func_retain(struct dc_3dlut *lut); 839 #endif 840 /* 841 * This structure holds a surface address. There could be multiple addresses 842 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 843 * as frame durations and DCC format can also be set. 844 */ 845 struct dc_flip_addrs { 846 struct dc_plane_address address; 847 unsigned int flip_timestamp_in_us; 848 bool flip_immediate; 849 /* TODO: add flip duration for FreeSync */ 850 }; 851 852 bool dc_post_update_surfaces_to_stream( 853 struct dc *dc); 854 855 #include "dc_stream.h" 856 857 /* 858 * Structure to store surface/stream associations for validation 859 */ 860 struct dc_validation_set { 861 struct dc_stream_state *stream; 862 struct dc_plane_state *plane_states[MAX_SURFACES]; 863 uint8_t plane_count; 864 }; 865 866 bool dc_validate_seamless_boot_timing(const struct dc *dc, 867 const struct dc_sink *sink, 868 struct dc_crtc_timing *crtc_timing); 869 870 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 871 872 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 873 874 bool dc_set_generic_gpio_for_stereo(bool enable, 875 struct gpio_service *gpio_service); 876 877 /* 878 * fast_validate: we return after determining if we can support the new state, 879 * but before we populate the programming info 880 */ 881 enum dc_status dc_validate_global_state( 882 struct dc *dc, 883 struct dc_state *new_ctx, 884 bool fast_validate); 885 886 887 void dc_resource_state_construct( 888 const struct dc *dc, 889 struct dc_state *dst_ctx); 890 891 void dc_resource_state_copy_construct( 892 const struct dc_state *src_ctx, 893 struct dc_state *dst_ctx); 894 895 void dc_resource_state_copy_construct_current( 896 const struct dc *dc, 897 struct dc_state *dst_ctx); 898 899 void dc_resource_state_destruct(struct dc_state *context); 900 901 /* 902 * TODO update to make it about validation sets 903 * Set up streams and links associated to drive sinks 904 * The streams parameter is an absolute set of all active streams. 905 * 906 * After this call: 907 * Phy, Encoder, Timing Generator are programmed and enabled. 908 * New streams are enabled with blank stream; no memory read. 909 */ 910 bool dc_commit_state(struct dc *dc, struct dc_state *context); 911 912 913 struct dc_state *dc_create_state(struct dc *dc); 914 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 915 void dc_retain_state(struct dc_state *context); 916 void dc_release_state(struct dc_state *context); 917 918 /******************************************************************************* 919 * Link Interfaces 920 ******************************************************************************/ 921 922 struct dpcd_caps { 923 union dpcd_rev dpcd_rev; 924 union max_lane_count max_ln_count; 925 union max_down_spread max_down_spread; 926 union dprx_feature dprx_feature; 927 928 /* valid only for eDP v1.4 or higher*/ 929 uint8_t edp_supported_link_rates_count; 930 enum dc_link_rate edp_supported_link_rates[8]; 931 932 /* dongle type (DP converter, CV smart dongle) */ 933 enum display_dongle_type dongle_type; 934 /* branch device or sink device */ 935 bool is_branch_dev; 936 /* Dongle's downstream count. */ 937 union sink_count sink_count; 938 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 939 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 940 struct dc_dongle_caps dongle_caps; 941 942 uint32_t sink_dev_id; 943 int8_t sink_dev_id_str[6]; 944 int8_t sink_hw_revision; 945 int8_t sink_fw_revision[2]; 946 947 uint32_t branch_dev_id; 948 int8_t branch_dev_name[6]; 949 int8_t branch_hw_revision; 950 int8_t branch_fw_revision[2]; 951 952 bool allow_invalid_MSA_timing_param; 953 bool panel_mode_edp; 954 bool dpcd_display_control_capable; 955 bool ext_receiver_cap_field_present; 956 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 957 union dpcd_fec_capability fec_cap; 958 struct dpcd_dsc_capabilities dsc_caps; 959 #endif 960 }; 961 962 #include "dc_link.h" 963 964 /******************************************************************************* 965 * Sink Interfaces - A sink corresponds to a display output device 966 ******************************************************************************/ 967 968 struct dc_container_id { 969 // 128bit GUID in binary form 970 unsigned char guid[16]; 971 // 8 byte port ID -> ELD.PortID 972 unsigned int portId[2]; 973 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 974 unsigned short manufacturerName; 975 // 2 byte product code -> ELD.ProductCode 976 unsigned short productCode; 977 }; 978 979 980 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 981 struct dc_sink_dsc_caps { 982 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 983 // 'false' if they are sink's DSC caps 984 bool is_virtual_dpcd_dsc; 985 struct dsc_dec_dpcd_caps dsc_dec_caps; 986 }; 987 #endif 988 989 /* 990 * The sink structure contains EDID and other display device properties 991 */ 992 struct dc_sink { 993 enum signal_type sink_signal; 994 struct dc_edid dc_edid; /* raw edid */ 995 struct dc_edid_caps edid_caps; /* parse display caps */ 996 struct dc_container_id *dc_container_id; 997 uint32_t dongle_max_pix_clk; 998 void *priv; 999 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1000 bool converter_disable_audio; 1001 1002 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1003 struct dc_sink_dsc_caps sink_dsc_caps; 1004 #endif 1005 1006 /* private to DC core */ 1007 struct dc_link *link; 1008 struct dc_context *ctx; 1009 1010 uint32_t sink_id; 1011 1012 /* private to dc_sink.c */ 1013 // refcount must be the last member in dc_sink, since we want the 1014 // sink structure to be logically cloneable up to (but not including) 1015 // refcount 1016 struct kref refcount; 1017 }; 1018 1019 void dc_sink_retain(struct dc_sink *sink); 1020 void dc_sink_release(struct dc_sink *sink); 1021 1022 struct dc_sink_init_data { 1023 enum signal_type sink_signal; 1024 struct dc_link *link; 1025 uint32_t dongle_max_pix_clk; 1026 bool converter_disable_audio; 1027 }; 1028 1029 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1030 1031 /* Newer interfaces */ 1032 struct dc_cursor { 1033 struct dc_plane_address address; 1034 struct dc_cursor_attributes attributes; 1035 }; 1036 1037 1038 /******************************************************************************* 1039 * Interrupt interfaces 1040 ******************************************************************************/ 1041 enum dc_irq_source dc_interrupt_to_irq_source( 1042 struct dc *dc, 1043 uint32_t src_id, 1044 uint32_t ext_id); 1045 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1046 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1047 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1048 struct dc *dc, uint32_t link_index); 1049 1050 /******************************************************************************* 1051 * Power Interfaces 1052 ******************************************************************************/ 1053 1054 void dc_set_power_state( 1055 struct dc *dc, 1056 enum dc_acpi_cm_power_state power_state); 1057 void dc_resume(struct dc *dc); 1058 unsigned int dc_get_current_backlight_pwm(struct dc *dc); 1059 unsigned int dc_get_target_backlight_pwm(struct dc *dc); 1060 1061 bool dc_is_dmcu_initialized(struct dc *dc); 1062 1063 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1064 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1065 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) 1066 /******************************************************************************* 1067 * DSC Interfaces 1068 ******************************************************************************/ 1069 #include "dc_dsc.h" 1070 #endif 1071 #endif /* DC_INTERFACE_H_ */ 1072