1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "dml/display_mode_lib.h" 40 41 #define DC_VER "3.1.44" 42 43 #define MAX_SURFACES 3 44 #define MAX_STREAMS 6 45 #define MAX_SINKS_PER_LINK 4 46 47 48 /******************************************************************************* 49 * Display Core Interfaces 50 ******************************************************************************/ 51 struct dmcu_version { 52 unsigned int date; 53 unsigned int month; 54 unsigned int year; 55 unsigned int interface_version; 56 }; 57 58 struct dc_versions { 59 const char *dc_ver; 60 struct dmcu_version dmcu_version; 61 }; 62 63 struct dc_caps { 64 uint32_t max_streams; 65 uint32_t max_links; 66 uint32_t max_audios; 67 uint32_t max_slave_planes; 68 uint32_t max_planes; 69 uint32_t max_downscale_ratio; 70 uint32_t i2c_speed_in_khz; 71 unsigned int max_cursor_size; 72 unsigned int max_video_width; 73 int linear_pitch_alignment; 74 bool dcc_const_color; 75 bool dynamic_audio; 76 bool is_apu; 77 bool dual_link_dvi; 78 bool post_blend_color_processing; 79 bool force_dp_tps4_for_cp2520; 80 }; 81 82 struct dc_dcc_surface_param { 83 struct dc_size surface_size; 84 enum surface_pixel_format format; 85 enum swizzle_mode_values swizzle_mode; 86 enum dc_scan_direction scan; 87 }; 88 89 struct dc_dcc_setting { 90 unsigned int max_compressed_blk_size; 91 unsigned int max_uncompressed_blk_size; 92 bool independent_64b_blks; 93 }; 94 95 struct dc_surface_dcc_cap { 96 union { 97 struct { 98 struct dc_dcc_setting rgb; 99 } grph; 100 101 struct { 102 struct dc_dcc_setting luma; 103 struct dc_dcc_setting chroma; 104 } video; 105 }; 106 107 bool capable; 108 bool const_color_support; 109 }; 110 111 struct dc_static_screen_events { 112 bool force_trigger; 113 bool cursor_update; 114 bool surface_update; 115 bool overlay_update; 116 }; 117 118 119 /* Surface update type is used by dc_update_surfaces_and_stream 120 * The update type is determined at the very beginning of the function based 121 * on parameters passed in and decides how much programming (or updating) is 122 * going to be done during the call. 123 * 124 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 125 * logical calculations or hardware register programming. This update MUST be 126 * ISR safe on windows. Currently fast update will only be used to flip surface 127 * address. 128 * 129 * UPDATE_TYPE_MED is used for slower updates which require significant hw 130 * re-programming however do not affect bandwidth consumption or clock 131 * requirements. At present, this is the level at which front end updates 132 * that do not require us to run bw_calcs happen. These are in/out transfer func 133 * updates, viewport offset changes, recout size changes and pixel depth changes. 134 * This update can be done at ISR, but we want to minimize how often this happens. 135 * 136 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 137 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 138 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 139 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 140 * a full update. This cannot be done at ISR level and should be a rare event. 141 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 142 * underscan we don't expect to see this call at all. 143 */ 144 145 enum surface_update_type { 146 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 147 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 148 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 149 }; 150 151 /* Forward declaration*/ 152 struct dc; 153 struct dc_plane_state; 154 struct dc_state; 155 156 157 struct dc_cap_funcs { 158 bool (*get_dcc_compression_cap)(const struct dc *dc, 159 const struct dc_dcc_surface_param *input, 160 struct dc_surface_dcc_cap *output); 161 }; 162 163 struct link_training_settings; 164 165 166 /* Structure to hold configuration flags set by dm at dc creation. */ 167 struct dc_config { 168 bool gpu_vm_support; 169 bool disable_disp_pll_sharing; 170 }; 171 172 enum dcc_option { 173 DCC_ENABLE = 0, 174 DCC_DISABLE = 1, 175 DCC_HALF_REQ_DISALBE = 2, 176 }; 177 178 enum pipe_split_policy { 179 MPC_SPLIT_DYNAMIC = 0, 180 MPC_SPLIT_AVOID = 1, 181 MPC_SPLIT_AVOID_MULT_DISP = 2, 182 }; 183 184 enum wm_report_mode { 185 WM_REPORT_DEFAULT = 0, 186 WM_REPORT_OVERRIDE = 1, 187 }; 188 189 struct dc_clocks { 190 int dispclk_khz; 191 int max_supported_dppclk_khz; 192 int dppclk_khz; 193 int dcfclk_khz; 194 int socclk_khz; 195 int dcfclk_deep_sleep_khz; 196 int fclk_khz; 197 }; 198 199 struct dc_debug { 200 bool surface_visual_confirm; 201 bool sanity_checks; 202 bool max_disp_clk; 203 bool surface_trace; 204 bool timing_trace; 205 bool clock_trace; 206 bool validation_trace; 207 bool bandwidth_calcs_trace; 208 int max_downscale_src_width; 209 210 /* stutter efficiency related */ 211 bool disable_stutter; 212 bool use_max_lb; 213 enum dcc_option disable_dcc; 214 enum pipe_split_policy pipe_split_policy; 215 bool force_single_disp_pipe_split; 216 bool voltage_align_fclk; 217 218 bool disable_dfs_bypass; 219 bool disable_dpp_power_gate; 220 bool disable_hubp_power_gate; 221 bool disable_pplib_wm_range; 222 enum wm_report_mode pplib_wm_report_mode; 223 unsigned int min_disp_clk_khz; 224 int sr_exit_time_dpm0_ns; 225 int sr_enter_plus_exit_time_dpm0_ns; 226 int sr_exit_time_ns; 227 int sr_enter_plus_exit_time_ns; 228 int urgent_latency_ns; 229 int percent_of_ideal_drambw; 230 int dram_clock_change_latency_ns; 231 int always_scale; 232 bool disable_pplib_clock_request; 233 bool disable_clock_gate; 234 bool disable_dmcu; 235 bool disable_psr; 236 bool force_abm_enable; 237 bool disable_hbup_pg; 238 bool disable_dpp_pg; 239 bool disable_stereo_support; 240 bool vsr_support; 241 bool performance_trace; 242 bool az_endpoint_mute_only; 243 bool always_use_regamma; 244 bool p010_mpo_support; 245 bool recovery_enabled; 246 247 }; 248 struct dc_state; 249 struct resource_pool; 250 struct dce_hwseq; 251 struct dc { 252 struct dc_versions versions; 253 struct dc_caps caps; 254 struct dc_cap_funcs cap_funcs; 255 struct dc_config config; 256 struct dc_debug debug; 257 258 struct dc_context *ctx; 259 260 uint8_t link_count; 261 struct dc_link *links[MAX_PIPES * 2]; 262 263 struct dc_state *current_state; 264 struct resource_pool *res_pool; 265 266 /* Display Engine Clock levels */ 267 struct dm_pp_clock_levels sclk_lvls; 268 269 /* Inputs into BW and WM calculations. */ 270 struct bw_calcs_dceip *bw_dceip; 271 struct bw_calcs_vbios *bw_vbios; 272 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 273 struct dcn_soc_bounding_box *dcn_soc; 274 struct dcn_ip_params *dcn_ip; 275 struct display_mode_lib dml; 276 #endif 277 278 /* HW functions */ 279 struct hw_sequencer_funcs hwss; 280 struct dce_hwseq *hwseq; 281 282 /* temp store of dm_pp_display_configuration 283 * to compare to see if display config changed 284 */ 285 struct dm_pp_display_configuration prev_display_config; 286 287 bool optimized_required; 288 289 bool apply_edp_fast_boot_optimization; 290 291 /* FBC compressor */ 292 #if defined(CONFIG_DRM_AMD_DC_FBC) 293 struct compressor *fbc_compressor; 294 #endif 295 }; 296 297 enum frame_buffer_mode { 298 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 299 FRAME_BUFFER_MODE_ZFB_ONLY, 300 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 301 } ; 302 303 struct dchub_init_data { 304 int64_t zfb_phys_addr_base; 305 int64_t zfb_mc_base_addr; 306 uint64_t zfb_size_in_byte; 307 enum frame_buffer_mode fb_mode; 308 bool dchub_initialzied; 309 bool dchub_info_valid; 310 }; 311 312 struct dc_init_data { 313 struct hw_asic_id asic_id; 314 void *driver; /* ctx */ 315 struct cgs_device *cgs_device; 316 317 int num_virtual_links; 318 /* 319 * If 'vbios_override' not NULL, it will be called instead 320 * of the real VBIOS. Intended use is Diagnostics on FPGA. 321 */ 322 struct dc_bios *vbios_override; 323 enum dce_environment dce_environment; 324 325 struct dc_config flags; 326 uint32_t log_mask; 327 }; 328 329 struct dc *dc_create(const struct dc_init_data *init_params); 330 331 void dc_destroy(struct dc **dc); 332 333 /******************************************************************************* 334 * Surface Interfaces 335 ******************************************************************************/ 336 337 enum { 338 TRANSFER_FUNC_POINTS = 1025 339 }; 340 341 struct dc_hdr_static_metadata { 342 /* display chromaticities and white point in units of 0.00001 */ 343 unsigned int chromaticity_green_x; 344 unsigned int chromaticity_green_y; 345 unsigned int chromaticity_blue_x; 346 unsigned int chromaticity_blue_y; 347 unsigned int chromaticity_red_x; 348 unsigned int chromaticity_red_y; 349 unsigned int chromaticity_white_point_x; 350 unsigned int chromaticity_white_point_y; 351 352 uint32_t min_luminance; 353 uint32_t max_luminance; 354 uint32_t maximum_content_light_level; 355 uint32_t maximum_frame_average_light_level; 356 }; 357 358 enum dc_transfer_func_type { 359 TF_TYPE_PREDEFINED, 360 TF_TYPE_DISTRIBUTED_POINTS, 361 TF_TYPE_BYPASS, 362 }; 363 364 struct dc_transfer_func_distributed_points { 365 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 366 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 367 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 368 369 uint16_t end_exponent; 370 uint16_t x_point_at_y1_red; 371 uint16_t x_point_at_y1_green; 372 uint16_t x_point_at_y1_blue; 373 }; 374 375 enum dc_transfer_func_predefined { 376 TRANSFER_FUNCTION_SRGB, 377 TRANSFER_FUNCTION_BT709, 378 TRANSFER_FUNCTION_PQ, 379 TRANSFER_FUNCTION_LINEAR, 380 TRANSFER_FUNCTION_UNITY, 381 }; 382 383 struct dc_transfer_func { 384 struct kref refcount; 385 struct dc_transfer_func_distributed_points tf_pts; 386 enum dc_transfer_func_type type; 387 enum dc_transfer_func_predefined tf; 388 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 389 uint32_t sdr_ref_white_level; 390 struct dc_context *ctx; 391 }; 392 393 /* 394 * This structure is filled in by dc_surface_get_status and contains 395 * the last requested address and the currently active address so the called 396 * can determine if there are any outstanding flips 397 */ 398 struct dc_plane_status { 399 struct dc_plane_address requested_address; 400 struct dc_plane_address current_address; 401 bool is_flip_pending; 402 bool is_right_eye; 403 }; 404 405 union surface_update_flags { 406 407 struct { 408 /* Medium updates */ 409 uint32_t dcc_change:1; 410 uint32_t color_space_change:1; 411 uint32_t horizontal_mirror_change:1; 412 uint32_t per_pixel_alpha_change:1; 413 uint32_t rotation_change:1; 414 uint32_t swizzle_change:1; 415 uint32_t scaling_change:1; 416 uint32_t position_change:1; 417 uint32_t in_transfer_func_change:1; 418 uint32_t input_csc_change:1; 419 uint32_t coeff_reduction_change:1; 420 uint32_t output_tf_change:1; 421 uint32_t pixel_format_change:1; 422 423 /* Full updates */ 424 uint32_t new_plane:1; 425 uint32_t bpp_change:1; 426 uint32_t gamma_change:1; 427 uint32_t bandwidth_change:1; 428 uint32_t clock_change:1; 429 uint32_t stereo_format_change:1; 430 uint32_t full_update:1; 431 } bits; 432 433 uint32_t raw; 434 }; 435 436 struct dc_plane_state { 437 struct dc_plane_address address; 438 struct dc_plane_flip_time time; 439 struct scaling_taps scaling_quality; 440 struct rect src_rect; 441 struct rect dst_rect; 442 struct rect clip_rect; 443 444 union plane_size plane_size; 445 union dc_tiling_info tiling_info; 446 447 struct dc_plane_dcc_param dcc; 448 449 struct dc_gamma *gamma_correction; 450 struct dc_transfer_func *in_transfer_func; 451 struct dc_bias_and_scale *bias_and_scale; 452 struct dc_csc_transform input_csc_color_matrix; 453 struct fixed31_32 coeff_reduction_factor; 454 uint32_t sdr_white_level; 455 456 // TODO: No longer used, remove 457 struct dc_hdr_static_metadata hdr_static_ctx; 458 459 enum dc_color_space color_space; 460 461 enum surface_pixel_format format; 462 enum dc_rotation_angle rotation; 463 enum plane_stereo_format stereo_format; 464 465 bool is_tiling_rotated; 466 bool per_pixel_alpha; 467 bool visible; 468 bool flip_immediate; 469 bool horizontal_mirror; 470 471 union surface_update_flags update_flags; 472 /* private to DC core */ 473 struct dc_plane_status status; 474 struct dc_context *ctx; 475 476 /* private to dc_surface.c */ 477 enum dc_irq_source irq_source; 478 struct kref refcount; 479 }; 480 481 struct dc_plane_info { 482 union plane_size plane_size; 483 union dc_tiling_info tiling_info; 484 struct dc_plane_dcc_param dcc; 485 enum surface_pixel_format format; 486 enum dc_rotation_angle rotation; 487 enum plane_stereo_format stereo_format; 488 enum dc_color_space color_space; 489 unsigned int sdr_white_level; 490 bool horizontal_mirror; 491 bool visible; 492 bool per_pixel_alpha; 493 bool input_csc_enabled; 494 }; 495 496 struct dc_scaling_info { 497 struct rect src_rect; 498 struct rect dst_rect; 499 struct rect clip_rect; 500 struct scaling_taps scaling_quality; 501 }; 502 503 struct dc_surface_update { 504 struct dc_plane_state *surface; 505 506 /* isr safe update parameters. null means no updates */ 507 const struct dc_flip_addrs *flip_addr; 508 const struct dc_plane_info *plane_info; 509 const struct dc_scaling_info *scaling_info; 510 511 /* following updates require alloc/sleep/spin that is not isr safe, 512 * null means no updates 513 */ 514 const struct dc_gamma *gamma; 515 const struct dc_transfer_func *in_transfer_func; 516 517 const struct dc_csc_transform *input_csc_color_matrix; 518 const struct fixed31_32 *coeff_reduction_factor; 519 }; 520 521 /* 522 * Create a new surface with default parameters; 523 */ 524 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 525 const struct dc_plane_status *dc_plane_get_status( 526 const struct dc_plane_state *plane_state); 527 528 void dc_plane_state_retain(struct dc_plane_state *plane_state); 529 void dc_plane_state_release(struct dc_plane_state *plane_state); 530 531 void dc_gamma_retain(struct dc_gamma *dc_gamma); 532 void dc_gamma_release(struct dc_gamma **dc_gamma); 533 struct dc_gamma *dc_create_gamma(void); 534 535 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 536 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 537 struct dc_transfer_func *dc_create_transfer_func(void); 538 539 /* 540 * This structure holds a surface address. There could be multiple addresses 541 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 542 * as frame durations and DCC format can also be set. 543 */ 544 struct dc_flip_addrs { 545 struct dc_plane_address address; 546 unsigned int flip_timestamp_in_us; 547 bool flip_immediate; 548 /* TODO: add flip duration for FreeSync */ 549 }; 550 551 bool dc_post_update_surfaces_to_stream( 552 struct dc *dc); 553 554 #include "dc_stream.h" 555 556 /* 557 * Structure to store surface/stream associations for validation 558 */ 559 struct dc_validation_set { 560 struct dc_stream_state *stream; 561 struct dc_plane_state *plane_states[MAX_SURFACES]; 562 uint8_t plane_count; 563 }; 564 565 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 566 567 enum dc_status dc_validate_global_state( 568 struct dc *dc, 569 struct dc_state *new_ctx); 570 571 572 void dc_resource_state_construct( 573 const struct dc *dc, 574 struct dc_state *dst_ctx); 575 576 void dc_resource_state_copy_construct( 577 const struct dc_state *src_ctx, 578 struct dc_state *dst_ctx); 579 580 void dc_resource_state_copy_construct_current( 581 const struct dc *dc, 582 struct dc_state *dst_ctx); 583 584 void dc_resource_state_destruct(struct dc_state *context); 585 586 /* 587 * TODO update to make it about validation sets 588 * Set up streams and links associated to drive sinks 589 * The streams parameter is an absolute set of all active streams. 590 * 591 * After this call: 592 * Phy, Encoder, Timing Generator are programmed and enabled. 593 * New streams are enabled with blank stream; no memory read. 594 */ 595 bool dc_commit_state(struct dc *dc, struct dc_state *context); 596 597 598 struct dc_state *dc_create_state(void); 599 void dc_retain_state(struct dc_state *context); 600 void dc_release_state(struct dc_state *context); 601 602 /******************************************************************************* 603 * Link Interfaces 604 ******************************************************************************/ 605 606 struct dpcd_caps { 607 union dpcd_rev dpcd_rev; 608 union max_lane_count max_ln_count; 609 union max_down_spread max_down_spread; 610 611 /* dongle type (DP converter, CV smart dongle) */ 612 enum display_dongle_type dongle_type; 613 /* Dongle's downstream count. */ 614 union sink_count sink_count; 615 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 616 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 617 struct dc_dongle_caps dongle_caps; 618 619 uint32_t sink_dev_id; 620 uint32_t branch_dev_id; 621 int8_t branch_dev_name[6]; 622 int8_t branch_hw_revision; 623 624 bool allow_invalid_MSA_timing_param; 625 bool panel_mode_edp; 626 bool dpcd_display_control_capable; 627 }; 628 629 #include "dc_link.h" 630 631 /******************************************************************************* 632 * Sink Interfaces - A sink corresponds to a display output device 633 ******************************************************************************/ 634 635 struct dc_container_id { 636 // 128bit GUID in binary form 637 unsigned char guid[16]; 638 // 8 byte port ID -> ELD.PortID 639 unsigned int portId[2]; 640 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 641 unsigned short manufacturerName; 642 // 2 byte product code -> ELD.ProductCode 643 unsigned short productCode; 644 }; 645 646 647 648 /* 649 * The sink structure contains EDID and other display device properties 650 */ 651 struct dc_sink { 652 enum signal_type sink_signal; 653 struct dc_edid dc_edid; /* raw edid */ 654 struct dc_edid_caps edid_caps; /* parse display caps */ 655 struct dc_container_id *dc_container_id; 656 uint32_t dongle_max_pix_clk; 657 void *priv; 658 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 659 bool converter_disable_audio; 660 661 /* private to DC core */ 662 struct dc_link *link; 663 struct dc_context *ctx; 664 665 /* private to dc_sink.c */ 666 struct kref refcount; 667 668 }; 669 670 void dc_sink_retain(struct dc_sink *sink); 671 void dc_sink_release(struct dc_sink *sink); 672 673 struct dc_sink_init_data { 674 enum signal_type sink_signal; 675 struct dc_link *link; 676 uint32_t dongle_max_pix_clk; 677 bool converter_disable_audio; 678 }; 679 680 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 681 682 /* Newer interfaces */ 683 struct dc_cursor { 684 struct dc_plane_address address; 685 struct dc_cursor_attributes attributes; 686 }; 687 688 689 /******************************************************************************* 690 * Interrupt interfaces 691 ******************************************************************************/ 692 enum dc_irq_source dc_interrupt_to_irq_source( 693 struct dc *dc, 694 uint32_t src_id, 695 uint32_t ext_id); 696 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 697 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 698 enum dc_irq_source dc_get_hpd_irq_source_at_index( 699 struct dc *dc, uint32_t link_index); 700 701 /******************************************************************************* 702 * Power Interfaces 703 ******************************************************************************/ 704 705 void dc_set_power_state( 706 struct dc *dc, 707 enum dc_acpi_cm_power_state power_state); 708 void dc_resume(struct dc *dc); 709 710 #endif /* DC_INTERFACE_H_ */ 711