1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #define DC_VER "3.2.108" 46 47 #define MAX_SURFACES 3 48 #define MAX_PLANES 6 49 #define MAX_STREAMS 6 50 #define MAX_SINKS_PER_LINK 4 51 52 /******************************************************************************* 53 * Display Core Interfaces 54 ******************************************************************************/ 55 struct dc_versions { 56 const char *dc_ver; 57 struct dmcu_version dmcu_version; 58 }; 59 60 enum dp_protocol_version { 61 DP_VERSION_1_4, 62 }; 63 64 enum dc_plane_type { 65 DC_PLANE_TYPE_INVALID, 66 DC_PLANE_TYPE_DCE_RGB, 67 DC_PLANE_TYPE_DCE_UNDERLAY, 68 DC_PLANE_TYPE_DCN_UNIVERSAL, 69 }; 70 71 struct dc_plane_cap { 72 enum dc_plane_type type; 73 uint32_t blends_with_above : 1; 74 uint32_t blends_with_below : 1; 75 uint32_t per_pixel_alpha : 1; 76 struct { 77 uint32_t argb8888 : 1; 78 uint32_t nv12 : 1; 79 uint32_t fp16 : 1; 80 uint32_t p010 : 1; 81 uint32_t ayuv : 1; 82 } pixel_format_support; 83 // max upscaling factor x1000 84 // upscaling factors are always >= 1 85 // for example, 1080p -> 8K is 4.0, or 4000 raw value 86 struct { 87 uint32_t argb8888; 88 uint32_t nv12; 89 uint32_t fp16; 90 } max_upscale_factor; 91 // max downscale factor x1000 92 // downscale factors are always <= 1 93 // for example, 8K -> 1080p is 0.25, or 250 raw value 94 struct { 95 uint32_t argb8888; 96 uint32_t nv12; 97 uint32_t fp16; 98 } max_downscale_factor; 99 // minimal width/height 100 uint32_t min_width; 101 uint32_t min_height; 102 }; 103 104 // Color management caps (DPP and MPC) 105 struct rom_curve_caps { 106 uint16_t srgb : 1; 107 uint16_t bt2020 : 1; 108 uint16_t gamma2_2 : 1; 109 uint16_t pq : 1; 110 uint16_t hlg : 1; 111 }; 112 113 struct dpp_color_caps { 114 uint16_t dcn_arch : 1; // all DCE generations treated the same 115 // input lut is different than most LUTs, just plain 256-entry lookup 116 uint16_t input_lut_shared : 1; // shared with DGAM 117 uint16_t icsc : 1; 118 uint16_t dgam_ram : 1; 119 uint16_t post_csc : 1; // before gamut remap 120 uint16_t gamma_corr : 1; 121 122 // hdr_mult and gamut remap always available in DPP (in that order) 123 // 3d lut implies shaper LUT, 124 // it may be shared with MPC - check MPC:shared_3d_lut flag 125 uint16_t hw_3d_lut : 1; 126 uint16_t ogam_ram : 1; // blnd gam 127 uint16_t ocsc : 1; 128 struct rom_curve_caps dgam_rom_caps; 129 struct rom_curve_caps ogam_rom_caps; 130 }; 131 132 struct mpc_color_caps { 133 uint16_t gamut_remap : 1; 134 uint16_t ogam_ram : 1; 135 uint16_t ocsc : 1; 136 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 137 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 138 139 struct rom_curve_caps ogam_rom_caps; 140 }; 141 142 struct dc_color_caps { 143 struct dpp_color_caps dpp; 144 struct mpc_color_caps mpc; 145 }; 146 147 struct dc_caps { 148 uint32_t max_streams; 149 uint32_t max_links; 150 uint32_t max_audios; 151 uint32_t max_slave_planes; 152 uint32_t max_planes; 153 uint32_t max_downscale_ratio; 154 uint32_t i2c_speed_in_khz; 155 uint32_t i2c_speed_in_khz_hdcp; 156 uint32_t dmdata_alloc_size; 157 unsigned int max_cursor_size; 158 unsigned int max_video_width; 159 unsigned int min_horizontal_blanking_period; 160 int linear_pitch_alignment; 161 bool dcc_const_color; 162 bool dynamic_audio; 163 bool is_apu; 164 bool dual_link_dvi; 165 bool post_blend_color_processing; 166 bool force_dp_tps4_for_cp2520; 167 bool disable_dp_clk_share; 168 bool psp_setup_panel_mode; 169 bool extended_aux_timeout_support; 170 bool dmcub_support; 171 enum dp_protocol_version max_dp_protocol_version; 172 struct dc_plane_cap planes[MAX_PLANES]; 173 struct dc_color_caps color; 174 }; 175 176 struct dc_bug_wa { 177 bool no_connect_phy_config; 178 bool dedcn20_305_wa; 179 bool skip_clock_update; 180 bool lt_early_cr_pattern; 181 }; 182 183 struct dc_dcc_surface_param { 184 struct dc_size surface_size; 185 enum surface_pixel_format format; 186 enum swizzle_mode_values swizzle_mode; 187 enum dc_scan_direction scan; 188 }; 189 190 struct dc_dcc_setting { 191 unsigned int max_compressed_blk_size; 192 unsigned int max_uncompressed_blk_size; 193 bool independent_64b_blks; 194 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 195 //These bitfields to be used starting with DCN 3.0 196 struct { 197 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 198 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 199 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 200 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 201 } dcc_controls; 202 #endif 203 }; 204 205 struct dc_surface_dcc_cap { 206 union { 207 struct { 208 struct dc_dcc_setting rgb; 209 } grph; 210 211 struct { 212 struct dc_dcc_setting luma; 213 struct dc_dcc_setting chroma; 214 } video; 215 }; 216 217 bool capable; 218 bool const_color_support; 219 }; 220 221 struct dc_static_screen_params { 222 struct { 223 bool force_trigger; 224 bool cursor_update; 225 bool surface_update; 226 bool overlay_update; 227 } triggers; 228 unsigned int num_frames; 229 }; 230 231 232 /* Surface update type is used by dc_update_surfaces_and_stream 233 * The update type is determined at the very beginning of the function based 234 * on parameters passed in and decides how much programming (or updating) is 235 * going to be done during the call. 236 * 237 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 238 * logical calculations or hardware register programming. This update MUST be 239 * ISR safe on windows. Currently fast update will only be used to flip surface 240 * address. 241 * 242 * UPDATE_TYPE_MED is used for slower updates which require significant hw 243 * re-programming however do not affect bandwidth consumption or clock 244 * requirements. At present, this is the level at which front end updates 245 * that do not require us to run bw_calcs happen. These are in/out transfer func 246 * updates, viewport offset changes, recout size changes and pixel depth changes. 247 * This update can be done at ISR, but we want to minimize how often this happens. 248 * 249 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 250 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 251 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 252 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 253 * a full update. This cannot be done at ISR level and should be a rare event. 254 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 255 * underscan we don't expect to see this call at all. 256 */ 257 258 enum surface_update_type { 259 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 260 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 261 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 262 }; 263 264 /* Forward declaration*/ 265 struct dc; 266 struct dc_plane_state; 267 struct dc_state; 268 269 270 struct dc_cap_funcs { 271 bool (*get_dcc_compression_cap)(const struct dc *dc, 272 const struct dc_dcc_surface_param *input, 273 struct dc_surface_dcc_cap *output); 274 }; 275 276 struct link_training_settings; 277 278 279 /* Structure to hold configuration flags set by dm at dc creation. */ 280 struct dc_config { 281 bool gpu_vm_support; 282 bool disable_disp_pll_sharing; 283 bool fbc_support; 284 bool optimize_edp_link_rate; 285 bool disable_fractional_pwm; 286 bool allow_seamless_boot_optimization; 287 bool power_down_display_on_boot; 288 bool edp_not_connected; 289 bool force_enum_edp; 290 bool forced_clocks; 291 bool allow_lttpr_non_transparent_mode; 292 bool multi_mon_pp_mclk_switch; 293 bool disable_dmcu; 294 bool enable_4to1MPC; 295 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 296 bool clamp_min_dcfclk; 297 #endif 298 }; 299 300 enum visual_confirm { 301 VISUAL_CONFIRM_DISABLE = 0, 302 VISUAL_CONFIRM_SURFACE = 1, 303 VISUAL_CONFIRM_HDR = 2, 304 VISUAL_CONFIRM_MPCTREE = 4, 305 VISUAL_CONFIRM_PSR = 5, 306 }; 307 308 enum dcc_option { 309 DCC_ENABLE = 0, 310 DCC_DISABLE = 1, 311 DCC_HALF_REQ_DISALBE = 2, 312 }; 313 314 enum pipe_split_policy { 315 MPC_SPLIT_DYNAMIC = 0, 316 MPC_SPLIT_AVOID = 1, 317 MPC_SPLIT_AVOID_MULT_DISP = 2, 318 }; 319 320 enum wm_report_mode { 321 WM_REPORT_DEFAULT = 0, 322 WM_REPORT_OVERRIDE = 1, 323 }; 324 enum dtm_pstate{ 325 dtm_level_p0 = 0,/*highest voltage*/ 326 dtm_level_p1, 327 dtm_level_p2, 328 dtm_level_p3, 329 dtm_level_p4,/*when active_display_count = 0*/ 330 }; 331 332 enum dcn_pwr_state { 333 DCN_PWR_STATE_UNKNOWN = -1, 334 DCN_PWR_STATE_MISSION_MODE = 0, 335 DCN_PWR_STATE_LOW_POWER = 3, 336 }; 337 338 /* 339 * For any clocks that may differ per pipe 340 * only the max is stored in this structure 341 */ 342 struct dc_clocks { 343 int dispclk_khz; 344 int dppclk_khz; 345 int disp_dpp_voltage_level_khz; 346 int dcfclk_khz; 347 int socclk_khz; 348 int dcfclk_deep_sleep_khz; 349 int fclk_khz; 350 int phyclk_khz; 351 int dramclk_khz; 352 bool p_state_change_support; 353 enum dcn_pwr_state pwr_state; 354 /* 355 * Elements below are not compared for the purposes of 356 * optimization required 357 */ 358 bool prev_p_state_change_support; 359 enum dtm_pstate dtm_level; 360 int max_supported_dppclk_khz; 361 int max_supported_dispclk_khz; 362 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 363 int bw_dispclk_khz; 364 }; 365 366 struct dc_bw_validation_profile { 367 bool enable; 368 369 unsigned long long total_ticks; 370 unsigned long long voltage_level_ticks; 371 unsigned long long watermark_ticks; 372 unsigned long long rq_dlg_ticks; 373 374 unsigned long long total_count; 375 unsigned long long skip_fast_count; 376 unsigned long long skip_pass_count; 377 unsigned long long skip_fail_count; 378 }; 379 380 #define BW_VAL_TRACE_SETUP() \ 381 unsigned long long end_tick = 0; \ 382 unsigned long long voltage_level_tick = 0; \ 383 unsigned long long watermark_tick = 0; \ 384 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 385 dm_get_timestamp(dc->ctx) : 0 386 387 #define BW_VAL_TRACE_COUNT() \ 388 if (dc->debug.bw_val_profile.enable) \ 389 dc->debug.bw_val_profile.total_count++ 390 391 #define BW_VAL_TRACE_SKIP(status) \ 392 if (dc->debug.bw_val_profile.enable) { \ 393 if (!voltage_level_tick) \ 394 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 395 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 396 } 397 398 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 399 if (dc->debug.bw_val_profile.enable) \ 400 voltage_level_tick = dm_get_timestamp(dc->ctx) 401 402 #define BW_VAL_TRACE_END_WATERMARKS() \ 403 if (dc->debug.bw_val_profile.enable) \ 404 watermark_tick = dm_get_timestamp(dc->ctx) 405 406 #define BW_VAL_TRACE_FINISH() \ 407 if (dc->debug.bw_val_profile.enable) { \ 408 end_tick = dm_get_timestamp(dc->ctx); \ 409 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 410 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 411 if (watermark_tick) { \ 412 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 413 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 414 } \ 415 } 416 417 struct dc_debug_options { 418 enum visual_confirm visual_confirm; 419 bool sanity_checks; 420 bool max_disp_clk; 421 bool surface_trace; 422 bool timing_trace; 423 bool clock_trace; 424 bool validation_trace; 425 bool bandwidth_calcs_trace; 426 int max_downscale_src_width; 427 428 /* stutter efficiency related */ 429 bool disable_stutter; 430 bool use_max_lb; 431 enum dcc_option disable_dcc; 432 enum pipe_split_policy pipe_split_policy; 433 bool force_single_disp_pipe_split; 434 bool voltage_align_fclk; 435 436 bool disable_dfs_bypass; 437 bool disable_dpp_power_gate; 438 bool disable_hubp_power_gate; 439 bool disable_dsc_power_gate; 440 int dsc_min_slice_height_override; 441 int dsc_bpp_increment_div; 442 bool native422_support; 443 bool disable_pplib_wm_range; 444 enum wm_report_mode pplib_wm_report_mode; 445 unsigned int min_disp_clk_khz; 446 unsigned int min_dpp_clk_khz; 447 int sr_exit_time_dpm0_ns; 448 int sr_enter_plus_exit_time_dpm0_ns; 449 int sr_exit_time_ns; 450 int sr_enter_plus_exit_time_ns; 451 int urgent_latency_ns; 452 uint32_t underflow_assert_delay_us; 453 int percent_of_ideal_drambw; 454 int dram_clock_change_latency_ns; 455 bool optimized_watermark; 456 int always_scale; 457 bool disable_pplib_clock_request; 458 bool disable_clock_gate; 459 bool disable_mem_low_power; 460 bool disable_dmcu; 461 bool disable_psr; 462 bool force_abm_enable; 463 bool disable_stereo_support; 464 bool vsr_support; 465 bool performance_trace; 466 bool az_endpoint_mute_only; 467 bool always_use_regamma; 468 bool p010_mpo_support; 469 bool recovery_enabled; 470 bool avoid_vbios_exec_table; 471 bool scl_reset_length10; 472 bool hdmi20_disable; 473 bool skip_detection_link_training; 474 bool edid_read_retry_times; 475 bool remove_disconnect_edp; 476 unsigned int force_odm_combine; //bit vector based on otg inst 477 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 478 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 479 #endif 480 unsigned int force_fclk_khz; 481 bool enable_tri_buf; 482 bool dmub_offload_enabled; 483 bool dmcub_emulation; 484 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 485 bool disable_idle_power_optimizations; 486 #endif 487 bool dmub_command_table; /* for testing only */ 488 struct dc_bw_validation_profile bw_val_profile; 489 bool disable_fec; 490 bool disable_48mhz_pwrdwn; 491 /* This forces a hard min on the DCFCLK requested to SMU/PP 492 * watermarks are not affected. 493 */ 494 unsigned int force_min_dcfclk_mhz; 495 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 496 int dwb_fi_phase; 497 #endif 498 bool disable_timing_sync; 499 bool cm_in_bypass; 500 int force_clock_mode;/*every mode change.*/ 501 502 bool disable_dram_clock_change_vactive_support; 503 bool validate_dml_output; 504 bool enable_dmcub_surface_flip; 505 bool usbc_combo_phy_reset_wa; 506 bool disable_dsc; 507 bool enable_dram_clock_change_one_display_vactive; 508 bool force_ignore_link_settings; 509 }; 510 511 struct dc_debug_data { 512 uint32_t ltFailCount; 513 uint32_t i2cErrorCount; 514 uint32_t auxErrorCount; 515 }; 516 517 struct dc_phy_addr_space_config { 518 struct { 519 uint64_t start_addr; 520 uint64_t end_addr; 521 uint64_t fb_top; 522 uint64_t fb_offset; 523 uint64_t fb_base; 524 uint64_t agp_top; 525 uint64_t agp_bot; 526 uint64_t agp_base; 527 } system_aperture; 528 529 struct { 530 uint64_t page_table_start_addr; 531 uint64_t page_table_end_addr; 532 uint64_t page_table_base_addr; 533 } gart_config; 534 535 bool valid; 536 bool is_hvm_enabled; 537 uint64_t page_table_default_page_addr; 538 }; 539 540 struct dc_virtual_addr_space_config { 541 uint64_t page_table_base_addr; 542 uint64_t page_table_start_addr; 543 uint64_t page_table_end_addr; 544 uint32_t page_table_block_size_in_bytes; 545 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 546 }; 547 548 struct dc_bounding_box_overrides { 549 int sr_exit_time_ns; 550 int sr_enter_plus_exit_time_ns; 551 int urgent_latency_ns; 552 int percent_of_ideal_drambw; 553 int dram_clock_change_latency_ns; 554 int dummy_clock_change_latency_ns; 555 /* This forces a hard min on the DCFCLK we use 556 * for DML. Unlike the debug option for forcing 557 * DCFCLK, this override affects watermark calculations 558 */ 559 int min_dcfclk_mhz; 560 }; 561 562 struct dc_state; 563 struct resource_pool; 564 struct dce_hwseq; 565 struct gpu_info_soc_bounding_box_v1_0; 566 struct dc { 567 struct dc_versions versions; 568 struct dc_caps caps; 569 struct dc_cap_funcs cap_funcs; 570 struct dc_config config; 571 struct dc_debug_options debug; 572 struct dc_bounding_box_overrides bb_overrides; 573 struct dc_bug_wa work_arounds; 574 struct dc_context *ctx; 575 struct dc_phy_addr_space_config vm_pa_config; 576 577 uint8_t link_count; 578 struct dc_link *links[MAX_PIPES * 2]; 579 580 struct dc_state *current_state; 581 struct resource_pool *res_pool; 582 583 struct clk_mgr *clk_mgr; 584 585 /* Display Engine Clock levels */ 586 struct dm_pp_clock_levels sclk_lvls; 587 588 /* Inputs into BW and WM calculations. */ 589 struct bw_calcs_dceip *bw_dceip; 590 struct bw_calcs_vbios *bw_vbios; 591 #ifdef CONFIG_DRM_AMD_DC_DCN 592 struct dcn_soc_bounding_box *dcn_soc; 593 struct dcn_ip_params *dcn_ip; 594 struct display_mode_lib dml; 595 #endif 596 597 /* HW functions */ 598 struct hw_sequencer_funcs hwss; 599 struct dce_hwseq *hwseq; 600 601 /* Require to optimize clocks and bandwidth for added/removed planes */ 602 bool optimized_required; 603 bool wm_optimized_required; 604 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 605 bool idle_optimizations_allowed; 606 #endif 607 608 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 609 int optimize_seamless_boot_streams; 610 611 /* FBC compressor */ 612 struct compressor *fbc_compressor; 613 614 struct dc_debug_data debug_data; 615 struct dpcd_vendor_signature vendor_signature; 616 617 const char *build_id; 618 struct vm_helper *vm_helper; 619 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 620 }; 621 622 enum frame_buffer_mode { 623 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 624 FRAME_BUFFER_MODE_ZFB_ONLY, 625 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 626 } ; 627 628 struct dchub_init_data { 629 int64_t zfb_phys_addr_base; 630 int64_t zfb_mc_base_addr; 631 uint64_t zfb_size_in_byte; 632 enum frame_buffer_mode fb_mode; 633 bool dchub_initialzied; 634 bool dchub_info_valid; 635 }; 636 637 struct dc_init_data { 638 struct hw_asic_id asic_id; 639 void *driver; /* ctx */ 640 struct cgs_device *cgs_device; 641 struct dc_bounding_box_overrides bb_overrides; 642 643 int num_virtual_links; 644 /* 645 * If 'vbios_override' not NULL, it will be called instead 646 * of the real VBIOS. Intended use is Diagnostics on FPGA. 647 */ 648 struct dc_bios *vbios_override; 649 enum dce_environment dce_environment; 650 651 struct dmub_offload_funcs *dmub_if; 652 struct dc_reg_helper_state *dmub_offload; 653 654 struct dc_config flags; 655 uint64_t log_mask; 656 657 /** 658 * gpu_info FW provided soc bounding box struct or 0 if not 659 * available in FW 660 */ 661 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 662 struct dpcd_vendor_signature vendor_signature; 663 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 664 bool force_smu_not_present; 665 #endif 666 bool force_ignore_link_settings; 667 }; 668 669 struct dc_callback_init { 670 #ifdef CONFIG_DRM_AMD_DC_HDCP 671 struct cp_psp cp_psp; 672 #else 673 uint8_t reserved; 674 #endif 675 }; 676 677 struct dc *dc_create(const struct dc_init_data *init_params); 678 void dc_hardware_init(struct dc *dc); 679 680 int dc_get_vmid_use_vector(struct dc *dc); 681 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 682 /* Returns the number of vmids supported */ 683 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 684 void dc_init_callbacks(struct dc *dc, 685 const struct dc_callback_init *init_params); 686 void dc_deinit_callbacks(struct dc *dc); 687 void dc_destroy(struct dc **dc); 688 689 /******************************************************************************* 690 * Surface Interfaces 691 ******************************************************************************/ 692 693 enum { 694 TRANSFER_FUNC_POINTS = 1025 695 }; 696 697 struct dc_hdr_static_metadata { 698 /* display chromaticities and white point in units of 0.00001 */ 699 unsigned int chromaticity_green_x; 700 unsigned int chromaticity_green_y; 701 unsigned int chromaticity_blue_x; 702 unsigned int chromaticity_blue_y; 703 unsigned int chromaticity_red_x; 704 unsigned int chromaticity_red_y; 705 unsigned int chromaticity_white_point_x; 706 unsigned int chromaticity_white_point_y; 707 708 uint32_t min_luminance; 709 uint32_t max_luminance; 710 uint32_t maximum_content_light_level; 711 uint32_t maximum_frame_average_light_level; 712 }; 713 714 enum dc_transfer_func_type { 715 TF_TYPE_PREDEFINED, 716 TF_TYPE_DISTRIBUTED_POINTS, 717 TF_TYPE_BYPASS, 718 TF_TYPE_HWPWL 719 }; 720 721 struct dc_transfer_func_distributed_points { 722 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 723 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 724 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 725 726 uint16_t end_exponent; 727 uint16_t x_point_at_y1_red; 728 uint16_t x_point_at_y1_green; 729 uint16_t x_point_at_y1_blue; 730 }; 731 732 enum dc_transfer_func_predefined { 733 TRANSFER_FUNCTION_SRGB, 734 TRANSFER_FUNCTION_BT709, 735 TRANSFER_FUNCTION_PQ, 736 TRANSFER_FUNCTION_LINEAR, 737 TRANSFER_FUNCTION_UNITY, 738 TRANSFER_FUNCTION_HLG, 739 TRANSFER_FUNCTION_HLG12, 740 TRANSFER_FUNCTION_GAMMA22, 741 TRANSFER_FUNCTION_GAMMA24, 742 TRANSFER_FUNCTION_GAMMA26 743 }; 744 745 746 struct dc_transfer_func { 747 struct kref refcount; 748 enum dc_transfer_func_type type; 749 enum dc_transfer_func_predefined tf; 750 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 751 uint32_t sdr_ref_white_level; 752 union { 753 struct pwl_params pwl; 754 struct dc_transfer_func_distributed_points tf_pts; 755 }; 756 }; 757 758 759 union dc_3dlut_state { 760 struct { 761 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 762 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 763 uint32_t rmu_mux_num:3; /*index of mux to use*/ 764 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 765 uint32_t mpc_rmu1_mux:4; 766 uint32_t mpc_rmu2_mux:4; 767 uint32_t reserved:15; 768 } bits; 769 uint32_t raw; 770 }; 771 772 773 struct dc_3dlut { 774 struct kref refcount; 775 struct tetrahedral_params lut_3d; 776 struct fixed31_32 hdr_multiplier; 777 union dc_3dlut_state state; 778 }; 779 /* 780 * This structure is filled in by dc_surface_get_status and contains 781 * the last requested address and the currently active address so the called 782 * can determine if there are any outstanding flips 783 */ 784 struct dc_plane_status { 785 struct dc_plane_address requested_address; 786 struct dc_plane_address current_address; 787 bool is_flip_pending; 788 bool is_right_eye; 789 }; 790 791 union surface_update_flags { 792 793 struct { 794 uint32_t addr_update:1; 795 /* Medium updates */ 796 uint32_t dcc_change:1; 797 uint32_t color_space_change:1; 798 uint32_t horizontal_mirror_change:1; 799 uint32_t per_pixel_alpha_change:1; 800 uint32_t global_alpha_change:1; 801 uint32_t hdr_mult:1; 802 uint32_t rotation_change:1; 803 uint32_t swizzle_change:1; 804 uint32_t scaling_change:1; 805 uint32_t position_change:1; 806 uint32_t in_transfer_func_change:1; 807 uint32_t input_csc_change:1; 808 uint32_t coeff_reduction_change:1; 809 uint32_t output_tf_change:1; 810 uint32_t pixel_format_change:1; 811 uint32_t plane_size_change:1; 812 uint32_t gamut_remap_change:1; 813 814 /* Full updates */ 815 uint32_t new_plane:1; 816 uint32_t bpp_change:1; 817 uint32_t gamma_change:1; 818 uint32_t bandwidth_change:1; 819 uint32_t clock_change:1; 820 uint32_t stereo_format_change:1; 821 uint32_t full_update:1; 822 } bits; 823 824 uint32_t raw; 825 }; 826 827 struct dc_plane_state { 828 struct dc_plane_address address; 829 struct dc_plane_flip_time time; 830 bool triplebuffer_flips; 831 struct scaling_taps scaling_quality; 832 struct rect src_rect; 833 struct rect dst_rect; 834 struct rect clip_rect; 835 836 struct plane_size plane_size; 837 union dc_tiling_info tiling_info; 838 839 struct dc_plane_dcc_param dcc; 840 841 struct dc_gamma *gamma_correction; 842 struct dc_transfer_func *in_transfer_func; 843 struct dc_bias_and_scale *bias_and_scale; 844 struct dc_csc_transform input_csc_color_matrix; 845 struct fixed31_32 coeff_reduction_factor; 846 struct fixed31_32 hdr_mult; 847 struct colorspace_transform gamut_remap_matrix; 848 849 // TODO: No longer used, remove 850 struct dc_hdr_static_metadata hdr_static_ctx; 851 852 enum dc_color_space color_space; 853 854 struct dc_3dlut *lut3d_func; 855 struct dc_transfer_func *in_shaper_func; 856 struct dc_transfer_func *blend_tf; 857 858 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 859 struct dc_transfer_func *gamcor_tf; 860 #endif 861 enum surface_pixel_format format; 862 enum dc_rotation_angle rotation; 863 enum plane_stereo_format stereo_format; 864 865 bool is_tiling_rotated; 866 bool per_pixel_alpha; 867 bool global_alpha; 868 int global_alpha_value; 869 bool visible; 870 bool flip_immediate; 871 bool horizontal_mirror; 872 int layer_index; 873 874 union surface_update_flags update_flags; 875 /* private to DC core */ 876 struct dc_plane_status status; 877 struct dc_context *ctx; 878 879 /* HACK: Workaround for forcing full reprogramming under some conditions */ 880 bool force_full_update; 881 882 /* private to dc_surface.c */ 883 enum dc_irq_source irq_source; 884 struct kref refcount; 885 }; 886 887 struct dc_plane_info { 888 struct plane_size plane_size; 889 union dc_tiling_info tiling_info; 890 struct dc_plane_dcc_param dcc; 891 enum surface_pixel_format format; 892 enum dc_rotation_angle rotation; 893 enum plane_stereo_format stereo_format; 894 enum dc_color_space color_space; 895 bool horizontal_mirror; 896 bool visible; 897 bool per_pixel_alpha; 898 bool global_alpha; 899 int global_alpha_value; 900 bool input_csc_enabled; 901 int layer_index; 902 }; 903 904 struct dc_scaling_info { 905 struct rect src_rect; 906 struct rect dst_rect; 907 struct rect clip_rect; 908 struct scaling_taps scaling_quality; 909 }; 910 911 struct dc_surface_update { 912 struct dc_plane_state *surface; 913 914 /* isr safe update parameters. null means no updates */ 915 const struct dc_flip_addrs *flip_addr; 916 const struct dc_plane_info *plane_info; 917 const struct dc_scaling_info *scaling_info; 918 struct fixed31_32 hdr_mult; 919 /* following updates require alloc/sleep/spin that is not isr safe, 920 * null means no updates 921 */ 922 const struct dc_gamma *gamma; 923 const struct dc_transfer_func *in_transfer_func; 924 925 const struct dc_csc_transform *input_csc_color_matrix; 926 const struct fixed31_32 *coeff_reduction_factor; 927 const struct dc_transfer_func *func_shaper; 928 const struct dc_3dlut *lut3d_func; 929 const struct dc_transfer_func *blend_tf; 930 const struct colorspace_transform *gamut_remap_matrix; 931 }; 932 933 /* 934 * Create a new surface with default parameters; 935 */ 936 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 937 const struct dc_plane_status *dc_plane_get_status( 938 const struct dc_plane_state *plane_state); 939 940 void dc_plane_state_retain(struct dc_plane_state *plane_state); 941 void dc_plane_state_release(struct dc_plane_state *plane_state); 942 943 void dc_gamma_retain(struct dc_gamma *dc_gamma); 944 void dc_gamma_release(struct dc_gamma **dc_gamma); 945 struct dc_gamma *dc_create_gamma(void); 946 947 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 948 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 949 struct dc_transfer_func *dc_create_transfer_func(void); 950 951 struct dc_3dlut *dc_create_3dlut_func(void); 952 void dc_3dlut_func_release(struct dc_3dlut *lut); 953 void dc_3dlut_func_retain(struct dc_3dlut *lut); 954 /* 955 * This structure holds a surface address. There could be multiple addresses 956 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 957 * as frame durations and DCC format can also be set. 958 */ 959 struct dc_flip_addrs { 960 struct dc_plane_address address; 961 unsigned int flip_timestamp_in_us; 962 bool flip_immediate; 963 /* TODO: add flip duration for FreeSync */ 964 bool triplebuffer_flips; 965 }; 966 967 void dc_post_update_surfaces_to_stream( 968 struct dc *dc); 969 970 #include "dc_stream.h" 971 972 /* 973 * Structure to store surface/stream associations for validation 974 */ 975 struct dc_validation_set { 976 struct dc_stream_state *stream; 977 struct dc_plane_state *plane_states[MAX_SURFACES]; 978 uint8_t plane_count; 979 }; 980 981 bool dc_validate_seamless_boot_timing(const struct dc *dc, 982 const struct dc_sink *sink, 983 struct dc_crtc_timing *crtc_timing); 984 985 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 986 987 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 988 989 bool dc_set_generic_gpio_for_stereo(bool enable, 990 struct gpio_service *gpio_service); 991 992 /* 993 * fast_validate: we return after determining if we can support the new state, 994 * but before we populate the programming info 995 */ 996 enum dc_status dc_validate_global_state( 997 struct dc *dc, 998 struct dc_state *new_ctx, 999 bool fast_validate); 1000 1001 1002 void dc_resource_state_construct( 1003 const struct dc *dc, 1004 struct dc_state *dst_ctx); 1005 1006 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 1007 bool dc_acquire_release_mpc_3dlut( 1008 struct dc *dc, bool acquire, 1009 struct dc_stream_state *stream, 1010 struct dc_3dlut **lut, 1011 struct dc_transfer_func **shaper); 1012 #endif 1013 1014 void dc_resource_state_copy_construct( 1015 const struct dc_state *src_ctx, 1016 struct dc_state *dst_ctx); 1017 1018 void dc_resource_state_copy_construct_current( 1019 const struct dc *dc, 1020 struct dc_state *dst_ctx); 1021 1022 void dc_resource_state_destruct(struct dc_state *context); 1023 1024 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1025 1026 /* 1027 * TODO update to make it about validation sets 1028 * Set up streams and links associated to drive sinks 1029 * The streams parameter is an absolute set of all active streams. 1030 * 1031 * After this call: 1032 * Phy, Encoder, Timing Generator are programmed and enabled. 1033 * New streams are enabled with blank stream; no memory read. 1034 */ 1035 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1036 1037 void dc_power_down_on_boot(struct dc *dc); 1038 1039 struct dc_state *dc_create_state(struct dc *dc); 1040 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1041 void dc_retain_state(struct dc_state *context); 1042 void dc_release_state(struct dc_state *context); 1043 1044 /******************************************************************************* 1045 * Link Interfaces 1046 ******************************************************************************/ 1047 1048 struct dpcd_caps { 1049 union dpcd_rev dpcd_rev; 1050 union max_lane_count max_ln_count; 1051 union max_down_spread max_down_spread; 1052 union dprx_feature dprx_feature; 1053 1054 /* valid only for eDP v1.4 or higher*/ 1055 uint8_t edp_supported_link_rates_count; 1056 enum dc_link_rate edp_supported_link_rates[8]; 1057 1058 /* dongle type (DP converter, CV smart dongle) */ 1059 enum display_dongle_type dongle_type; 1060 /* branch device or sink device */ 1061 bool is_branch_dev; 1062 /* Dongle's downstream count. */ 1063 union sink_count sink_count; 1064 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1065 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1066 struct dc_dongle_caps dongle_caps; 1067 1068 uint32_t sink_dev_id; 1069 int8_t sink_dev_id_str[6]; 1070 int8_t sink_hw_revision; 1071 int8_t sink_fw_revision[2]; 1072 1073 uint32_t branch_dev_id; 1074 int8_t branch_dev_name[6]; 1075 int8_t branch_hw_revision; 1076 int8_t branch_fw_revision[2]; 1077 1078 bool allow_invalid_MSA_timing_param; 1079 bool panel_mode_edp; 1080 bool dpcd_display_control_capable; 1081 bool ext_receiver_cap_field_present; 1082 union dpcd_fec_capability fec_cap; 1083 struct dpcd_dsc_capabilities dsc_caps; 1084 struct dc_lttpr_caps lttpr_caps; 1085 struct psr_caps psr_caps; 1086 1087 }; 1088 1089 union dpcd_sink_ext_caps { 1090 struct { 1091 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1092 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1093 */ 1094 uint8_t sdr_aux_backlight_control : 1; 1095 uint8_t hdr_aux_backlight_control : 1; 1096 uint8_t reserved_1 : 2; 1097 uint8_t oled : 1; 1098 uint8_t reserved : 3; 1099 } bits; 1100 uint8_t raw; 1101 }; 1102 1103 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1104 union hdcp_rx_caps { 1105 struct { 1106 uint8_t version; 1107 uint8_t reserved; 1108 struct { 1109 uint8_t repeater : 1; 1110 uint8_t hdcp_capable : 1; 1111 uint8_t reserved : 6; 1112 } byte0; 1113 } fields; 1114 uint8_t raw[3]; 1115 }; 1116 1117 union hdcp_bcaps { 1118 struct { 1119 uint8_t HDCP_CAPABLE:1; 1120 uint8_t REPEATER:1; 1121 uint8_t RESERVED:6; 1122 } bits; 1123 uint8_t raw; 1124 }; 1125 1126 struct hdcp_caps { 1127 union hdcp_rx_caps rx_caps; 1128 union hdcp_bcaps bcaps; 1129 }; 1130 #endif 1131 1132 #include "dc_link.h" 1133 1134 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 1135 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1136 1137 #endif 1138 /******************************************************************************* 1139 * Sink Interfaces - A sink corresponds to a display output device 1140 ******************************************************************************/ 1141 1142 struct dc_container_id { 1143 // 128bit GUID in binary form 1144 unsigned char guid[16]; 1145 // 8 byte port ID -> ELD.PortID 1146 unsigned int portId[2]; 1147 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1148 unsigned short manufacturerName; 1149 // 2 byte product code -> ELD.ProductCode 1150 unsigned short productCode; 1151 }; 1152 1153 1154 struct dc_sink_dsc_caps { 1155 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1156 // 'false' if they are sink's DSC caps 1157 bool is_virtual_dpcd_dsc; 1158 struct dsc_dec_dpcd_caps dsc_dec_caps; 1159 }; 1160 1161 struct dc_sink_fec_caps { 1162 bool is_rx_fec_supported; 1163 bool is_topology_fec_supported; 1164 }; 1165 1166 /* 1167 * The sink structure contains EDID and other display device properties 1168 */ 1169 struct dc_sink { 1170 enum signal_type sink_signal; 1171 struct dc_edid dc_edid; /* raw edid */ 1172 struct dc_edid_caps edid_caps; /* parse display caps */ 1173 struct dc_container_id *dc_container_id; 1174 uint32_t dongle_max_pix_clk; 1175 void *priv; 1176 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1177 bool converter_disable_audio; 1178 1179 struct dc_sink_dsc_caps dsc_caps; 1180 struct dc_sink_fec_caps fec_caps; 1181 1182 bool is_vsc_sdp_colorimetry_supported; 1183 1184 /* private to DC core */ 1185 struct dc_link *link; 1186 struct dc_context *ctx; 1187 1188 uint32_t sink_id; 1189 1190 /* private to dc_sink.c */ 1191 // refcount must be the last member in dc_sink, since we want the 1192 // sink structure to be logically cloneable up to (but not including) 1193 // refcount 1194 struct kref refcount; 1195 }; 1196 1197 void dc_sink_retain(struct dc_sink *sink); 1198 void dc_sink_release(struct dc_sink *sink); 1199 1200 struct dc_sink_init_data { 1201 enum signal_type sink_signal; 1202 struct dc_link *link; 1203 uint32_t dongle_max_pix_clk; 1204 bool converter_disable_audio; 1205 }; 1206 1207 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1208 1209 /* Newer interfaces */ 1210 struct dc_cursor { 1211 struct dc_plane_address address; 1212 struct dc_cursor_attributes attributes; 1213 }; 1214 1215 1216 /******************************************************************************* 1217 * Interrupt interfaces 1218 ******************************************************************************/ 1219 enum dc_irq_source dc_interrupt_to_irq_source( 1220 struct dc *dc, 1221 uint32_t src_id, 1222 uint32_t ext_id); 1223 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1224 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1225 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1226 struct dc *dc, uint32_t link_index); 1227 1228 /******************************************************************************* 1229 * Power Interfaces 1230 ******************************************************************************/ 1231 1232 void dc_set_power_state( 1233 struct dc *dc, 1234 enum dc_acpi_cm_power_state power_state); 1235 void dc_resume(struct dc *dc); 1236 1237 void dc_power_down_on_boot(struct dc *dc); 1238 1239 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1240 /* 1241 * HDCP Interfaces 1242 */ 1243 enum hdcp_message_status dc_process_hdcp_msg( 1244 enum signal_type signal, 1245 struct dc_link *link, 1246 struct hdcp_protection_message *message_info); 1247 #endif 1248 bool dc_is_dmcu_initialized(struct dc *dc); 1249 1250 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1251 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1252 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 1253 1254 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 1255 struct dc_plane_state *plane); 1256 1257 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1258 1259 /* 1260 * blank all streams, and set min and max memory clock to 1261 * lowest and highest DPM level, respectively 1262 */ 1263 void dc_unlock_memory_clock_frequency(struct dc *dc); 1264 1265 /* 1266 * set min memory clock to the min required for current mode, 1267 * max to maxDPM, and unblank streams 1268 */ 1269 void dc_lock_memory_clock_frequency(struct dc *dc); 1270 1271 /* cleanup on driver unload */ 1272 void dc_hardware_release(struct dc *dc); 1273 1274 #endif 1275 1276 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1277 1278 /******************************************************************************* 1279 * DSC Interfaces 1280 ******************************************************************************/ 1281 #include "dc_dsc.h" 1282 #endif /* DC_INTERFACE_H_ */ 1283