1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.183" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 // Sizes defined as multiples of 64KB 79 enum det_size { 80 DET_SIZE_DEFAULT = 0, 81 DET_SIZE_192KB = 3, 82 DET_SIZE_256KB = 4, 83 DET_SIZE_320KB = 5, 84 DET_SIZE_384KB = 6 85 }; 86 87 88 struct dc_plane_cap { 89 enum dc_plane_type type; 90 uint32_t blends_with_above : 1; 91 uint32_t blends_with_below : 1; 92 uint32_t per_pixel_alpha : 1; 93 struct { 94 uint32_t argb8888 : 1; 95 uint32_t nv12 : 1; 96 uint32_t fp16 : 1; 97 uint32_t p010 : 1; 98 uint32_t ayuv : 1; 99 } pixel_format_support; 100 // max upscaling factor x1000 101 // upscaling factors are always >= 1 102 // for example, 1080p -> 8K is 4.0, or 4000 raw value 103 struct { 104 uint32_t argb8888; 105 uint32_t nv12; 106 uint32_t fp16; 107 } max_upscale_factor; 108 // max downscale factor x1000 109 // downscale factors are always <= 1 110 // for example, 8K -> 1080p is 0.25, or 250 raw value 111 struct { 112 uint32_t argb8888; 113 uint32_t nv12; 114 uint32_t fp16; 115 } max_downscale_factor; 116 // minimal width/height 117 uint32_t min_width; 118 uint32_t min_height; 119 }; 120 121 // Color management caps (DPP and MPC) 122 struct rom_curve_caps { 123 uint16_t srgb : 1; 124 uint16_t bt2020 : 1; 125 uint16_t gamma2_2 : 1; 126 uint16_t pq : 1; 127 uint16_t hlg : 1; 128 }; 129 130 struct dpp_color_caps { 131 uint16_t dcn_arch : 1; // all DCE generations treated the same 132 // input lut is different than most LUTs, just plain 256-entry lookup 133 uint16_t input_lut_shared : 1; // shared with DGAM 134 uint16_t icsc : 1; 135 uint16_t dgam_ram : 1; 136 uint16_t post_csc : 1; // before gamut remap 137 uint16_t gamma_corr : 1; 138 139 // hdr_mult and gamut remap always available in DPP (in that order) 140 // 3d lut implies shaper LUT, 141 // it may be shared with MPC - check MPC:shared_3d_lut flag 142 uint16_t hw_3d_lut : 1; 143 uint16_t ogam_ram : 1; // blnd gam 144 uint16_t ocsc : 1; 145 uint16_t dgam_rom_for_yuv : 1; 146 struct rom_curve_caps dgam_rom_caps; 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct mpc_color_caps { 151 uint16_t gamut_remap : 1; 152 uint16_t ogam_ram : 1; 153 uint16_t ocsc : 1; 154 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 155 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 156 157 struct rom_curve_caps ogam_rom_caps; 158 }; 159 160 struct dc_color_caps { 161 struct dpp_color_caps dpp; 162 struct mpc_color_caps mpc; 163 }; 164 165 struct dc_caps { 166 uint32_t max_streams; 167 uint32_t max_links; 168 uint32_t max_audios; 169 uint32_t max_slave_planes; 170 uint32_t max_slave_yuv_planes; 171 uint32_t max_slave_rgb_planes; 172 uint32_t max_planes; 173 uint32_t max_downscale_ratio; 174 uint32_t i2c_speed_in_khz; 175 uint32_t i2c_speed_in_khz_hdcp; 176 uint32_t dmdata_alloc_size; 177 unsigned int max_cursor_size; 178 unsigned int max_video_width; 179 unsigned int min_horizontal_blanking_period; 180 int linear_pitch_alignment; 181 bool dcc_const_color; 182 bool dynamic_audio; 183 bool is_apu; 184 bool dual_link_dvi; 185 bool post_blend_color_processing; 186 bool force_dp_tps4_for_cp2520; 187 bool disable_dp_clk_share; 188 bool psp_setup_panel_mode; 189 bool extended_aux_timeout_support; 190 bool dmcub_support; 191 bool zstate_support; 192 uint32_t num_of_internal_disp; 193 enum dp_protocol_version max_dp_protocol_version; 194 unsigned int mall_size_per_mem_channel; 195 unsigned int mall_size_total; 196 unsigned int cursor_cache_size; 197 struct dc_plane_cap planes[MAX_PLANES]; 198 struct dc_color_caps color; 199 bool dp_hpo; 200 bool hdmi_frl_pcon_support; 201 bool edp_dsc_support; 202 bool vbios_lttpr_aware; 203 bool vbios_lttpr_enable; 204 uint32_t max_otg_num; 205 }; 206 207 struct dc_bug_wa { 208 bool no_connect_phy_config; 209 bool dedcn20_305_wa; 210 bool skip_clock_update; 211 bool lt_early_cr_pattern; 212 }; 213 214 struct dc_dcc_surface_param { 215 struct dc_size surface_size; 216 enum surface_pixel_format format; 217 enum swizzle_mode_values swizzle_mode; 218 enum dc_scan_direction scan; 219 }; 220 221 struct dc_dcc_setting { 222 unsigned int max_compressed_blk_size; 223 unsigned int max_uncompressed_blk_size; 224 bool independent_64b_blks; 225 #if defined(CONFIG_DRM_AMD_DC_DCN) 226 //These bitfields to be used starting with DCN 227 struct { 228 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 229 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 230 uint32_t dcc_256_128_128 : 1; //available starting with DCN 231 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 232 } dcc_controls; 233 #endif 234 }; 235 236 struct dc_surface_dcc_cap { 237 union { 238 struct { 239 struct dc_dcc_setting rgb; 240 } grph; 241 242 struct { 243 struct dc_dcc_setting luma; 244 struct dc_dcc_setting chroma; 245 } video; 246 }; 247 248 bool capable; 249 bool const_color_support; 250 }; 251 252 struct dc_static_screen_params { 253 struct { 254 bool force_trigger; 255 bool cursor_update; 256 bool surface_update; 257 bool overlay_update; 258 } triggers; 259 unsigned int num_frames; 260 }; 261 262 263 /* Surface update type is used by dc_update_surfaces_and_stream 264 * The update type is determined at the very beginning of the function based 265 * on parameters passed in and decides how much programming (or updating) is 266 * going to be done during the call. 267 * 268 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 269 * logical calculations or hardware register programming. This update MUST be 270 * ISR safe on windows. Currently fast update will only be used to flip surface 271 * address. 272 * 273 * UPDATE_TYPE_MED is used for slower updates which require significant hw 274 * re-programming however do not affect bandwidth consumption or clock 275 * requirements. At present, this is the level at which front end updates 276 * that do not require us to run bw_calcs happen. These are in/out transfer func 277 * updates, viewport offset changes, recout size changes and pixel depth changes. 278 * This update can be done at ISR, but we want to minimize how often this happens. 279 * 280 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 281 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 282 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 283 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 284 * a full update. This cannot be done at ISR level and should be a rare event. 285 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 286 * underscan we don't expect to see this call at all. 287 */ 288 289 enum surface_update_type { 290 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 291 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 292 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 293 }; 294 295 /* Forward declaration*/ 296 struct dc; 297 struct dc_plane_state; 298 struct dc_state; 299 300 301 struct dc_cap_funcs { 302 bool (*get_dcc_compression_cap)(const struct dc *dc, 303 const struct dc_dcc_surface_param *input, 304 struct dc_surface_dcc_cap *output); 305 }; 306 307 struct link_training_settings; 308 309 union allow_lttpr_non_transparent_mode { 310 struct { 311 bool DP1_4A : 1; 312 bool DP2_0 : 1; 313 } bits; 314 unsigned char raw; 315 }; 316 317 /* Structure to hold configuration flags set by dm at dc creation. */ 318 struct dc_config { 319 bool gpu_vm_support; 320 bool disable_disp_pll_sharing; 321 bool fbc_support; 322 bool disable_fractional_pwm; 323 bool allow_seamless_boot_optimization; 324 bool seamless_boot_edp_requested; 325 bool edp_not_connected; 326 bool edp_no_power_sequencing; 327 bool force_enum_edp; 328 bool forced_clocks; 329 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 330 bool multi_mon_pp_mclk_switch; 331 bool disable_dmcu; 332 bool enable_4to1MPC; 333 bool enable_windowed_mpo_odm; 334 bool allow_edp_hotplug_detection; 335 #if defined(CONFIG_DRM_AMD_DC_DCN) 336 bool clamp_min_dcfclk; 337 #endif 338 uint64_t vblank_alignment_dto_params; 339 uint8_t vblank_alignment_max_frame_time_diff; 340 bool is_asymmetric_memory; 341 bool is_single_rank_dimm; 342 bool use_pipe_ctx_sync_logic; 343 bool ignore_dpref_ss; 344 }; 345 346 enum visual_confirm { 347 VISUAL_CONFIRM_DISABLE = 0, 348 VISUAL_CONFIRM_SURFACE = 1, 349 VISUAL_CONFIRM_HDR = 2, 350 VISUAL_CONFIRM_MPCTREE = 4, 351 VISUAL_CONFIRM_PSR = 5, 352 VISUAL_CONFIRM_SWIZZLE = 9, 353 }; 354 355 enum dc_psr_power_opts { 356 psr_power_opt_invalid = 0x0, 357 psr_power_opt_smu_opt_static_screen = 0x1, 358 psr_power_opt_z10_static_screen = 0x10, 359 psr_power_opt_ds_disable_allow = 0x100, 360 }; 361 362 enum dml_hostvm_override_opts { 363 DML_HOSTVM_NO_OVERRIDE = 0x0, 364 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 365 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 366 }; 367 368 enum dcc_option { 369 DCC_ENABLE = 0, 370 DCC_DISABLE = 1, 371 DCC_HALF_REQ_DISALBE = 2, 372 }; 373 374 enum pipe_split_policy { 375 MPC_SPLIT_DYNAMIC = 0, 376 MPC_SPLIT_AVOID = 1, 377 MPC_SPLIT_AVOID_MULT_DISP = 2, 378 }; 379 380 enum wm_report_mode { 381 WM_REPORT_DEFAULT = 0, 382 WM_REPORT_OVERRIDE = 1, 383 }; 384 enum dtm_pstate{ 385 dtm_level_p0 = 0,/*highest voltage*/ 386 dtm_level_p1, 387 dtm_level_p2, 388 dtm_level_p3, 389 dtm_level_p4,/*when active_display_count = 0*/ 390 }; 391 392 enum dcn_pwr_state { 393 DCN_PWR_STATE_UNKNOWN = -1, 394 DCN_PWR_STATE_MISSION_MODE = 0, 395 DCN_PWR_STATE_LOW_POWER = 3, 396 }; 397 398 #if defined(CONFIG_DRM_AMD_DC_DCN) 399 enum dcn_zstate_support_state { 400 DCN_ZSTATE_SUPPORT_UNKNOWN, 401 DCN_ZSTATE_SUPPORT_ALLOW, 402 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 403 DCN_ZSTATE_SUPPORT_DISALLOW, 404 }; 405 #endif 406 /* 407 * For any clocks that may differ per pipe 408 * only the max is stored in this structure 409 */ 410 struct dc_clocks { 411 int dispclk_khz; 412 int actual_dispclk_khz; 413 int dppclk_khz; 414 int actual_dppclk_khz; 415 int disp_dpp_voltage_level_khz; 416 int dcfclk_khz; 417 int socclk_khz; 418 int dcfclk_deep_sleep_khz; 419 int fclk_khz; 420 int phyclk_khz; 421 int dramclk_khz; 422 bool p_state_change_support; 423 #if defined(CONFIG_DRM_AMD_DC_DCN) 424 enum dcn_zstate_support_state zstate_support; 425 bool dtbclk_en; 426 #endif 427 enum dcn_pwr_state pwr_state; 428 /* 429 * Elements below are not compared for the purposes of 430 * optimization required 431 */ 432 bool prev_p_state_change_support; 433 enum dtm_pstate dtm_level; 434 int max_supported_dppclk_khz; 435 int max_supported_dispclk_khz; 436 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 437 int bw_dispclk_khz; 438 }; 439 440 struct dc_bw_validation_profile { 441 bool enable; 442 443 unsigned long long total_ticks; 444 unsigned long long voltage_level_ticks; 445 unsigned long long watermark_ticks; 446 unsigned long long rq_dlg_ticks; 447 448 unsigned long long total_count; 449 unsigned long long skip_fast_count; 450 unsigned long long skip_pass_count; 451 unsigned long long skip_fail_count; 452 }; 453 454 #define BW_VAL_TRACE_SETUP() \ 455 unsigned long long end_tick = 0; \ 456 unsigned long long voltage_level_tick = 0; \ 457 unsigned long long watermark_tick = 0; \ 458 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 459 dm_get_timestamp(dc->ctx) : 0 460 461 #define BW_VAL_TRACE_COUNT() \ 462 if (dc->debug.bw_val_profile.enable) \ 463 dc->debug.bw_val_profile.total_count++ 464 465 #define BW_VAL_TRACE_SKIP(status) \ 466 if (dc->debug.bw_val_profile.enable) { \ 467 if (!voltage_level_tick) \ 468 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 469 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 470 } 471 472 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 473 if (dc->debug.bw_val_profile.enable) \ 474 voltage_level_tick = dm_get_timestamp(dc->ctx) 475 476 #define BW_VAL_TRACE_END_WATERMARKS() \ 477 if (dc->debug.bw_val_profile.enable) \ 478 watermark_tick = dm_get_timestamp(dc->ctx) 479 480 #define BW_VAL_TRACE_FINISH() \ 481 if (dc->debug.bw_val_profile.enable) { \ 482 end_tick = dm_get_timestamp(dc->ctx); \ 483 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 484 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 485 if (watermark_tick) { \ 486 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 487 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 488 } \ 489 } 490 491 union mem_low_power_enable_options { 492 struct { 493 bool vga: 1; 494 bool i2c: 1; 495 bool dmcu: 1; 496 bool dscl: 1; 497 bool cm: 1; 498 bool mpc: 1; 499 bool optc: 1; 500 bool vpg: 1; 501 bool afmt: 1; 502 } bits; 503 uint32_t u32All; 504 }; 505 506 union root_clock_optimization_options { 507 struct { 508 bool dpp: 1; 509 bool dsc: 1; 510 bool hdmistream: 1; 511 bool hdmichar: 1; 512 bool dpstream: 1; 513 bool symclk32_se: 1; 514 bool symclk32_le: 1; 515 bool symclk_fe: 1; 516 bool physymclk: 1; 517 bool dpiasymclk: 1; 518 uint32_t reserved: 22; 519 } bits; 520 uint32_t u32All; 521 }; 522 523 union dpia_debug_options { 524 struct { 525 uint32_t disable_dpia:1; /* bit 0 */ 526 uint32_t force_non_lttpr:1; /* bit 1 */ 527 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 528 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 529 uint32_t hpd_delay_in_ms:12; /* bits 4-15 */ 530 uint32_t disable_force_tbt3_work_around:1; /* bit 16 */ 531 uint32_t reserved:15; 532 } bits; 533 uint32_t raw; 534 }; 535 536 /* AUX wake work around options 537 * 0: enable/disable work around 538 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 539 * 15-2: reserved 540 * 31-16: timeout in ms 541 */ 542 union aux_wake_wa_options { 543 struct { 544 uint32_t enable_wa : 1; 545 uint32_t use_default_timeout : 1; 546 uint32_t rsvd: 14; 547 uint32_t timeout_ms : 16; 548 } bits; 549 uint32_t raw; 550 }; 551 552 struct dc_debug_data { 553 uint32_t ltFailCount; 554 uint32_t i2cErrorCount; 555 uint32_t auxErrorCount; 556 }; 557 558 struct dc_phy_addr_space_config { 559 struct { 560 uint64_t start_addr; 561 uint64_t end_addr; 562 uint64_t fb_top; 563 uint64_t fb_offset; 564 uint64_t fb_base; 565 uint64_t agp_top; 566 uint64_t agp_bot; 567 uint64_t agp_base; 568 } system_aperture; 569 570 struct { 571 uint64_t page_table_start_addr; 572 uint64_t page_table_end_addr; 573 uint64_t page_table_base_addr; 574 bool base_addr_is_mc_addr; 575 } gart_config; 576 577 bool valid; 578 bool is_hvm_enabled; 579 uint64_t page_table_default_page_addr; 580 }; 581 582 struct dc_virtual_addr_space_config { 583 uint64_t page_table_base_addr; 584 uint64_t page_table_start_addr; 585 uint64_t page_table_end_addr; 586 uint32_t page_table_block_size_in_bytes; 587 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 588 }; 589 590 struct dc_bounding_box_overrides { 591 int sr_exit_time_ns; 592 int sr_enter_plus_exit_time_ns; 593 int urgent_latency_ns; 594 int percent_of_ideal_drambw; 595 int dram_clock_change_latency_ns; 596 int dummy_clock_change_latency_ns; 597 /* This forces a hard min on the DCFCLK we use 598 * for DML. Unlike the debug option for forcing 599 * DCFCLK, this override affects watermark calculations 600 */ 601 int min_dcfclk_mhz; 602 }; 603 604 struct dc_state; 605 struct resource_pool; 606 struct dce_hwseq; 607 608 struct dc_debug_options { 609 bool native422_support; 610 bool disable_dsc; 611 enum visual_confirm visual_confirm; 612 int visual_confirm_rect_height; 613 614 bool sanity_checks; 615 bool max_disp_clk; 616 bool surface_trace; 617 bool timing_trace; 618 bool clock_trace; 619 bool validation_trace; 620 bool bandwidth_calcs_trace; 621 int max_downscale_src_width; 622 623 /* stutter efficiency related */ 624 bool disable_stutter; 625 bool use_max_lb; 626 enum dcc_option disable_dcc; 627 enum pipe_split_policy pipe_split_policy; 628 bool force_single_disp_pipe_split; 629 bool voltage_align_fclk; 630 bool disable_min_fclk; 631 632 bool disable_dfs_bypass; 633 bool disable_dpp_power_gate; 634 bool disable_hubp_power_gate; 635 bool disable_dsc_power_gate; 636 int dsc_min_slice_height_override; 637 int dsc_bpp_increment_div; 638 bool disable_pplib_wm_range; 639 enum wm_report_mode pplib_wm_report_mode; 640 unsigned int min_disp_clk_khz; 641 unsigned int min_dpp_clk_khz; 642 unsigned int min_dram_clk_khz; 643 int sr_exit_time_dpm0_ns; 644 int sr_enter_plus_exit_time_dpm0_ns; 645 int sr_exit_time_ns; 646 int sr_enter_plus_exit_time_ns; 647 int urgent_latency_ns; 648 uint32_t underflow_assert_delay_us; 649 int percent_of_ideal_drambw; 650 int dram_clock_change_latency_ns; 651 bool optimized_watermark; 652 int always_scale; 653 bool disable_pplib_clock_request; 654 bool disable_clock_gate; 655 bool disable_mem_low_power; 656 #if defined(CONFIG_DRM_AMD_DC_DCN) 657 bool pstate_enabled; 658 #endif 659 bool disable_dmcu; 660 bool disable_psr; 661 bool force_abm_enable; 662 bool disable_stereo_support; 663 bool vsr_support; 664 bool performance_trace; 665 bool az_endpoint_mute_only; 666 bool always_use_regamma; 667 bool recovery_enabled; 668 bool avoid_vbios_exec_table; 669 bool scl_reset_length10; 670 bool hdmi20_disable; 671 bool skip_detection_link_training; 672 uint32_t edid_read_retry_times; 673 bool remove_disconnect_edp; 674 unsigned int force_odm_combine; //bit vector based on otg inst 675 unsigned int seamless_boot_odm_combine; 676 #if defined(CONFIG_DRM_AMD_DC_DCN) 677 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 678 bool disable_z9_mpc; 679 #endif 680 unsigned int force_fclk_khz; 681 bool enable_tri_buf; 682 bool dmub_offload_enabled; 683 bool dmcub_emulation; 684 #if defined(CONFIG_DRM_AMD_DC_DCN) 685 bool disable_idle_power_optimizations; 686 unsigned int mall_size_override; 687 unsigned int mall_additional_timer_percent; 688 bool mall_error_as_fatal; 689 #endif 690 bool dmub_command_table; /* for testing only */ 691 struct dc_bw_validation_profile bw_val_profile; 692 bool disable_fec; 693 bool disable_48mhz_pwrdwn; 694 /* This forces a hard min on the DCFCLK requested to SMU/PP 695 * watermarks are not affected. 696 */ 697 unsigned int force_min_dcfclk_mhz; 698 #if defined(CONFIG_DRM_AMD_DC_DCN) 699 int dwb_fi_phase; 700 #endif 701 bool disable_timing_sync; 702 bool cm_in_bypass; 703 int force_clock_mode;/*every mode change.*/ 704 705 bool disable_dram_clock_change_vactive_support; 706 bool validate_dml_output; 707 bool enable_dmcub_surface_flip; 708 bool usbc_combo_phy_reset_wa; 709 bool disable_dsc_edp; 710 unsigned int force_dsc_edp_policy; 711 bool enable_dram_clock_change_one_display_vactive; 712 /* TODO - remove once tested */ 713 bool legacy_dp2_lt; 714 bool set_mst_en_for_sst; 715 bool disable_uhbr; 716 bool force_dp2_lt_fallback_method; 717 bool ignore_cable_id; 718 union mem_low_power_enable_options enable_mem_low_power; 719 union root_clock_optimization_options root_clock_optimization; 720 bool hpo_optimization; 721 bool force_vblank_alignment; 722 723 /* Enable dmub aux for legacy ddc */ 724 bool enable_dmub_aux_for_legacy_ddc; 725 bool optimize_edp_link_rate; /* eDP ILR */ 726 /* FEC/PSR1 sequence enable delay in 100us */ 727 uint8_t fec_enable_delay_in100us; 728 bool enable_driver_sequence_debug; 729 enum det_size crb_alloc_policy; 730 int crb_alloc_policy_min_disp_count; 731 bool disable_z10; 732 #if defined(CONFIG_DRM_AMD_DC_DCN) 733 bool enable_z9_disable_interface; 734 bool enable_sw_cntl_psr; 735 union dpia_debug_options dpia_debug; 736 #endif 737 bool apply_vendor_specific_lttpr_wa; 738 bool extended_blank_optimization; 739 union aux_wake_wa_options aux_wake_wa; 740 uint8_t psr_power_use_phy_fsm; 741 enum dml_hostvm_override_opts dml_hostvm_override; 742 }; 743 744 struct gpu_info_soc_bounding_box_v1_0; 745 struct dc { 746 struct dc_debug_options debug; 747 struct dc_versions versions; 748 struct dc_caps caps; 749 struct dc_cap_funcs cap_funcs; 750 struct dc_config config; 751 struct dc_bounding_box_overrides bb_overrides; 752 struct dc_bug_wa work_arounds; 753 struct dc_context *ctx; 754 struct dc_phy_addr_space_config vm_pa_config; 755 756 uint8_t link_count; 757 struct dc_link *links[MAX_PIPES * 2]; 758 759 struct dc_state *current_state; 760 struct resource_pool *res_pool; 761 762 struct clk_mgr *clk_mgr; 763 764 /* Display Engine Clock levels */ 765 struct dm_pp_clock_levels sclk_lvls; 766 767 /* Inputs into BW and WM calculations. */ 768 struct bw_calcs_dceip *bw_dceip; 769 struct bw_calcs_vbios *bw_vbios; 770 #ifdef CONFIG_DRM_AMD_DC_DCN 771 struct dcn_soc_bounding_box *dcn_soc; 772 struct dcn_ip_params *dcn_ip; 773 struct display_mode_lib dml; 774 #endif 775 776 /* HW functions */ 777 struct hw_sequencer_funcs hwss; 778 struct dce_hwseq *hwseq; 779 780 /* Require to optimize clocks and bandwidth for added/removed planes */ 781 bool optimized_required; 782 bool wm_optimized_required; 783 #if defined(CONFIG_DRM_AMD_DC_DCN) 784 bool idle_optimizations_allowed; 785 #endif 786 #if defined(CONFIG_DRM_AMD_DC_DCN) 787 bool enable_c20_dtm_b0; 788 #endif 789 790 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 791 792 /* FBC compressor */ 793 struct compressor *fbc_compressor; 794 795 struct dc_debug_data debug_data; 796 struct dpcd_vendor_signature vendor_signature; 797 798 const char *build_id; 799 struct vm_helper *vm_helper; 800 }; 801 802 enum frame_buffer_mode { 803 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 804 FRAME_BUFFER_MODE_ZFB_ONLY, 805 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 806 } ; 807 808 struct dchub_init_data { 809 int64_t zfb_phys_addr_base; 810 int64_t zfb_mc_base_addr; 811 uint64_t zfb_size_in_byte; 812 enum frame_buffer_mode fb_mode; 813 bool dchub_initialzied; 814 bool dchub_info_valid; 815 }; 816 817 struct dc_init_data { 818 struct hw_asic_id asic_id; 819 void *driver; /* ctx */ 820 struct cgs_device *cgs_device; 821 struct dc_bounding_box_overrides bb_overrides; 822 823 int num_virtual_links; 824 /* 825 * If 'vbios_override' not NULL, it will be called instead 826 * of the real VBIOS. Intended use is Diagnostics on FPGA. 827 */ 828 struct dc_bios *vbios_override; 829 enum dce_environment dce_environment; 830 831 struct dmub_offload_funcs *dmub_if; 832 struct dc_reg_helper_state *dmub_offload; 833 834 struct dc_config flags; 835 uint64_t log_mask; 836 837 struct dpcd_vendor_signature vendor_signature; 838 #if defined(CONFIG_DRM_AMD_DC_DCN) 839 bool force_smu_not_present; 840 #endif 841 }; 842 843 struct dc_callback_init { 844 #ifdef CONFIG_DRM_AMD_DC_HDCP 845 struct cp_psp cp_psp; 846 #else 847 uint8_t reserved; 848 #endif 849 }; 850 851 struct dc *dc_create(const struct dc_init_data *init_params); 852 void dc_hardware_init(struct dc *dc); 853 854 int dc_get_vmid_use_vector(struct dc *dc); 855 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 856 /* Returns the number of vmids supported */ 857 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 858 void dc_init_callbacks(struct dc *dc, 859 const struct dc_callback_init *init_params); 860 void dc_deinit_callbacks(struct dc *dc); 861 void dc_destroy(struct dc **dc); 862 863 /******************************************************************************* 864 * Surface Interfaces 865 ******************************************************************************/ 866 867 enum { 868 TRANSFER_FUNC_POINTS = 1025 869 }; 870 871 struct dc_hdr_static_metadata { 872 /* display chromaticities and white point in units of 0.00001 */ 873 unsigned int chromaticity_green_x; 874 unsigned int chromaticity_green_y; 875 unsigned int chromaticity_blue_x; 876 unsigned int chromaticity_blue_y; 877 unsigned int chromaticity_red_x; 878 unsigned int chromaticity_red_y; 879 unsigned int chromaticity_white_point_x; 880 unsigned int chromaticity_white_point_y; 881 882 uint32_t min_luminance; 883 uint32_t max_luminance; 884 uint32_t maximum_content_light_level; 885 uint32_t maximum_frame_average_light_level; 886 }; 887 888 enum dc_transfer_func_type { 889 TF_TYPE_PREDEFINED, 890 TF_TYPE_DISTRIBUTED_POINTS, 891 TF_TYPE_BYPASS, 892 TF_TYPE_HWPWL 893 }; 894 895 struct dc_transfer_func_distributed_points { 896 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 897 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 898 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 899 900 uint16_t end_exponent; 901 uint16_t x_point_at_y1_red; 902 uint16_t x_point_at_y1_green; 903 uint16_t x_point_at_y1_blue; 904 }; 905 906 enum dc_transfer_func_predefined { 907 TRANSFER_FUNCTION_SRGB, 908 TRANSFER_FUNCTION_BT709, 909 TRANSFER_FUNCTION_PQ, 910 TRANSFER_FUNCTION_LINEAR, 911 TRANSFER_FUNCTION_UNITY, 912 TRANSFER_FUNCTION_HLG, 913 TRANSFER_FUNCTION_HLG12, 914 TRANSFER_FUNCTION_GAMMA22, 915 TRANSFER_FUNCTION_GAMMA24, 916 TRANSFER_FUNCTION_GAMMA26 917 }; 918 919 920 struct dc_transfer_func { 921 struct kref refcount; 922 enum dc_transfer_func_type type; 923 enum dc_transfer_func_predefined tf; 924 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 925 uint32_t sdr_ref_white_level; 926 union { 927 struct pwl_params pwl; 928 struct dc_transfer_func_distributed_points tf_pts; 929 }; 930 }; 931 932 933 union dc_3dlut_state { 934 struct { 935 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 936 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 937 uint32_t rmu_mux_num:3; /*index of mux to use*/ 938 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 939 uint32_t mpc_rmu1_mux:4; 940 uint32_t mpc_rmu2_mux:4; 941 uint32_t reserved:15; 942 } bits; 943 uint32_t raw; 944 }; 945 946 947 struct dc_3dlut { 948 struct kref refcount; 949 struct tetrahedral_params lut_3d; 950 struct fixed31_32 hdr_multiplier; 951 union dc_3dlut_state state; 952 }; 953 /* 954 * This structure is filled in by dc_surface_get_status and contains 955 * the last requested address and the currently active address so the called 956 * can determine if there are any outstanding flips 957 */ 958 struct dc_plane_status { 959 struct dc_plane_address requested_address; 960 struct dc_plane_address current_address; 961 bool is_flip_pending; 962 bool is_right_eye; 963 }; 964 965 union surface_update_flags { 966 967 struct { 968 uint32_t addr_update:1; 969 /* Medium updates */ 970 uint32_t dcc_change:1; 971 uint32_t color_space_change:1; 972 uint32_t horizontal_mirror_change:1; 973 uint32_t per_pixel_alpha_change:1; 974 uint32_t global_alpha_change:1; 975 uint32_t hdr_mult:1; 976 uint32_t rotation_change:1; 977 uint32_t swizzle_change:1; 978 uint32_t scaling_change:1; 979 uint32_t position_change:1; 980 uint32_t in_transfer_func_change:1; 981 uint32_t input_csc_change:1; 982 uint32_t coeff_reduction_change:1; 983 uint32_t output_tf_change:1; 984 uint32_t pixel_format_change:1; 985 uint32_t plane_size_change:1; 986 uint32_t gamut_remap_change:1; 987 988 /* Full updates */ 989 uint32_t new_plane:1; 990 uint32_t bpp_change:1; 991 uint32_t gamma_change:1; 992 uint32_t bandwidth_change:1; 993 uint32_t clock_change:1; 994 uint32_t stereo_format_change:1; 995 uint32_t lut_3d:1; 996 uint32_t full_update:1; 997 } bits; 998 999 uint32_t raw; 1000 }; 1001 1002 struct dc_plane_state { 1003 struct dc_plane_address address; 1004 struct dc_plane_flip_time time; 1005 bool triplebuffer_flips; 1006 struct scaling_taps scaling_quality; 1007 struct rect src_rect; 1008 struct rect dst_rect; 1009 struct rect clip_rect; 1010 1011 struct plane_size plane_size; 1012 union dc_tiling_info tiling_info; 1013 1014 struct dc_plane_dcc_param dcc; 1015 1016 struct dc_gamma *gamma_correction; 1017 struct dc_transfer_func *in_transfer_func; 1018 struct dc_bias_and_scale *bias_and_scale; 1019 struct dc_csc_transform input_csc_color_matrix; 1020 struct fixed31_32 coeff_reduction_factor; 1021 struct fixed31_32 hdr_mult; 1022 struct colorspace_transform gamut_remap_matrix; 1023 1024 // TODO: No longer used, remove 1025 struct dc_hdr_static_metadata hdr_static_ctx; 1026 1027 enum dc_color_space color_space; 1028 1029 struct dc_3dlut *lut3d_func; 1030 struct dc_transfer_func *in_shaper_func; 1031 struct dc_transfer_func *blend_tf; 1032 1033 #if defined(CONFIG_DRM_AMD_DC_DCN) 1034 struct dc_transfer_func *gamcor_tf; 1035 #endif 1036 enum surface_pixel_format format; 1037 enum dc_rotation_angle rotation; 1038 enum plane_stereo_format stereo_format; 1039 1040 bool is_tiling_rotated; 1041 bool per_pixel_alpha; 1042 bool global_alpha; 1043 int global_alpha_value; 1044 bool visible; 1045 bool flip_immediate; 1046 bool horizontal_mirror; 1047 int layer_index; 1048 1049 union surface_update_flags update_flags; 1050 bool flip_int_enabled; 1051 bool skip_manual_trigger; 1052 1053 /* private to DC core */ 1054 struct dc_plane_status status; 1055 struct dc_context *ctx; 1056 1057 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1058 bool force_full_update; 1059 1060 /* private to dc_surface.c */ 1061 enum dc_irq_source irq_source; 1062 struct kref refcount; 1063 }; 1064 1065 struct dc_plane_info { 1066 struct plane_size plane_size; 1067 union dc_tiling_info tiling_info; 1068 struct dc_plane_dcc_param dcc; 1069 enum surface_pixel_format format; 1070 enum dc_rotation_angle rotation; 1071 enum plane_stereo_format stereo_format; 1072 enum dc_color_space color_space; 1073 bool horizontal_mirror; 1074 bool visible; 1075 bool per_pixel_alpha; 1076 bool global_alpha; 1077 int global_alpha_value; 1078 bool input_csc_enabled; 1079 int layer_index; 1080 }; 1081 1082 struct dc_scaling_info { 1083 struct rect src_rect; 1084 struct rect dst_rect; 1085 struct rect clip_rect; 1086 struct scaling_taps scaling_quality; 1087 }; 1088 1089 struct dc_surface_update { 1090 struct dc_plane_state *surface; 1091 1092 /* isr safe update parameters. null means no updates */ 1093 const struct dc_flip_addrs *flip_addr; 1094 const struct dc_plane_info *plane_info; 1095 const struct dc_scaling_info *scaling_info; 1096 struct fixed31_32 hdr_mult; 1097 /* following updates require alloc/sleep/spin that is not isr safe, 1098 * null means no updates 1099 */ 1100 const struct dc_gamma *gamma; 1101 const struct dc_transfer_func *in_transfer_func; 1102 1103 const struct dc_csc_transform *input_csc_color_matrix; 1104 const struct fixed31_32 *coeff_reduction_factor; 1105 const struct dc_transfer_func *func_shaper; 1106 const struct dc_3dlut *lut3d_func; 1107 const struct dc_transfer_func *blend_tf; 1108 const struct colorspace_transform *gamut_remap_matrix; 1109 }; 1110 1111 /* 1112 * Create a new surface with default parameters; 1113 */ 1114 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1115 const struct dc_plane_status *dc_plane_get_status( 1116 const struct dc_plane_state *plane_state); 1117 1118 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1119 void dc_plane_state_release(struct dc_plane_state *plane_state); 1120 1121 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1122 void dc_gamma_release(struct dc_gamma **dc_gamma); 1123 struct dc_gamma *dc_create_gamma(void); 1124 1125 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1126 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1127 struct dc_transfer_func *dc_create_transfer_func(void); 1128 1129 struct dc_3dlut *dc_create_3dlut_func(void); 1130 void dc_3dlut_func_release(struct dc_3dlut *lut); 1131 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1132 /* 1133 * This structure holds a surface address. There could be multiple addresses 1134 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1135 * as frame durations and DCC format can also be set. 1136 */ 1137 struct dc_flip_addrs { 1138 struct dc_plane_address address; 1139 unsigned int flip_timestamp_in_us; 1140 bool flip_immediate; 1141 /* TODO: add flip duration for FreeSync */ 1142 bool triplebuffer_flips; 1143 }; 1144 1145 void dc_post_update_surfaces_to_stream( 1146 struct dc *dc); 1147 1148 #include "dc_stream.h" 1149 1150 /* 1151 * Structure to store surface/stream associations for validation 1152 */ 1153 struct dc_validation_set { 1154 struct dc_stream_state *stream; 1155 struct dc_plane_state *plane_states[MAX_SURFACES]; 1156 uint8_t plane_count; 1157 }; 1158 1159 bool dc_validate_boot_timing(const struct dc *dc, 1160 const struct dc_sink *sink, 1161 struct dc_crtc_timing *crtc_timing); 1162 1163 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1164 1165 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1166 1167 bool dc_set_generic_gpio_for_stereo(bool enable, 1168 struct gpio_service *gpio_service); 1169 1170 /* 1171 * fast_validate: we return after determining if we can support the new state, 1172 * but before we populate the programming info 1173 */ 1174 enum dc_status dc_validate_global_state( 1175 struct dc *dc, 1176 struct dc_state *new_ctx, 1177 bool fast_validate); 1178 1179 1180 void dc_resource_state_construct( 1181 const struct dc *dc, 1182 struct dc_state *dst_ctx); 1183 1184 #if defined(CONFIG_DRM_AMD_DC_DCN) 1185 bool dc_acquire_release_mpc_3dlut( 1186 struct dc *dc, bool acquire, 1187 struct dc_stream_state *stream, 1188 struct dc_3dlut **lut, 1189 struct dc_transfer_func **shaper); 1190 #endif 1191 1192 void dc_resource_state_copy_construct( 1193 const struct dc_state *src_ctx, 1194 struct dc_state *dst_ctx); 1195 1196 void dc_resource_state_copy_construct_current( 1197 const struct dc *dc, 1198 struct dc_state *dst_ctx); 1199 1200 void dc_resource_state_destruct(struct dc_state *context); 1201 1202 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1203 1204 /* 1205 * TODO update to make it about validation sets 1206 * Set up streams and links associated to drive sinks 1207 * The streams parameter is an absolute set of all active streams. 1208 * 1209 * After this call: 1210 * Phy, Encoder, Timing Generator are programmed and enabled. 1211 * New streams are enabled with blank stream; no memory read. 1212 */ 1213 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1214 1215 struct dc_state *dc_create_state(struct dc *dc); 1216 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1217 void dc_retain_state(struct dc_state *context); 1218 void dc_release_state(struct dc_state *context); 1219 1220 /******************************************************************************* 1221 * Link Interfaces 1222 ******************************************************************************/ 1223 1224 struct dpcd_caps { 1225 union dpcd_rev dpcd_rev; 1226 union max_lane_count max_ln_count; 1227 union max_down_spread max_down_spread; 1228 union dprx_feature dprx_feature; 1229 1230 /* valid only for eDP v1.4 or higher*/ 1231 uint8_t edp_supported_link_rates_count; 1232 enum dc_link_rate edp_supported_link_rates[8]; 1233 1234 /* dongle type (DP converter, CV smart dongle) */ 1235 enum display_dongle_type dongle_type; 1236 bool is_dongle_type_one; 1237 /* branch device or sink device */ 1238 bool is_branch_dev; 1239 /* Dongle's downstream count. */ 1240 union sink_count sink_count; 1241 bool is_mst_capable; 1242 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1243 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1244 struct dc_dongle_caps dongle_caps; 1245 1246 uint32_t sink_dev_id; 1247 int8_t sink_dev_id_str[6]; 1248 int8_t sink_hw_revision; 1249 int8_t sink_fw_revision[2]; 1250 1251 uint32_t branch_dev_id; 1252 int8_t branch_dev_name[6]; 1253 int8_t branch_hw_revision; 1254 int8_t branch_fw_revision[2]; 1255 1256 bool allow_invalid_MSA_timing_param; 1257 bool panel_mode_edp; 1258 bool dpcd_display_control_capable; 1259 bool ext_receiver_cap_field_present; 1260 bool dynamic_backlight_capable_edp; 1261 union dpcd_fec_capability fec_cap; 1262 struct dpcd_dsc_capabilities dsc_caps; 1263 struct dc_lttpr_caps lttpr_caps; 1264 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1265 1266 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1267 union dp_main_line_channel_coding_cap channel_coding_cap; 1268 union dp_sink_video_fallback_formats fallback_formats; 1269 union dp_fec_capability1 fec_cap1; 1270 union dp_cable_id cable_id; 1271 uint8_t edp_rev; 1272 union edp_alpm_caps alpm_caps; 1273 struct edp_psr_info psr_info; 1274 }; 1275 1276 union dpcd_sink_ext_caps { 1277 struct { 1278 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1279 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1280 */ 1281 uint8_t sdr_aux_backlight_control : 1; 1282 uint8_t hdr_aux_backlight_control : 1; 1283 uint8_t reserved_1 : 2; 1284 uint8_t oled : 1; 1285 uint8_t reserved : 3; 1286 } bits; 1287 uint8_t raw; 1288 }; 1289 1290 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1291 union hdcp_rx_caps { 1292 struct { 1293 uint8_t version; 1294 uint8_t reserved; 1295 struct { 1296 uint8_t repeater : 1; 1297 uint8_t hdcp_capable : 1; 1298 uint8_t reserved : 6; 1299 } byte0; 1300 } fields; 1301 uint8_t raw[3]; 1302 }; 1303 1304 union hdcp_bcaps { 1305 struct { 1306 uint8_t HDCP_CAPABLE:1; 1307 uint8_t REPEATER:1; 1308 uint8_t RESERVED:6; 1309 } bits; 1310 uint8_t raw; 1311 }; 1312 1313 struct hdcp_caps { 1314 union hdcp_rx_caps rx_caps; 1315 union hdcp_bcaps bcaps; 1316 }; 1317 #endif 1318 1319 #include "dc_link.h" 1320 1321 #if defined(CONFIG_DRM_AMD_DC_DCN) 1322 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1323 1324 #endif 1325 /******************************************************************************* 1326 * Sink Interfaces - A sink corresponds to a display output device 1327 ******************************************************************************/ 1328 1329 struct dc_container_id { 1330 // 128bit GUID in binary form 1331 unsigned char guid[16]; 1332 // 8 byte port ID -> ELD.PortID 1333 unsigned int portId[2]; 1334 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1335 unsigned short manufacturerName; 1336 // 2 byte product code -> ELD.ProductCode 1337 unsigned short productCode; 1338 }; 1339 1340 1341 struct dc_sink_dsc_caps { 1342 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1343 // 'false' if they are sink's DSC caps 1344 bool is_virtual_dpcd_dsc; 1345 #if defined(CONFIG_DRM_AMD_DC_DCN) 1346 // 'true' if MST topology supports DSC passthrough for sink 1347 // 'false' if MST topology does not support DSC passthrough 1348 bool is_dsc_passthrough_supported; 1349 #endif 1350 struct dsc_dec_dpcd_caps dsc_dec_caps; 1351 }; 1352 1353 struct dc_sink_fec_caps { 1354 bool is_rx_fec_supported; 1355 bool is_topology_fec_supported; 1356 }; 1357 1358 /* 1359 * The sink structure contains EDID and other display device properties 1360 */ 1361 struct dc_sink { 1362 enum signal_type sink_signal; 1363 struct dc_edid dc_edid; /* raw edid */ 1364 struct dc_edid_caps edid_caps; /* parse display caps */ 1365 struct dc_container_id *dc_container_id; 1366 uint32_t dongle_max_pix_clk; 1367 void *priv; 1368 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1369 bool converter_disable_audio; 1370 1371 struct dc_sink_dsc_caps dsc_caps; 1372 struct dc_sink_fec_caps fec_caps; 1373 1374 bool is_vsc_sdp_colorimetry_supported; 1375 1376 /* private to DC core */ 1377 struct dc_link *link; 1378 struct dc_context *ctx; 1379 1380 uint32_t sink_id; 1381 1382 /* private to dc_sink.c */ 1383 // refcount must be the last member in dc_sink, since we want the 1384 // sink structure to be logically cloneable up to (but not including) 1385 // refcount 1386 struct kref refcount; 1387 }; 1388 1389 void dc_sink_retain(struct dc_sink *sink); 1390 void dc_sink_release(struct dc_sink *sink); 1391 1392 struct dc_sink_init_data { 1393 enum signal_type sink_signal; 1394 struct dc_link *link; 1395 uint32_t dongle_max_pix_clk; 1396 bool converter_disable_audio; 1397 }; 1398 1399 bool dc_extended_blank_supported(struct dc *dc); 1400 1401 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1402 1403 /* Newer interfaces */ 1404 struct dc_cursor { 1405 struct dc_plane_address address; 1406 struct dc_cursor_attributes attributes; 1407 }; 1408 1409 1410 /******************************************************************************* 1411 * Interrupt interfaces 1412 ******************************************************************************/ 1413 enum dc_irq_source dc_interrupt_to_irq_source( 1414 struct dc *dc, 1415 uint32_t src_id, 1416 uint32_t ext_id); 1417 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1418 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1419 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1420 struct dc *dc, uint32_t link_index); 1421 1422 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1423 1424 /******************************************************************************* 1425 * Power Interfaces 1426 ******************************************************************************/ 1427 1428 void dc_set_power_state( 1429 struct dc *dc, 1430 enum dc_acpi_cm_power_state power_state); 1431 void dc_resume(struct dc *dc); 1432 1433 void dc_power_down_on_boot(struct dc *dc); 1434 1435 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1436 /* 1437 * HDCP Interfaces 1438 */ 1439 enum hdcp_message_status dc_process_hdcp_msg( 1440 enum signal_type signal, 1441 struct dc_link *link, 1442 struct hdcp_protection_message *message_info); 1443 #endif 1444 bool dc_is_dmcu_initialized(struct dc *dc); 1445 1446 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1447 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1448 #if defined(CONFIG_DRM_AMD_DC_DCN) 1449 1450 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1451 struct dc_cursor_attributes *cursor_attr); 1452 1453 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1454 1455 /* 1456 * blank all streams, and set min and max memory clock to 1457 * lowest and highest DPM level, respectively 1458 */ 1459 void dc_unlock_memory_clock_frequency(struct dc *dc); 1460 1461 /* 1462 * set min memory clock to the min required for current mode, 1463 * max to maxDPM, and unblank streams 1464 */ 1465 void dc_lock_memory_clock_frequency(struct dc *dc); 1466 1467 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1468 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1469 1470 /* cleanup on driver unload */ 1471 void dc_hardware_release(struct dc *dc); 1472 1473 #endif 1474 1475 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1476 #if defined(CONFIG_DRM_AMD_DC_DCN) 1477 void dc_z10_restore(const struct dc *dc); 1478 void dc_z10_save_init(struct dc *dc); 1479 #endif 1480 1481 bool dc_is_dmub_outbox_supported(struct dc *dc); 1482 bool dc_enable_dmub_notifications(struct dc *dc); 1483 1484 void dc_enable_dmub_outbox(struct dc *dc); 1485 1486 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1487 uint32_t link_index, 1488 struct aux_payload *payload); 1489 1490 /* Get dc link index from dpia port index */ 1491 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1492 uint8_t dpia_port_index); 1493 1494 bool dc_process_dmub_set_config_async(struct dc *dc, 1495 uint32_t link_index, 1496 struct set_config_cmd_payload *payload, 1497 struct dmub_notification *notify); 1498 1499 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1500 uint32_t link_index, 1501 uint8_t mst_alloc_slots, 1502 uint8_t *mst_slots_in_use); 1503 1504 /******************************************************************************* 1505 * DSC Interfaces 1506 ******************************************************************************/ 1507 #include "dc_dsc.h" 1508 1509 /******************************************************************************* 1510 * Disable acc mode Interfaces 1511 ******************************************************************************/ 1512 void dc_disable_accelerated_mode(struct dc *dc); 1513 1514 #endif /* DC_INTERFACE_H_ */ 1515