1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 48 #define DC_VER "3.2.141" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MAX_SINKS_PER_LINK 4 54 #define MIN_VIEWPORT_SIZE 12 55 #define MAX_NUM_EDP 2 56 57 /******************************************************************************* 58 * Display Core Interfaces 59 ******************************************************************************/ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 struct dc_plane_cap { 77 enum dc_plane_type type; 78 uint32_t blends_with_above : 1; 79 uint32_t blends_with_below : 1; 80 uint32_t per_pixel_alpha : 1; 81 struct { 82 uint32_t argb8888 : 1; 83 uint32_t nv12 : 1; 84 uint32_t fp16 : 1; 85 uint32_t p010 : 1; 86 uint32_t ayuv : 1; 87 } pixel_format_support; 88 // max upscaling factor x1000 89 // upscaling factors are always >= 1 90 // for example, 1080p -> 8K is 4.0, or 4000 raw value 91 struct { 92 uint32_t argb8888; 93 uint32_t nv12; 94 uint32_t fp16; 95 } max_upscale_factor; 96 // max downscale factor x1000 97 // downscale factors are always <= 1 98 // for example, 8K -> 1080p is 0.25, or 250 raw value 99 struct { 100 uint32_t argb8888; 101 uint32_t nv12; 102 uint32_t fp16; 103 } max_downscale_factor; 104 // minimal width/height 105 uint32_t min_width; 106 uint32_t min_height; 107 }; 108 109 // Color management caps (DPP and MPC) 110 struct rom_curve_caps { 111 uint16_t srgb : 1; 112 uint16_t bt2020 : 1; 113 uint16_t gamma2_2 : 1; 114 uint16_t pq : 1; 115 uint16_t hlg : 1; 116 }; 117 118 struct dpp_color_caps { 119 uint16_t dcn_arch : 1; // all DCE generations treated the same 120 // input lut is different than most LUTs, just plain 256-entry lookup 121 uint16_t input_lut_shared : 1; // shared with DGAM 122 uint16_t icsc : 1; 123 uint16_t dgam_ram : 1; 124 uint16_t post_csc : 1; // before gamut remap 125 uint16_t gamma_corr : 1; 126 127 // hdr_mult and gamut remap always available in DPP (in that order) 128 // 3d lut implies shaper LUT, 129 // it may be shared with MPC - check MPC:shared_3d_lut flag 130 uint16_t hw_3d_lut : 1; 131 uint16_t ogam_ram : 1; // blnd gam 132 uint16_t ocsc : 1; 133 uint16_t dgam_rom_for_yuv : 1; 134 struct rom_curve_caps dgam_rom_caps; 135 struct rom_curve_caps ogam_rom_caps; 136 }; 137 138 struct mpc_color_caps { 139 uint16_t gamut_remap : 1; 140 uint16_t ogam_ram : 1; 141 uint16_t ocsc : 1; 142 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 143 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 144 145 struct rom_curve_caps ogam_rom_caps; 146 }; 147 148 struct dc_color_caps { 149 struct dpp_color_caps dpp; 150 struct mpc_color_caps mpc; 151 }; 152 153 struct dc_caps { 154 uint32_t max_streams; 155 uint32_t max_links; 156 uint32_t max_audios; 157 uint32_t max_slave_planes; 158 uint32_t max_slave_yuv_planes; 159 uint32_t max_slave_rgb_planes; 160 uint32_t max_planes; 161 uint32_t max_downscale_ratio; 162 uint32_t i2c_speed_in_khz; 163 uint32_t i2c_speed_in_khz_hdcp; 164 uint32_t dmdata_alloc_size; 165 unsigned int max_cursor_size; 166 unsigned int max_video_width; 167 unsigned int min_horizontal_blanking_period; 168 int linear_pitch_alignment; 169 bool dcc_const_color; 170 bool dynamic_audio; 171 bool is_apu; 172 bool dual_link_dvi; 173 bool post_blend_color_processing; 174 bool force_dp_tps4_for_cp2520; 175 bool disable_dp_clk_share; 176 bool psp_setup_panel_mode; 177 bool extended_aux_timeout_support; 178 bool dmcub_support; 179 uint32_t num_of_internal_disp; 180 enum dp_protocol_version max_dp_protocol_version; 181 unsigned int mall_size_per_mem_channel; 182 unsigned int mall_size_total; 183 unsigned int cursor_cache_size; 184 struct dc_plane_cap planes[MAX_PLANES]; 185 struct dc_color_caps color; 186 }; 187 188 struct dc_bug_wa { 189 bool no_connect_phy_config; 190 bool dedcn20_305_wa; 191 bool skip_clock_update; 192 bool lt_early_cr_pattern; 193 }; 194 195 struct dc_dcc_surface_param { 196 struct dc_size surface_size; 197 enum surface_pixel_format format; 198 enum swizzle_mode_values swizzle_mode; 199 enum dc_scan_direction scan; 200 }; 201 202 struct dc_dcc_setting { 203 unsigned int max_compressed_blk_size; 204 unsigned int max_uncompressed_blk_size; 205 bool independent_64b_blks; 206 #if defined(CONFIG_DRM_AMD_DC_DCN) 207 //These bitfields to be used starting with DCN 3.0 208 struct { 209 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 210 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 211 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 212 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 213 } dcc_controls; 214 #endif 215 }; 216 217 struct dc_surface_dcc_cap { 218 union { 219 struct { 220 struct dc_dcc_setting rgb; 221 } grph; 222 223 struct { 224 struct dc_dcc_setting luma; 225 struct dc_dcc_setting chroma; 226 } video; 227 }; 228 229 bool capable; 230 bool const_color_support; 231 }; 232 233 struct dc_static_screen_params { 234 struct { 235 bool force_trigger; 236 bool cursor_update; 237 bool surface_update; 238 bool overlay_update; 239 } triggers; 240 unsigned int num_frames; 241 }; 242 243 244 /* Surface update type is used by dc_update_surfaces_and_stream 245 * The update type is determined at the very beginning of the function based 246 * on parameters passed in and decides how much programming (or updating) is 247 * going to be done during the call. 248 * 249 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 250 * logical calculations or hardware register programming. This update MUST be 251 * ISR safe on windows. Currently fast update will only be used to flip surface 252 * address. 253 * 254 * UPDATE_TYPE_MED is used for slower updates which require significant hw 255 * re-programming however do not affect bandwidth consumption or clock 256 * requirements. At present, this is the level at which front end updates 257 * that do not require us to run bw_calcs happen. These are in/out transfer func 258 * updates, viewport offset changes, recout size changes and pixel depth changes. 259 * This update can be done at ISR, but we want to minimize how often this happens. 260 * 261 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 262 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 263 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 264 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 265 * a full update. This cannot be done at ISR level and should be a rare event. 266 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 267 * underscan we don't expect to see this call at all. 268 */ 269 270 enum surface_update_type { 271 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 272 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 273 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 274 }; 275 276 /* Forward declaration*/ 277 struct dc; 278 struct dc_plane_state; 279 struct dc_state; 280 281 282 struct dc_cap_funcs { 283 bool (*get_dcc_compression_cap)(const struct dc *dc, 284 const struct dc_dcc_surface_param *input, 285 struct dc_surface_dcc_cap *output); 286 }; 287 288 struct link_training_settings; 289 290 291 /* Structure to hold configuration flags set by dm at dc creation. */ 292 struct dc_config { 293 bool gpu_vm_support; 294 bool disable_disp_pll_sharing; 295 bool fbc_support; 296 bool disable_fractional_pwm; 297 bool allow_seamless_boot_optimization; 298 bool power_down_display_on_boot; 299 bool edp_not_connected; 300 bool force_enum_edp; 301 bool forced_clocks; 302 bool allow_lttpr_non_transparent_mode; 303 bool multi_mon_pp_mclk_switch; 304 bool disable_dmcu; 305 bool enable_4to1MPC; 306 bool allow_edp_hotplug_detection; 307 #if defined(CONFIG_DRM_AMD_DC_DCN) 308 bool clamp_min_dcfclk; 309 #endif 310 uint64_t vblank_alignment_dto_params; 311 uint8_t vblank_alignment_max_frame_time_diff; 312 bool is_asymmetric_memory; 313 bool is_single_rank_dimm; 314 }; 315 316 enum visual_confirm { 317 VISUAL_CONFIRM_DISABLE = 0, 318 VISUAL_CONFIRM_SURFACE = 1, 319 VISUAL_CONFIRM_HDR = 2, 320 VISUAL_CONFIRM_MPCTREE = 4, 321 VISUAL_CONFIRM_PSR = 5, 322 VISUAL_CONFIRM_SWIZZLE = 9, 323 }; 324 325 enum dcc_option { 326 DCC_ENABLE = 0, 327 DCC_DISABLE = 1, 328 DCC_HALF_REQ_DISALBE = 2, 329 }; 330 331 enum pipe_split_policy { 332 MPC_SPLIT_DYNAMIC = 0, 333 MPC_SPLIT_AVOID = 1, 334 MPC_SPLIT_AVOID_MULT_DISP = 2, 335 }; 336 337 enum wm_report_mode { 338 WM_REPORT_DEFAULT = 0, 339 WM_REPORT_OVERRIDE = 1, 340 }; 341 enum dtm_pstate{ 342 dtm_level_p0 = 0,/*highest voltage*/ 343 dtm_level_p1, 344 dtm_level_p2, 345 dtm_level_p3, 346 dtm_level_p4,/*when active_display_count = 0*/ 347 }; 348 349 enum dcn_pwr_state { 350 DCN_PWR_STATE_UNKNOWN = -1, 351 DCN_PWR_STATE_MISSION_MODE = 0, 352 DCN_PWR_STATE_LOW_POWER = 3, 353 }; 354 355 #if defined(CONFIG_DRM_AMD_DC_DCN) 356 enum dcn_z9_support_state { 357 DCN_Z9_SUPPORT_UNKNOWN, 358 DCN_Z9_SUPPORT_ALLOW, 359 DCN_Z9_SUPPORT_DISALLOW, 360 }; 361 #endif 362 /* 363 * For any clocks that may differ per pipe 364 * only the max is stored in this structure 365 */ 366 struct dc_clocks { 367 int dispclk_khz; 368 int actual_dispclk_khz; 369 int dppclk_khz; 370 int actual_dppclk_khz; 371 int disp_dpp_voltage_level_khz; 372 int dcfclk_khz; 373 int socclk_khz; 374 int dcfclk_deep_sleep_khz; 375 int fclk_khz; 376 int phyclk_khz; 377 int dramclk_khz; 378 bool p_state_change_support; 379 #if defined(CONFIG_DRM_AMD_DC_DCN) 380 enum dcn_z9_support_state z9_support; 381 bool dtbclk_en; 382 #endif 383 enum dcn_pwr_state pwr_state; 384 /* 385 * Elements below are not compared for the purposes of 386 * optimization required 387 */ 388 bool prev_p_state_change_support; 389 enum dtm_pstate dtm_level; 390 int max_supported_dppclk_khz; 391 int max_supported_dispclk_khz; 392 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 393 int bw_dispclk_khz; 394 }; 395 396 struct dc_bw_validation_profile { 397 bool enable; 398 399 unsigned long long total_ticks; 400 unsigned long long voltage_level_ticks; 401 unsigned long long watermark_ticks; 402 unsigned long long rq_dlg_ticks; 403 404 unsigned long long total_count; 405 unsigned long long skip_fast_count; 406 unsigned long long skip_pass_count; 407 unsigned long long skip_fail_count; 408 }; 409 410 #define BW_VAL_TRACE_SETUP() \ 411 unsigned long long end_tick = 0; \ 412 unsigned long long voltage_level_tick = 0; \ 413 unsigned long long watermark_tick = 0; \ 414 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 415 dm_get_timestamp(dc->ctx) : 0 416 417 #define BW_VAL_TRACE_COUNT() \ 418 if (dc->debug.bw_val_profile.enable) \ 419 dc->debug.bw_val_profile.total_count++ 420 421 #define BW_VAL_TRACE_SKIP(status) \ 422 if (dc->debug.bw_val_profile.enable) { \ 423 if (!voltage_level_tick) \ 424 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 425 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 426 } 427 428 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 429 if (dc->debug.bw_val_profile.enable) \ 430 voltage_level_tick = dm_get_timestamp(dc->ctx) 431 432 #define BW_VAL_TRACE_END_WATERMARKS() \ 433 if (dc->debug.bw_val_profile.enable) \ 434 watermark_tick = dm_get_timestamp(dc->ctx) 435 436 #define BW_VAL_TRACE_FINISH() \ 437 if (dc->debug.bw_val_profile.enable) { \ 438 end_tick = dm_get_timestamp(dc->ctx); \ 439 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 440 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 441 if (watermark_tick) { \ 442 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 443 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 444 } \ 445 } 446 447 union mem_low_power_enable_options { 448 struct { 449 bool vga: 1; 450 bool i2c: 1; 451 bool dmcu: 1; 452 bool dscl: 1; 453 bool cm: 1; 454 bool mpc: 1; 455 bool optc: 1; 456 } bits; 457 uint32_t u32All; 458 }; 459 460 struct dc_debug_options { 461 enum visual_confirm visual_confirm; 462 bool sanity_checks; 463 bool max_disp_clk; 464 bool surface_trace; 465 bool timing_trace; 466 bool clock_trace; 467 bool validation_trace; 468 bool bandwidth_calcs_trace; 469 int max_downscale_src_width; 470 471 /* stutter efficiency related */ 472 bool disable_stutter; 473 bool use_max_lb; 474 enum dcc_option disable_dcc; 475 enum pipe_split_policy pipe_split_policy; 476 bool force_single_disp_pipe_split; 477 bool voltage_align_fclk; 478 bool disable_min_fclk; 479 480 bool disable_dfs_bypass; 481 bool disable_dpp_power_gate; 482 bool disable_hubp_power_gate; 483 bool disable_dsc_power_gate; 484 int dsc_min_slice_height_override; 485 int dsc_bpp_increment_div; 486 bool native422_support; 487 bool disable_pplib_wm_range; 488 enum wm_report_mode pplib_wm_report_mode; 489 unsigned int min_disp_clk_khz; 490 unsigned int min_dpp_clk_khz; 491 int sr_exit_time_dpm0_ns; 492 int sr_enter_plus_exit_time_dpm0_ns; 493 int sr_exit_time_ns; 494 int sr_enter_plus_exit_time_ns; 495 int urgent_latency_ns; 496 uint32_t underflow_assert_delay_us; 497 int percent_of_ideal_drambw; 498 int dram_clock_change_latency_ns; 499 bool optimized_watermark; 500 int always_scale; 501 bool disable_pplib_clock_request; 502 bool disable_clock_gate; 503 bool disable_mem_low_power; 504 #if defined(CONFIG_DRM_AMD_DC_DCN) 505 bool pstate_enabled; 506 #endif 507 bool disable_dmcu; 508 bool disable_psr; 509 bool force_abm_enable; 510 bool disable_stereo_support; 511 bool vsr_support; 512 bool performance_trace; 513 bool az_endpoint_mute_only; 514 bool always_use_regamma; 515 bool recovery_enabled; 516 bool avoid_vbios_exec_table; 517 bool scl_reset_length10; 518 bool hdmi20_disable; 519 bool skip_detection_link_training; 520 uint32_t edid_read_retry_times; 521 bool remove_disconnect_edp; 522 unsigned int force_odm_combine; //bit vector based on otg inst 523 #if defined(CONFIG_DRM_AMD_DC_DCN) 524 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 525 bool disable_z9_mpc; 526 #endif 527 unsigned int force_fclk_khz; 528 bool enable_tri_buf; 529 bool dmub_offload_enabled; 530 bool dmcub_emulation; 531 #if defined(CONFIG_DRM_AMD_DC_DCN) 532 bool disable_idle_power_optimizations; 533 unsigned int mall_size_override; 534 unsigned int mall_additional_timer_percent; 535 bool mall_error_as_fatal; 536 #endif 537 bool dmub_command_table; /* for testing only */ 538 struct dc_bw_validation_profile bw_val_profile; 539 bool disable_fec; 540 bool disable_48mhz_pwrdwn; 541 /* This forces a hard min on the DCFCLK requested to SMU/PP 542 * watermarks are not affected. 543 */ 544 unsigned int force_min_dcfclk_mhz; 545 #if defined(CONFIG_DRM_AMD_DC_DCN) 546 int dwb_fi_phase; 547 #endif 548 bool disable_timing_sync; 549 bool cm_in_bypass; 550 int force_clock_mode;/*every mode change.*/ 551 552 bool disable_dram_clock_change_vactive_support; 553 bool validate_dml_output; 554 bool enable_dmcub_surface_flip; 555 bool usbc_combo_phy_reset_wa; 556 bool disable_dsc; 557 bool enable_dram_clock_change_one_display_vactive; 558 union mem_low_power_enable_options enable_mem_low_power; 559 bool force_vblank_alignment; 560 561 /* Enable dmub aux for legacy ddc */ 562 bool enable_dmub_aux_for_legacy_ddc; 563 bool optimize_edp_link_rate; /* eDP ILR */ 564 /* force enable edp FEC */ 565 bool force_enable_edp_fec; 566 /* FEC/PSR1 sequence enable delay in 100us */ 567 uint8_t fec_enable_delay_in100us; 568 #if defined(CONFIG_DRM_AMD_DC_DCN) 569 bool disable_z10; 570 bool enable_sw_cntl_psr; 571 #endif 572 }; 573 574 struct dc_debug_data { 575 uint32_t ltFailCount; 576 uint32_t i2cErrorCount; 577 uint32_t auxErrorCount; 578 }; 579 580 struct dc_phy_addr_space_config { 581 struct { 582 uint64_t start_addr; 583 uint64_t end_addr; 584 uint64_t fb_top; 585 uint64_t fb_offset; 586 uint64_t fb_base; 587 uint64_t agp_top; 588 uint64_t agp_bot; 589 uint64_t agp_base; 590 } system_aperture; 591 592 struct { 593 uint64_t page_table_start_addr; 594 uint64_t page_table_end_addr; 595 uint64_t page_table_base_addr; 596 #if defined(CONFIG_DRM_AMD_DC_DCN) 597 bool base_addr_is_mc_addr; 598 #endif 599 } gart_config; 600 601 bool valid; 602 bool is_hvm_enabled; 603 uint64_t page_table_default_page_addr; 604 }; 605 606 struct dc_virtual_addr_space_config { 607 uint64_t page_table_base_addr; 608 uint64_t page_table_start_addr; 609 uint64_t page_table_end_addr; 610 uint32_t page_table_block_size_in_bytes; 611 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 612 }; 613 614 struct dc_bounding_box_overrides { 615 int sr_exit_time_ns; 616 int sr_enter_plus_exit_time_ns; 617 int urgent_latency_ns; 618 int percent_of_ideal_drambw; 619 int dram_clock_change_latency_ns; 620 int dummy_clock_change_latency_ns; 621 /* This forces a hard min on the DCFCLK we use 622 * for DML. Unlike the debug option for forcing 623 * DCFCLK, this override affects watermark calculations 624 */ 625 int min_dcfclk_mhz; 626 }; 627 628 struct resource_pool; 629 struct dce_hwseq; 630 struct gpu_info_soc_bounding_box_v1_0; 631 struct dc { 632 struct dc_versions versions; 633 struct dc_caps caps; 634 struct dc_cap_funcs cap_funcs; 635 struct dc_config config; 636 struct dc_debug_options debug; 637 struct dc_bounding_box_overrides bb_overrides; 638 struct dc_bug_wa work_arounds; 639 struct dc_context *ctx; 640 struct dc_phy_addr_space_config vm_pa_config; 641 642 uint8_t link_count; 643 struct dc_link *links[MAX_PIPES * 2]; 644 645 struct dc_state *current_state; 646 struct resource_pool *res_pool; 647 648 struct clk_mgr *clk_mgr; 649 650 /* Display Engine Clock levels */ 651 struct dm_pp_clock_levels sclk_lvls; 652 653 /* Inputs into BW and WM calculations. */ 654 struct bw_calcs_dceip *bw_dceip; 655 struct bw_calcs_vbios *bw_vbios; 656 #ifdef CONFIG_DRM_AMD_DC_DCN 657 struct dcn_soc_bounding_box *dcn_soc; 658 struct dcn_ip_params *dcn_ip; 659 struct display_mode_lib dml; 660 #endif 661 662 /* HW functions */ 663 struct hw_sequencer_funcs hwss; 664 struct dce_hwseq *hwseq; 665 666 /* Require to optimize clocks and bandwidth for added/removed planes */ 667 bool optimized_required; 668 bool wm_optimized_required; 669 #if defined(CONFIG_DRM_AMD_DC_DCN) 670 bool idle_optimizations_allowed; 671 #endif 672 673 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 674 675 /* FBC compressor */ 676 struct compressor *fbc_compressor; 677 678 struct dc_debug_data debug_data; 679 struct dpcd_vendor_signature vendor_signature; 680 681 const char *build_id; 682 struct vm_helper *vm_helper; 683 }; 684 685 enum frame_buffer_mode { 686 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 687 FRAME_BUFFER_MODE_ZFB_ONLY, 688 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 689 } ; 690 691 struct dchub_init_data { 692 int64_t zfb_phys_addr_base; 693 int64_t zfb_mc_base_addr; 694 uint64_t zfb_size_in_byte; 695 enum frame_buffer_mode fb_mode; 696 bool dchub_initialzied; 697 bool dchub_info_valid; 698 }; 699 700 struct dc_init_data { 701 struct hw_asic_id asic_id; 702 void *driver; /* ctx */ 703 struct cgs_device *cgs_device; 704 struct dc_bounding_box_overrides bb_overrides; 705 706 int num_virtual_links; 707 /* 708 * If 'vbios_override' not NULL, it will be called instead 709 * of the real VBIOS. Intended use is Diagnostics on FPGA. 710 */ 711 struct dc_bios *vbios_override; 712 enum dce_environment dce_environment; 713 714 struct dmub_offload_funcs *dmub_if; 715 struct dc_reg_helper_state *dmub_offload; 716 717 struct dc_config flags; 718 uint64_t log_mask; 719 720 struct dpcd_vendor_signature vendor_signature; 721 #if defined(CONFIG_DRM_AMD_DC_DCN) 722 bool force_smu_not_present; 723 #endif 724 }; 725 726 struct dc_callback_init { 727 #ifdef CONFIG_DRM_AMD_DC_HDCP 728 struct cp_psp cp_psp; 729 #else 730 uint8_t reserved; 731 #endif 732 }; 733 734 struct dc *dc_create(const struct dc_init_data *init_params); 735 void dc_hardware_init(struct dc *dc); 736 737 int dc_get_vmid_use_vector(struct dc *dc); 738 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 739 /* Returns the number of vmids supported */ 740 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 741 void dc_init_callbacks(struct dc *dc, 742 const struct dc_callback_init *init_params); 743 void dc_deinit_callbacks(struct dc *dc); 744 void dc_destroy(struct dc **dc); 745 746 /******************************************************************************* 747 * Surface Interfaces 748 ******************************************************************************/ 749 750 enum { 751 TRANSFER_FUNC_POINTS = 1025 752 }; 753 754 struct dc_hdr_static_metadata { 755 /* display chromaticities and white point in units of 0.00001 */ 756 unsigned int chromaticity_green_x; 757 unsigned int chromaticity_green_y; 758 unsigned int chromaticity_blue_x; 759 unsigned int chromaticity_blue_y; 760 unsigned int chromaticity_red_x; 761 unsigned int chromaticity_red_y; 762 unsigned int chromaticity_white_point_x; 763 unsigned int chromaticity_white_point_y; 764 765 uint32_t min_luminance; 766 uint32_t max_luminance; 767 uint32_t maximum_content_light_level; 768 uint32_t maximum_frame_average_light_level; 769 }; 770 771 enum dc_transfer_func_type { 772 TF_TYPE_PREDEFINED, 773 TF_TYPE_DISTRIBUTED_POINTS, 774 TF_TYPE_BYPASS, 775 TF_TYPE_HWPWL 776 }; 777 778 struct dc_transfer_func_distributed_points { 779 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 780 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 781 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 782 783 uint16_t end_exponent; 784 uint16_t x_point_at_y1_red; 785 uint16_t x_point_at_y1_green; 786 uint16_t x_point_at_y1_blue; 787 }; 788 789 enum dc_transfer_func_predefined { 790 TRANSFER_FUNCTION_SRGB, 791 TRANSFER_FUNCTION_BT709, 792 TRANSFER_FUNCTION_PQ, 793 TRANSFER_FUNCTION_LINEAR, 794 TRANSFER_FUNCTION_UNITY, 795 TRANSFER_FUNCTION_HLG, 796 TRANSFER_FUNCTION_HLG12, 797 TRANSFER_FUNCTION_GAMMA22, 798 TRANSFER_FUNCTION_GAMMA24, 799 TRANSFER_FUNCTION_GAMMA26 800 }; 801 802 803 struct dc_transfer_func { 804 struct kref refcount; 805 enum dc_transfer_func_type type; 806 enum dc_transfer_func_predefined tf; 807 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 808 uint32_t sdr_ref_white_level; 809 union { 810 struct pwl_params pwl; 811 struct dc_transfer_func_distributed_points tf_pts; 812 }; 813 }; 814 815 816 union dc_3dlut_state { 817 struct { 818 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 819 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 820 uint32_t rmu_mux_num:3; /*index of mux to use*/ 821 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 822 uint32_t mpc_rmu1_mux:4; 823 uint32_t mpc_rmu2_mux:4; 824 uint32_t reserved:15; 825 } bits; 826 uint32_t raw; 827 }; 828 829 830 struct dc_3dlut { 831 struct kref refcount; 832 struct tetrahedral_params lut_3d; 833 struct fixed31_32 hdr_multiplier; 834 union dc_3dlut_state state; 835 }; 836 /* 837 * This structure is filled in by dc_surface_get_status and contains 838 * the last requested address and the currently active address so the called 839 * can determine if there are any outstanding flips 840 */ 841 struct dc_plane_status { 842 struct dc_plane_address requested_address; 843 struct dc_plane_address current_address; 844 bool is_flip_pending; 845 bool is_right_eye; 846 }; 847 848 union surface_update_flags { 849 850 struct { 851 uint32_t addr_update:1; 852 /* Medium updates */ 853 uint32_t dcc_change:1; 854 uint32_t color_space_change:1; 855 uint32_t horizontal_mirror_change:1; 856 uint32_t per_pixel_alpha_change:1; 857 uint32_t global_alpha_change:1; 858 uint32_t hdr_mult:1; 859 uint32_t rotation_change:1; 860 uint32_t swizzle_change:1; 861 uint32_t scaling_change:1; 862 uint32_t position_change:1; 863 uint32_t in_transfer_func_change:1; 864 uint32_t input_csc_change:1; 865 uint32_t coeff_reduction_change:1; 866 uint32_t output_tf_change:1; 867 uint32_t pixel_format_change:1; 868 uint32_t plane_size_change:1; 869 uint32_t gamut_remap_change:1; 870 871 /* Full updates */ 872 uint32_t new_plane:1; 873 uint32_t bpp_change:1; 874 uint32_t gamma_change:1; 875 uint32_t bandwidth_change:1; 876 uint32_t clock_change:1; 877 uint32_t stereo_format_change:1; 878 uint32_t full_update:1; 879 } bits; 880 881 uint32_t raw; 882 }; 883 884 struct dc_plane_state { 885 struct dc_plane_address address; 886 struct dc_plane_flip_time time; 887 bool triplebuffer_flips; 888 struct scaling_taps scaling_quality; 889 struct rect src_rect; 890 struct rect dst_rect; 891 struct rect clip_rect; 892 893 struct plane_size plane_size; 894 union dc_tiling_info tiling_info; 895 896 struct dc_plane_dcc_param dcc; 897 898 struct dc_gamma *gamma_correction; 899 struct dc_transfer_func *in_transfer_func; 900 struct dc_bias_and_scale *bias_and_scale; 901 struct dc_csc_transform input_csc_color_matrix; 902 struct fixed31_32 coeff_reduction_factor; 903 struct fixed31_32 hdr_mult; 904 struct colorspace_transform gamut_remap_matrix; 905 906 // TODO: No longer used, remove 907 struct dc_hdr_static_metadata hdr_static_ctx; 908 909 enum dc_color_space color_space; 910 911 struct dc_3dlut *lut3d_func; 912 struct dc_transfer_func *in_shaper_func; 913 struct dc_transfer_func *blend_tf; 914 915 #if defined(CONFIG_DRM_AMD_DC_DCN) 916 struct dc_transfer_func *gamcor_tf; 917 #endif 918 enum surface_pixel_format format; 919 enum dc_rotation_angle rotation; 920 enum plane_stereo_format stereo_format; 921 922 bool is_tiling_rotated; 923 bool per_pixel_alpha; 924 bool global_alpha; 925 int global_alpha_value; 926 bool visible; 927 bool flip_immediate; 928 bool horizontal_mirror; 929 int layer_index; 930 931 union surface_update_flags update_flags; 932 bool flip_int_enabled; 933 bool skip_manual_trigger; 934 935 /* private to DC core */ 936 struct dc_plane_status status; 937 struct dc_context *ctx; 938 939 /* HACK: Workaround for forcing full reprogramming under some conditions */ 940 bool force_full_update; 941 942 /* private to dc_surface.c */ 943 enum dc_irq_source irq_source; 944 struct kref refcount; 945 }; 946 947 struct dc_plane_info { 948 struct plane_size plane_size; 949 union dc_tiling_info tiling_info; 950 struct dc_plane_dcc_param dcc; 951 enum surface_pixel_format format; 952 enum dc_rotation_angle rotation; 953 enum plane_stereo_format stereo_format; 954 enum dc_color_space color_space; 955 bool horizontal_mirror; 956 bool visible; 957 bool per_pixel_alpha; 958 bool global_alpha; 959 int global_alpha_value; 960 bool input_csc_enabled; 961 int layer_index; 962 }; 963 964 struct dc_scaling_info { 965 struct rect src_rect; 966 struct rect dst_rect; 967 struct rect clip_rect; 968 struct scaling_taps scaling_quality; 969 }; 970 971 struct dc_surface_update { 972 struct dc_plane_state *surface; 973 974 /* isr safe update parameters. null means no updates */ 975 const struct dc_flip_addrs *flip_addr; 976 const struct dc_plane_info *plane_info; 977 const struct dc_scaling_info *scaling_info; 978 struct fixed31_32 hdr_mult; 979 /* following updates require alloc/sleep/spin that is not isr safe, 980 * null means no updates 981 */ 982 const struct dc_gamma *gamma; 983 const struct dc_transfer_func *in_transfer_func; 984 985 const struct dc_csc_transform *input_csc_color_matrix; 986 const struct fixed31_32 *coeff_reduction_factor; 987 const struct dc_transfer_func *func_shaper; 988 const struct dc_3dlut *lut3d_func; 989 const struct dc_transfer_func *blend_tf; 990 const struct colorspace_transform *gamut_remap_matrix; 991 }; 992 993 /* 994 * Create a new surface with default parameters; 995 */ 996 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 997 const struct dc_plane_status *dc_plane_get_status( 998 const struct dc_plane_state *plane_state); 999 1000 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1001 void dc_plane_state_release(struct dc_plane_state *plane_state); 1002 1003 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1004 void dc_gamma_release(struct dc_gamma **dc_gamma); 1005 struct dc_gamma *dc_create_gamma(void); 1006 1007 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1008 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1009 struct dc_transfer_func *dc_create_transfer_func(void); 1010 1011 struct dc_3dlut *dc_create_3dlut_func(void); 1012 void dc_3dlut_func_release(struct dc_3dlut *lut); 1013 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1014 /* 1015 * This structure holds a surface address. There could be multiple addresses 1016 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1017 * as frame durations and DCC format can also be set. 1018 */ 1019 struct dc_flip_addrs { 1020 struct dc_plane_address address; 1021 unsigned int flip_timestamp_in_us; 1022 bool flip_immediate; 1023 /* TODO: add flip duration for FreeSync */ 1024 bool triplebuffer_flips; 1025 }; 1026 1027 void dc_post_update_surfaces_to_stream( 1028 struct dc *dc); 1029 1030 #include "dc_stream.h" 1031 1032 /* 1033 * Structure to store surface/stream associations for validation 1034 */ 1035 struct dc_validation_set { 1036 struct dc_stream_state *stream; 1037 struct dc_plane_state *plane_states[MAX_SURFACES]; 1038 uint8_t plane_count; 1039 }; 1040 1041 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1042 const struct dc_sink *sink, 1043 struct dc_crtc_timing *crtc_timing); 1044 1045 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1046 1047 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1048 1049 bool dc_set_generic_gpio_for_stereo(bool enable, 1050 struct gpio_service *gpio_service); 1051 1052 /* 1053 * fast_validate: we return after determining if we can support the new state, 1054 * but before we populate the programming info 1055 */ 1056 enum dc_status dc_validate_global_state( 1057 struct dc *dc, 1058 struct dc_state *new_ctx, 1059 bool fast_validate); 1060 1061 1062 void dc_resource_state_construct( 1063 const struct dc *dc, 1064 struct dc_state *dst_ctx); 1065 1066 #if defined(CONFIG_DRM_AMD_DC_DCN) 1067 bool dc_acquire_release_mpc_3dlut( 1068 struct dc *dc, bool acquire, 1069 struct dc_stream_state *stream, 1070 struct dc_3dlut **lut, 1071 struct dc_transfer_func **shaper); 1072 #endif 1073 1074 void dc_resource_state_copy_construct( 1075 const struct dc_state *src_ctx, 1076 struct dc_state *dst_ctx); 1077 1078 void dc_resource_state_copy_construct_current( 1079 const struct dc *dc, 1080 struct dc_state *dst_ctx); 1081 1082 void dc_resource_state_destruct(struct dc_state *context); 1083 1084 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1085 1086 /* 1087 * TODO update to make it about validation sets 1088 * Set up streams and links associated to drive sinks 1089 * The streams parameter is an absolute set of all active streams. 1090 * 1091 * After this call: 1092 * Phy, Encoder, Timing Generator are programmed and enabled. 1093 * New streams are enabled with blank stream; no memory read. 1094 */ 1095 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1096 1097 struct dc_state *dc_create_state(struct dc *dc); 1098 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1099 void dc_retain_state(struct dc_state *context); 1100 void dc_release_state(struct dc_state *context); 1101 1102 /******************************************************************************* 1103 * Link Interfaces 1104 ******************************************************************************/ 1105 1106 struct dpcd_caps { 1107 union dpcd_rev dpcd_rev; 1108 union max_lane_count max_ln_count; 1109 union max_down_spread max_down_spread; 1110 union dprx_feature dprx_feature; 1111 1112 /* valid only for eDP v1.4 or higher*/ 1113 uint8_t edp_supported_link_rates_count; 1114 enum dc_link_rate edp_supported_link_rates[8]; 1115 1116 /* dongle type (DP converter, CV smart dongle) */ 1117 enum display_dongle_type dongle_type; 1118 /* branch device or sink device */ 1119 bool is_branch_dev; 1120 /* Dongle's downstream count. */ 1121 union sink_count sink_count; 1122 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1123 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1124 struct dc_dongle_caps dongle_caps; 1125 1126 uint32_t sink_dev_id; 1127 int8_t sink_dev_id_str[6]; 1128 int8_t sink_hw_revision; 1129 int8_t sink_fw_revision[2]; 1130 1131 uint32_t branch_dev_id; 1132 int8_t branch_dev_name[6]; 1133 int8_t branch_hw_revision; 1134 int8_t branch_fw_revision[2]; 1135 1136 bool allow_invalid_MSA_timing_param; 1137 bool panel_mode_edp; 1138 bool dpcd_display_control_capable; 1139 bool ext_receiver_cap_field_present; 1140 bool dynamic_backlight_capable_edp; 1141 union dpcd_fec_capability fec_cap; 1142 struct dpcd_dsc_capabilities dsc_caps; 1143 struct dc_lttpr_caps lttpr_caps; 1144 struct psr_caps psr_caps; 1145 1146 }; 1147 1148 union dpcd_sink_ext_caps { 1149 struct { 1150 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1151 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1152 */ 1153 uint8_t sdr_aux_backlight_control : 1; 1154 uint8_t hdr_aux_backlight_control : 1; 1155 uint8_t reserved_1 : 2; 1156 uint8_t oled : 1; 1157 uint8_t reserved : 3; 1158 } bits; 1159 uint8_t raw; 1160 }; 1161 1162 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1163 union hdcp_rx_caps { 1164 struct { 1165 uint8_t version; 1166 uint8_t reserved; 1167 struct { 1168 uint8_t repeater : 1; 1169 uint8_t hdcp_capable : 1; 1170 uint8_t reserved : 6; 1171 } byte0; 1172 } fields; 1173 uint8_t raw[3]; 1174 }; 1175 1176 union hdcp_bcaps { 1177 struct { 1178 uint8_t HDCP_CAPABLE:1; 1179 uint8_t REPEATER:1; 1180 uint8_t RESERVED:6; 1181 } bits; 1182 uint8_t raw; 1183 }; 1184 1185 struct hdcp_caps { 1186 union hdcp_rx_caps rx_caps; 1187 union hdcp_bcaps bcaps; 1188 }; 1189 #endif 1190 1191 #include "dc_link.h" 1192 1193 #if defined(CONFIG_DRM_AMD_DC_DCN) 1194 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1195 1196 #endif 1197 /******************************************************************************* 1198 * Sink Interfaces - A sink corresponds to a display output device 1199 ******************************************************************************/ 1200 1201 struct dc_container_id { 1202 // 128bit GUID in binary form 1203 unsigned char guid[16]; 1204 // 8 byte port ID -> ELD.PortID 1205 unsigned int portId[2]; 1206 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1207 unsigned short manufacturerName; 1208 // 2 byte product code -> ELD.ProductCode 1209 unsigned short productCode; 1210 }; 1211 1212 1213 struct dc_sink_dsc_caps { 1214 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1215 // 'false' if they are sink's DSC caps 1216 bool is_virtual_dpcd_dsc; 1217 struct dsc_dec_dpcd_caps dsc_dec_caps; 1218 }; 1219 1220 struct dc_sink_fec_caps { 1221 bool is_rx_fec_supported; 1222 bool is_topology_fec_supported; 1223 }; 1224 1225 /* 1226 * The sink structure contains EDID and other display device properties 1227 */ 1228 struct dc_sink { 1229 enum signal_type sink_signal; 1230 struct dc_edid dc_edid; /* raw edid */ 1231 struct dc_edid_caps edid_caps; /* parse display caps */ 1232 struct dc_container_id *dc_container_id; 1233 uint32_t dongle_max_pix_clk; 1234 void *priv; 1235 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1236 bool converter_disable_audio; 1237 1238 struct dc_sink_dsc_caps dsc_caps; 1239 struct dc_sink_fec_caps fec_caps; 1240 1241 bool is_vsc_sdp_colorimetry_supported; 1242 1243 /* private to DC core */ 1244 struct dc_link *link; 1245 struct dc_context *ctx; 1246 1247 uint32_t sink_id; 1248 1249 /* private to dc_sink.c */ 1250 // refcount must be the last member in dc_sink, since we want the 1251 // sink structure to be logically cloneable up to (but not including) 1252 // refcount 1253 struct kref refcount; 1254 }; 1255 1256 void dc_sink_retain(struct dc_sink *sink); 1257 void dc_sink_release(struct dc_sink *sink); 1258 1259 struct dc_sink_init_data { 1260 enum signal_type sink_signal; 1261 struct dc_link *link; 1262 uint32_t dongle_max_pix_clk; 1263 bool converter_disable_audio; 1264 }; 1265 1266 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1267 1268 /* Newer interfaces */ 1269 struct dc_cursor { 1270 struct dc_plane_address address; 1271 struct dc_cursor_attributes attributes; 1272 }; 1273 1274 1275 /******************************************************************************* 1276 * Interrupt interfaces 1277 ******************************************************************************/ 1278 enum dc_irq_source dc_interrupt_to_irq_source( 1279 struct dc *dc, 1280 uint32_t src_id, 1281 uint32_t ext_id); 1282 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1283 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1284 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1285 struct dc *dc, uint32_t link_index); 1286 1287 /******************************************************************************* 1288 * Power Interfaces 1289 ******************************************************************************/ 1290 1291 void dc_set_power_state( 1292 struct dc *dc, 1293 enum dc_acpi_cm_power_state power_state); 1294 void dc_resume(struct dc *dc); 1295 1296 void dc_power_down_on_boot(struct dc *dc); 1297 1298 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1299 /* 1300 * HDCP Interfaces 1301 */ 1302 enum hdcp_message_status dc_process_hdcp_msg( 1303 enum signal_type signal, 1304 struct dc_link *link, 1305 struct hdcp_protection_message *message_info); 1306 #endif 1307 bool dc_is_dmcu_initialized(struct dc *dc); 1308 1309 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1310 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1311 #if defined(CONFIG_DRM_AMD_DC_DCN) 1312 1313 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1314 struct dc_cursor_attributes *cursor_attr); 1315 1316 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1317 1318 /* 1319 * blank all streams, and set min and max memory clock to 1320 * lowest and highest DPM level, respectively 1321 */ 1322 void dc_unlock_memory_clock_frequency(struct dc *dc); 1323 1324 /* 1325 * set min memory clock to the min required for current mode, 1326 * max to maxDPM, and unblank streams 1327 */ 1328 void dc_lock_memory_clock_frequency(struct dc *dc); 1329 1330 /* cleanup on driver unload */ 1331 void dc_hardware_release(struct dc *dc); 1332 1333 #endif 1334 1335 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1336 #if defined(CONFIG_DRM_AMD_DC_DCN) 1337 void dc_z10_restore(struct dc *dc); 1338 #endif 1339 1340 bool dc_enable_dmub_notifications(struct dc *dc); 1341 1342 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1343 uint32_t link_index, 1344 struct aux_payload *payload); 1345 1346 /******************************************************************************* 1347 * DSC Interfaces 1348 ******************************************************************************/ 1349 #include "dc_dsc.h" 1350 1351 /******************************************************************************* 1352 * Disable acc mode Interfaces 1353 ******************************************************************************/ 1354 void dc_disable_accelerated_mode(struct dc *dc); 1355 1356 #endif /* DC_INTERFACE_H_ */ 1357