1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.42" 43 44 #define MAX_SURFACES 3 45 #define MAX_PLANES 6 46 #define MAX_STREAMS 6 47 #define MAX_SINKS_PER_LINK 4 48 49 /******************************************************************************* 50 * Display Core Interfaces 51 ******************************************************************************/ 52 struct dc_versions { 53 const char *dc_ver; 54 struct dmcu_version dmcu_version; 55 }; 56 57 enum dc_plane_type { 58 DC_PLANE_TYPE_INVALID, 59 DC_PLANE_TYPE_DCE_RGB, 60 DC_PLANE_TYPE_DCE_UNDERLAY, 61 DC_PLANE_TYPE_DCN_UNIVERSAL, 62 }; 63 64 struct dc_plane_cap { 65 enum dc_plane_type type; 66 uint32_t blends_with_above : 1; 67 uint32_t blends_with_below : 1; 68 uint32_t per_pixel_alpha : 1; 69 struct { 70 uint32_t argb8888 : 1; 71 uint32_t nv12 : 1; 72 uint32_t fp16 : 1; 73 uint32_t p010 : 1; 74 uint32_t ayuv : 1; 75 } pixel_format_support; 76 // max upscaling factor x1000 77 // upscaling factors are always >= 1 78 // for example, 1080p -> 8K is 4.0, or 4000 raw value 79 struct { 80 uint32_t argb8888; 81 uint32_t nv12; 82 uint32_t fp16; 83 } max_upscale_factor; 84 // max downscale factor x1000 85 // downscale factors are always <= 1 86 // for example, 8K -> 1080p is 0.25, or 250 raw value 87 struct { 88 uint32_t argb8888; 89 uint32_t nv12; 90 uint32_t fp16; 91 } max_downscale_factor; 92 }; 93 94 struct dc_caps { 95 uint32_t max_streams; 96 uint32_t max_links; 97 uint32_t max_audios; 98 uint32_t max_slave_planes; 99 uint32_t max_planes; 100 uint32_t max_downscale_ratio; 101 uint32_t i2c_speed_in_khz; 102 uint32_t dmdata_alloc_size; 103 unsigned int max_cursor_size; 104 unsigned int max_video_width; 105 int linear_pitch_alignment; 106 bool dcc_const_color; 107 bool dynamic_audio; 108 bool is_apu; 109 bool dual_link_dvi; 110 bool post_blend_color_processing; 111 bool force_dp_tps4_for_cp2520; 112 bool disable_dp_clk_share; 113 bool psp_setup_panel_mode; 114 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 115 bool hw_3d_lut; 116 #endif 117 struct dc_plane_cap planes[MAX_PLANES]; 118 }; 119 120 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 121 struct dc_bug_wa { 122 bool no_connect_phy_config; 123 bool dedcn20_305_wa; 124 struct display_mode_lib alternate_dml; 125 bool skip_clock_update; 126 }; 127 #endif 128 129 struct dc_dcc_surface_param { 130 struct dc_size surface_size; 131 enum surface_pixel_format format; 132 enum swizzle_mode_values swizzle_mode; 133 enum dc_scan_direction scan; 134 }; 135 136 struct dc_dcc_setting { 137 unsigned int max_compressed_blk_size; 138 unsigned int max_uncompressed_blk_size; 139 bool independent_64b_blks; 140 }; 141 142 struct dc_surface_dcc_cap { 143 union { 144 struct { 145 struct dc_dcc_setting rgb; 146 } grph; 147 148 struct { 149 struct dc_dcc_setting luma; 150 struct dc_dcc_setting chroma; 151 } video; 152 }; 153 154 bool capable; 155 bool const_color_support; 156 }; 157 158 struct dc_static_screen_events { 159 bool force_trigger; 160 bool cursor_update; 161 bool surface_update; 162 bool overlay_update; 163 }; 164 165 166 /* Surface update type is used by dc_update_surfaces_and_stream 167 * The update type is determined at the very beginning of the function based 168 * on parameters passed in and decides how much programming (or updating) is 169 * going to be done during the call. 170 * 171 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 172 * logical calculations or hardware register programming. This update MUST be 173 * ISR safe on windows. Currently fast update will only be used to flip surface 174 * address. 175 * 176 * UPDATE_TYPE_MED is used for slower updates which require significant hw 177 * re-programming however do not affect bandwidth consumption or clock 178 * requirements. At present, this is the level at which front end updates 179 * that do not require us to run bw_calcs happen. These are in/out transfer func 180 * updates, viewport offset changes, recout size changes and pixel depth changes. 181 * This update can be done at ISR, but we want to minimize how often this happens. 182 * 183 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 184 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 185 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 186 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 187 * a full update. This cannot be done at ISR level and should be a rare event. 188 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 189 * underscan we don't expect to see this call at all. 190 */ 191 192 enum surface_update_type { 193 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 194 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 195 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 196 }; 197 198 /* Forward declaration*/ 199 struct dc; 200 struct dc_plane_state; 201 struct dc_state; 202 203 204 struct dc_cap_funcs { 205 bool (*get_dcc_compression_cap)(const struct dc *dc, 206 const struct dc_dcc_surface_param *input, 207 struct dc_surface_dcc_cap *output); 208 }; 209 210 struct link_training_settings; 211 212 213 /* Structure to hold configuration flags set by dm at dc creation. */ 214 struct dc_config { 215 bool gpu_vm_support; 216 bool disable_disp_pll_sharing; 217 bool fbc_support; 218 bool optimize_edp_link_rate; 219 bool disable_fractional_pwm; 220 bool allow_seamless_boot_optimization; 221 bool power_down_display_on_boot; 222 bool edp_not_connected; 223 bool forced_clocks; 224 225 }; 226 227 enum visual_confirm { 228 VISUAL_CONFIRM_DISABLE = 0, 229 VISUAL_CONFIRM_SURFACE = 1, 230 VISUAL_CONFIRM_HDR = 2, 231 }; 232 233 enum dcc_option { 234 DCC_ENABLE = 0, 235 DCC_DISABLE = 1, 236 DCC_HALF_REQ_DISALBE = 2, 237 }; 238 239 enum pipe_split_policy { 240 MPC_SPLIT_DYNAMIC = 0, 241 MPC_SPLIT_AVOID = 1, 242 MPC_SPLIT_AVOID_MULT_DISP = 2, 243 }; 244 245 enum wm_report_mode { 246 WM_REPORT_DEFAULT = 0, 247 WM_REPORT_OVERRIDE = 1, 248 }; 249 250 /* 251 * For any clocks that may differ per pipe 252 * only the max is stored in this structure 253 */ 254 struct dc_clocks { 255 int dispclk_khz; 256 int max_supported_dppclk_khz; 257 int max_supported_dispclk_khz; 258 int dppclk_khz; 259 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 260 int bw_dispclk_khz; 261 int dcfclk_khz; 262 int socclk_khz; 263 int dcfclk_deep_sleep_khz; 264 int fclk_khz; 265 int phyclk_khz; 266 int dramclk_khz; 267 bool p_state_change_support; 268 269 /* 270 * Elements below are not compared for the purposes of 271 * optimization required 272 */ 273 bool prev_p_state_change_support; 274 }; 275 276 struct dc_bw_validation_profile { 277 bool enable; 278 279 unsigned long long total_ticks; 280 unsigned long long voltage_level_ticks; 281 unsigned long long watermark_ticks; 282 unsigned long long rq_dlg_ticks; 283 284 unsigned long long total_count; 285 unsigned long long skip_fast_count; 286 unsigned long long skip_pass_count; 287 unsigned long long skip_fail_count; 288 }; 289 290 #define BW_VAL_TRACE_SETUP() \ 291 unsigned long long end_tick = 0; \ 292 unsigned long long voltage_level_tick = 0; \ 293 unsigned long long watermark_tick = 0; \ 294 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 295 dm_get_timestamp(dc->ctx) : 0 296 297 #define BW_VAL_TRACE_COUNT() \ 298 if (dc->debug.bw_val_profile.enable) \ 299 dc->debug.bw_val_profile.total_count++ 300 301 #define BW_VAL_TRACE_SKIP(status) \ 302 if (dc->debug.bw_val_profile.enable) { \ 303 if (!voltage_level_tick) \ 304 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 305 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 306 } 307 308 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 309 if (dc->debug.bw_val_profile.enable) \ 310 voltage_level_tick = dm_get_timestamp(dc->ctx) 311 312 #define BW_VAL_TRACE_END_WATERMARKS() \ 313 if (dc->debug.bw_val_profile.enable) \ 314 watermark_tick = dm_get_timestamp(dc->ctx) 315 316 #define BW_VAL_TRACE_FINISH() \ 317 if (dc->debug.bw_val_profile.enable) { \ 318 end_tick = dm_get_timestamp(dc->ctx); \ 319 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 320 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 321 if (watermark_tick) { \ 322 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 323 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 324 } \ 325 } 326 327 struct dc_debug_options { 328 enum visual_confirm visual_confirm; 329 bool sanity_checks; 330 bool max_disp_clk; 331 bool surface_trace; 332 bool timing_trace; 333 bool clock_trace; 334 bool validation_trace; 335 bool bandwidth_calcs_trace; 336 int max_downscale_src_width; 337 338 /* stutter efficiency related */ 339 bool disable_stutter; 340 bool use_max_lb; 341 enum dcc_option disable_dcc; 342 enum pipe_split_policy pipe_split_policy; 343 bool force_single_disp_pipe_split; 344 bool voltage_align_fclk; 345 346 bool disable_dfs_bypass; 347 bool disable_dpp_power_gate; 348 bool disable_hubp_power_gate; 349 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 350 bool disable_dsc_power_gate; 351 #endif 352 bool disable_pplib_wm_range; 353 enum wm_report_mode pplib_wm_report_mode; 354 unsigned int min_disp_clk_khz; 355 unsigned int min_dpp_clk_khz; 356 int sr_exit_time_dpm0_ns; 357 int sr_enter_plus_exit_time_dpm0_ns; 358 int sr_exit_time_ns; 359 int sr_enter_plus_exit_time_ns; 360 int urgent_latency_ns; 361 uint32_t underflow_assert_delay_us; 362 int percent_of_ideal_drambw; 363 int dram_clock_change_latency_ns; 364 bool optimized_watermark; 365 int always_scale; 366 bool disable_pplib_clock_request; 367 bool disable_clock_gate; 368 bool disable_dmcu; 369 bool disable_psr; 370 bool force_abm_enable; 371 bool disable_stereo_support; 372 bool vsr_support; 373 bool performance_trace; 374 bool az_endpoint_mute_only; 375 bool always_use_regamma; 376 bool p010_mpo_support; 377 bool recovery_enabled; 378 bool avoid_vbios_exec_table; 379 bool scl_reset_length10; 380 bool hdmi20_disable; 381 bool skip_detection_link_training; 382 bool remove_disconnect_edp; 383 unsigned int force_odm_combine; //bit vector based on otg inst 384 unsigned int force_fclk_khz; 385 bool disable_tri_buf; 386 struct dc_bw_validation_profile bw_val_profile; 387 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 388 bool disable_fec; 389 #endif 390 /* This forces a hard min on the DCFCLK requested to SMU/PP 391 * watermarks are not affected. 392 */ 393 unsigned int force_min_dcfclk_mhz; 394 bool disable_timing_sync; 395 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 396 bool cm_in_bypass; 397 #endif 398 int force_clock_mode;/*every mode change.*/ 399 }; 400 401 struct dc_debug_data { 402 uint32_t ltFailCount; 403 uint32_t i2cErrorCount; 404 uint32_t auxErrorCount; 405 }; 406 407 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 408 struct dc_phy_addr_space_config { 409 struct { 410 uint64_t start_addr; 411 uint64_t end_addr; 412 uint64_t fb_top; 413 uint64_t fb_offset; 414 uint64_t fb_base; 415 uint64_t agp_top; 416 uint64_t agp_bot; 417 uint64_t agp_base; 418 } system_aperture; 419 420 struct { 421 uint64_t page_table_start_addr; 422 uint64_t page_table_end_addr; 423 uint64_t page_table_base_addr; 424 } gart_config; 425 426 bool valid; 427 }; 428 429 struct dc_virtual_addr_space_config { 430 uint64_t page_table_base_addr; 431 uint64_t page_table_start_addr; 432 uint64_t page_table_end_addr; 433 uint32_t page_table_block_size_in_bytes; 434 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 435 }; 436 #endif 437 438 struct dc_bounding_box_overrides { 439 int sr_exit_time_ns; 440 int sr_enter_plus_exit_time_ns; 441 int urgent_latency_ns; 442 int percent_of_ideal_drambw; 443 int dram_clock_change_latency_ns; 444 /* This forces a hard min on the DCFCLK we use 445 * for DML. Unlike the debug option for forcing 446 * DCFCLK, this override affects watermark calculations 447 */ 448 int min_dcfclk_mhz; 449 }; 450 451 struct dc_state; 452 struct resource_pool; 453 struct dce_hwseq; 454 struct gpu_info_soc_bounding_box_v1_0; 455 struct dc { 456 struct dc_versions versions; 457 struct dc_caps caps; 458 struct dc_cap_funcs cap_funcs; 459 struct dc_config config; 460 struct dc_debug_options debug; 461 struct dc_bounding_box_overrides bb_overrides; 462 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 463 struct dc_bug_wa work_arounds; 464 #endif 465 struct dc_context *ctx; 466 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 467 struct dc_phy_addr_space_config vm_pa_config; 468 #endif 469 470 uint8_t link_count; 471 struct dc_link *links[MAX_PIPES * 2]; 472 473 struct dc_state *current_state; 474 struct resource_pool *res_pool; 475 476 struct clk_mgr *clk_mgr; 477 478 /* Display Engine Clock levels */ 479 struct dm_pp_clock_levels sclk_lvls; 480 481 /* Inputs into BW and WM calculations. */ 482 struct bw_calcs_dceip *bw_dceip; 483 struct bw_calcs_vbios *bw_vbios; 484 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 485 struct dcn_soc_bounding_box *dcn_soc; 486 struct dcn_ip_params *dcn_ip; 487 struct display_mode_lib dml; 488 #endif 489 490 /* HW functions */ 491 struct hw_sequencer_funcs hwss; 492 struct dce_hwseq *hwseq; 493 494 /* Require to optimize clocks and bandwidth for added/removed planes */ 495 bool optimized_required; 496 497 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 498 bool optimize_seamless_boot; 499 500 /* FBC compressor */ 501 struct compressor *fbc_compressor; 502 503 struct dc_debug_data debug_data; 504 505 const char *build_id; 506 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 507 struct vm_helper *vm_helper; 508 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 509 #endif 510 }; 511 512 enum frame_buffer_mode { 513 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 514 FRAME_BUFFER_MODE_ZFB_ONLY, 515 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 516 } ; 517 518 struct dchub_init_data { 519 int64_t zfb_phys_addr_base; 520 int64_t zfb_mc_base_addr; 521 uint64_t zfb_size_in_byte; 522 enum frame_buffer_mode fb_mode; 523 bool dchub_initialzied; 524 bool dchub_info_valid; 525 }; 526 527 struct dc_init_data { 528 struct hw_asic_id asic_id; 529 void *driver; /* ctx */ 530 struct cgs_device *cgs_device; 531 struct dc_bounding_box_overrides bb_overrides; 532 533 int num_virtual_links; 534 /* 535 * If 'vbios_override' not NULL, it will be called instead 536 * of the real VBIOS. Intended use is Diagnostics on FPGA. 537 */ 538 struct dc_bios *vbios_override; 539 enum dce_environment dce_environment; 540 541 struct dc_config flags; 542 uint32_t log_mask; 543 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 544 /** 545 * gpu_info FW provided soc bounding box struct or 0 if not 546 * available in FW 547 */ 548 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 549 #endif 550 }; 551 552 struct dc_callback_init { 553 uint8_t reserved; 554 }; 555 556 struct dc *dc_create(const struct dc_init_data *init_params); 557 int dc_get_vmid_use_vector(struct dc *dc); 558 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 559 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 560 /* Returns the number of vmids supported */ 561 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 562 #endif 563 void dc_init_callbacks(struct dc *dc, 564 const struct dc_callback_init *init_params); 565 void dc_destroy(struct dc **dc); 566 567 /******************************************************************************* 568 * Surface Interfaces 569 ******************************************************************************/ 570 571 enum { 572 TRANSFER_FUNC_POINTS = 1025 573 }; 574 575 struct dc_hdr_static_metadata { 576 /* display chromaticities and white point in units of 0.00001 */ 577 unsigned int chromaticity_green_x; 578 unsigned int chromaticity_green_y; 579 unsigned int chromaticity_blue_x; 580 unsigned int chromaticity_blue_y; 581 unsigned int chromaticity_red_x; 582 unsigned int chromaticity_red_y; 583 unsigned int chromaticity_white_point_x; 584 unsigned int chromaticity_white_point_y; 585 586 uint32_t min_luminance; 587 uint32_t max_luminance; 588 uint32_t maximum_content_light_level; 589 uint32_t maximum_frame_average_light_level; 590 }; 591 592 enum dc_transfer_func_type { 593 TF_TYPE_PREDEFINED, 594 TF_TYPE_DISTRIBUTED_POINTS, 595 TF_TYPE_BYPASS, 596 TF_TYPE_HWPWL 597 }; 598 599 struct dc_transfer_func_distributed_points { 600 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 601 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 602 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 603 604 uint16_t end_exponent; 605 uint16_t x_point_at_y1_red; 606 uint16_t x_point_at_y1_green; 607 uint16_t x_point_at_y1_blue; 608 }; 609 610 enum dc_transfer_func_predefined { 611 TRANSFER_FUNCTION_SRGB, 612 TRANSFER_FUNCTION_BT709, 613 TRANSFER_FUNCTION_PQ, 614 TRANSFER_FUNCTION_LINEAR, 615 TRANSFER_FUNCTION_UNITY, 616 TRANSFER_FUNCTION_HLG, 617 TRANSFER_FUNCTION_HLG12, 618 TRANSFER_FUNCTION_GAMMA22, 619 TRANSFER_FUNCTION_GAMMA24, 620 TRANSFER_FUNCTION_GAMMA26 621 }; 622 623 624 struct dc_transfer_func { 625 struct kref refcount; 626 enum dc_transfer_func_type type; 627 enum dc_transfer_func_predefined tf; 628 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 629 uint32_t sdr_ref_white_level; 630 struct dc_context *ctx; 631 union { 632 struct pwl_params pwl; 633 struct dc_transfer_func_distributed_points tf_pts; 634 }; 635 }; 636 637 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 638 639 union dc_3dlut_state { 640 struct { 641 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 642 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 643 uint32_t rmu_mux_num:3; /*index of mux to use*/ 644 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 645 uint32_t mpc_rmu1_mux:4; 646 uint32_t mpc_rmu2_mux:4; 647 uint32_t reserved:15; 648 } bits; 649 uint32_t raw; 650 }; 651 652 653 struct dc_3dlut { 654 struct kref refcount; 655 struct tetrahedral_params lut_3d; 656 uint32_t hdr_multiplier; 657 bool initialized; /*remove after diag fix*/ 658 union dc_3dlut_state state; 659 struct dc_context *ctx; 660 }; 661 #endif 662 /* 663 * This structure is filled in by dc_surface_get_status and contains 664 * the last requested address and the currently active address so the called 665 * can determine if there are any outstanding flips 666 */ 667 struct dc_plane_status { 668 struct dc_plane_address requested_address; 669 struct dc_plane_address current_address; 670 bool is_flip_pending; 671 bool is_right_eye; 672 }; 673 674 union surface_update_flags { 675 676 struct { 677 uint32_t addr_update:1; 678 /* Medium updates */ 679 uint32_t dcc_change:1; 680 uint32_t color_space_change:1; 681 uint32_t horizontal_mirror_change:1; 682 uint32_t per_pixel_alpha_change:1; 683 uint32_t global_alpha_change:1; 684 uint32_t sdr_white_level:1; 685 uint32_t rotation_change:1; 686 uint32_t swizzle_change:1; 687 uint32_t scaling_change:1; 688 uint32_t position_change:1; 689 uint32_t in_transfer_func_change:1; 690 uint32_t input_csc_change:1; 691 uint32_t coeff_reduction_change:1; 692 uint32_t output_tf_change:1; 693 uint32_t pixel_format_change:1; 694 uint32_t plane_size_change:1; 695 696 /* Full updates */ 697 uint32_t new_plane:1; 698 uint32_t bpp_change:1; 699 uint32_t gamma_change:1; 700 uint32_t bandwidth_change:1; 701 uint32_t clock_change:1; 702 uint32_t stereo_format_change:1; 703 uint32_t full_update:1; 704 } bits; 705 706 uint32_t raw; 707 }; 708 709 struct dc_plane_state { 710 struct dc_plane_address address; 711 struct dc_plane_flip_time time; 712 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 713 bool triplebuffer_flips; 714 #endif 715 struct scaling_taps scaling_quality; 716 struct rect src_rect; 717 struct rect dst_rect; 718 struct rect clip_rect; 719 720 struct plane_size plane_size; 721 union dc_tiling_info tiling_info; 722 723 struct dc_plane_dcc_param dcc; 724 725 struct dc_gamma *gamma_correction; 726 struct dc_transfer_func *in_transfer_func; 727 struct dc_bias_and_scale *bias_and_scale; 728 struct dc_csc_transform input_csc_color_matrix; 729 struct fixed31_32 coeff_reduction_factor; 730 uint32_t sdr_white_level; 731 732 // TODO: No longer used, remove 733 struct dc_hdr_static_metadata hdr_static_ctx; 734 735 enum dc_color_space color_space; 736 737 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 738 struct dc_3dlut *lut3d_func; 739 struct dc_transfer_func *in_shaper_func; 740 struct dc_transfer_func *blend_tf; 741 #endif 742 743 enum surface_pixel_format format; 744 enum dc_rotation_angle rotation; 745 enum plane_stereo_format stereo_format; 746 747 bool is_tiling_rotated; 748 bool per_pixel_alpha; 749 bool global_alpha; 750 int global_alpha_value; 751 bool visible; 752 bool flip_immediate; 753 bool horizontal_mirror; 754 755 union surface_update_flags update_flags; 756 /* private to DC core */ 757 struct dc_plane_status status; 758 struct dc_context *ctx; 759 760 /* HACK: Workaround for forcing full reprogramming under some conditions */ 761 bool force_full_update; 762 763 /* private to dc_surface.c */ 764 enum dc_irq_source irq_source; 765 struct kref refcount; 766 }; 767 768 struct dc_plane_info { 769 struct plane_size plane_size; 770 union dc_tiling_info tiling_info; 771 struct dc_plane_dcc_param dcc; 772 enum surface_pixel_format format; 773 enum dc_rotation_angle rotation; 774 enum plane_stereo_format stereo_format; 775 enum dc_color_space color_space; 776 unsigned int sdr_white_level; 777 bool horizontal_mirror; 778 bool visible; 779 bool per_pixel_alpha; 780 bool global_alpha; 781 int global_alpha_value; 782 bool input_csc_enabled; 783 }; 784 785 struct dc_scaling_info { 786 struct rect src_rect; 787 struct rect dst_rect; 788 struct rect clip_rect; 789 struct scaling_taps scaling_quality; 790 }; 791 792 struct dc_surface_update { 793 struct dc_plane_state *surface; 794 795 /* isr safe update parameters. null means no updates */ 796 const struct dc_flip_addrs *flip_addr; 797 const struct dc_plane_info *plane_info; 798 const struct dc_scaling_info *scaling_info; 799 800 /* following updates require alloc/sleep/spin that is not isr safe, 801 * null means no updates 802 */ 803 const struct dc_gamma *gamma; 804 const struct dc_transfer_func *in_transfer_func; 805 806 const struct dc_csc_transform *input_csc_color_matrix; 807 const struct fixed31_32 *coeff_reduction_factor; 808 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 809 const struct dc_transfer_func *func_shaper; 810 const struct dc_3dlut *lut3d_func; 811 const struct dc_transfer_func *blend_tf; 812 #endif 813 }; 814 815 /* 816 * Create a new surface with default parameters; 817 */ 818 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 819 const struct dc_plane_status *dc_plane_get_status( 820 const struct dc_plane_state *plane_state); 821 822 void dc_plane_state_retain(struct dc_plane_state *plane_state); 823 void dc_plane_state_release(struct dc_plane_state *plane_state); 824 825 void dc_gamma_retain(struct dc_gamma *dc_gamma); 826 void dc_gamma_release(struct dc_gamma **dc_gamma); 827 struct dc_gamma *dc_create_gamma(void); 828 829 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 830 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 831 struct dc_transfer_func *dc_create_transfer_func(void); 832 833 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 834 struct dc_3dlut *dc_create_3dlut_func(void); 835 void dc_3dlut_func_release(struct dc_3dlut *lut); 836 void dc_3dlut_func_retain(struct dc_3dlut *lut); 837 #endif 838 /* 839 * This structure holds a surface address. There could be multiple addresses 840 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 841 * as frame durations and DCC format can also be set. 842 */ 843 struct dc_flip_addrs { 844 struct dc_plane_address address; 845 unsigned int flip_timestamp_in_us; 846 bool flip_immediate; 847 /* TODO: add flip duration for FreeSync */ 848 }; 849 850 bool dc_post_update_surfaces_to_stream( 851 struct dc *dc); 852 853 #include "dc_stream.h" 854 855 /* 856 * Structure to store surface/stream associations for validation 857 */ 858 struct dc_validation_set { 859 struct dc_stream_state *stream; 860 struct dc_plane_state *plane_states[MAX_SURFACES]; 861 uint8_t plane_count; 862 }; 863 864 bool dc_validate_seamless_boot_timing(const struct dc *dc, 865 const struct dc_sink *sink, 866 struct dc_crtc_timing *crtc_timing); 867 868 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 869 870 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 871 872 bool dc_set_generic_gpio_for_stereo(bool enable, 873 struct gpio_service *gpio_service); 874 875 /* 876 * fast_validate: we return after determining if we can support the new state, 877 * but before we populate the programming info 878 */ 879 enum dc_status dc_validate_global_state( 880 struct dc *dc, 881 struct dc_state *new_ctx, 882 bool fast_validate); 883 884 885 void dc_resource_state_construct( 886 const struct dc *dc, 887 struct dc_state *dst_ctx); 888 889 void dc_resource_state_copy_construct( 890 const struct dc_state *src_ctx, 891 struct dc_state *dst_ctx); 892 893 void dc_resource_state_copy_construct_current( 894 const struct dc *dc, 895 struct dc_state *dst_ctx); 896 897 void dc_resource_state_destruct(struct dc_state *context); 898 899 /* 900 * TODO update to make it about validation sets 901 * Set up streams and links associated to drive sinks 902 * The streams parameter is an absolute set of all active streams. 903 * 904 * After this call: 905 * Phy, Encoder, Timing Generator are programmed and enabled. 906 * New streams are enabled with blank stream; no memory read. 907 */ 908 bool dc_commit_state(struct dc *dc, struct dc_state *context); 909 910 911 struct dc_state *dc_create_state(struct dc *dc); 912 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 913 void dc_retain_state(struct dc_state *context); 914 void dc_release_state(struct dc_state *context); 915 916 /******************************************************************************* 917 * Link Interfaces 918 ******************************************************************************/ 919 920 struct dpcd_caps { 921 union dpcd_rev dpcd_rev; 922 union max_lane_count max_ln_count; 923 union max_down_spread max_down_spread; 924 union dprx_feature dprx_feature; 925 926 /* valid only for eDP v1.4 or higher*/ 927 uint8_t edp_supported_link_rates_count; 928 enum dc_link_rate edp_supported_link_rates[8]; 929 930 /* dongle type (DP converter, CV smart dongle) */ 931 enum display_dongle_type dongle_type; 932 /* branch device or sink device */ 933 bool is_branch_dev; 934 /* Dongle's downstream count. */ 935 union sink_count sink_count; 936 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 937 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 938 struct dc_dongle_caps dongle_caps; 939 940 uint32_t sink_dev_id; 941 int8_t sink_dev_id_str[6]; 942 int8_t sink_hw_revision; 943 int8_t sink_fw_revision[2]; 944 945 uint32_t branch_dev_id; 946 int8_t branch_dev_name[6]; 947 int8_t branch_hw_revision; 948 int8_t branch_fw_revision[2]; 949 950 bool allow_invalid_MSA_timing_param; 951 bool panel_mode_edp; 952 bool dpcd_display_control_capable; 953 bool ext_receiver_cap_field_present; 954 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 955 union dpcd_fec_capability fec_cap; 956 struct dpcd_dsc_capabilities dsc_caps; 957 #endif 958 }; 959 960 #include "dc_link.h" 961 962 /******************************************************************************* 963 * Sink Interfaces - A sink corresponds to a display output device 964 ******************************************************************************/ 965 966 struct dc_container_id { 967 // 128bit GUID in binary form 968 unsigned char guid[16]; 969 // 8 byte port ID -> ELD.PortID 970 unsigned int portId[2]; 971 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 972 unsigned short manufacturerName; 973 // 2 byte product code -> ELD.ProductCode 974 unsigned short productCode; 975 }; 976 977 978 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 979 struct dc_sink_dsc_caps { 980 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 981 // 'false' if they are sink's DSC caps 982 bool is_virtual_dpcd_dsc; 983 struct dsc_dec_dpcd_caps dsc_dec_caps; 984 }; 985 #endif 986 987 /* 988 * The sink structure contains EDID and other display device properties 989 */ 990 struct dc_sink { 991 enum signal_type sink_signal; 992 struct dc_edid dc_edid; /* raw edid */ 993 struct dc_edid_caps edid_caps; /* parse display caps */ 994 struct dc_container_id *dc_container_id; 995 uint32_t dongle_max_pix_clk; 996 void *priv; 997 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 998 bool converter_disable_audio; 999 1000 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1001 struct dc_sink_dsc_caps sink_dsc_caps; 1002 #endif 1003 1004 /* private to DC core */ 1005 struct dc_link *link; 1006 struct dc_context *ctx; 1007 1008 uint32_t sink_id; 1009 1010 /* private to dc_sink.c */ 1011 // refcount must be the last member in dc_sink, since we want the 1012 // sink structure to be logically cloneable up to (but not including) 1013 // refcount 1014 struct kref refcount; 1015 }; 1016 1017 void dc_sink_retain(struct dc_sink *sink); 1018 void dc_sink_release(struct dc_sink *sink); 1019 1020 struct dc_sink_init_data { 1021 enum signal_type sink_signal; 1022 struct dc_link *link; 1023 uint32_t dongle_max_pix_clk; 1024 bool converter_disable_audio; 1025 }; 1026 1027 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1028 1029 /* Newer interfaces */ 1030 struct dc_cursor { 1031 struct dc_plane_address address; 1032 struct dc_cursor_attributes attributes; 1033 }; 1034 1035 1036 /******************************************************************************* 1037 * Interrupt interfaces 1038 ******************************************************************************/ 1039 enum dc_irq_source dc_interrupt_to_irq_source( 1040 struct dc *dc, 1041 uint32_t src_id, 1042 uint32_t ext_id); 1043 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1044 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1045 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1046 struct dc *dc, uint32_t link_index); 1047 1048 /******************************************************************************* 1049 * Power Interfaces 1050 ******************************************************************************/ 1051 1052 void dc_set_power_state( 1053 struct dc *dc, 1054 enum dc_acpi_cm_power_state power_state); 1055 void dc_resume(struct dc *dc); 1056 unsigned int dc_get_current_backlight_pwm(struct dc *dc); 1057 unsigned int dc_get_target_backlight_pwm(struct dc *dc); 1058 1059 bool dc_is_dmcu_initialized(struct dc *dc); 1060 1061 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1062 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1063 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) 1064 /******************************************************************************* 1065 * DSC Interfaces 1066 ******************************************************************************/ 1067 #include "dc_dsc.h" 1068 #endif 1069 #endif /* DC_INTERFACE_H_ */ 1070