1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "hdcp_msg_types.h" 33 #include "gpio_types.h" 34 #include "link_service_types.h" 35 #include "grph_object_ctrl_defs.h" 36 #include <inc/hw/opp.h> 37 38 #include "inc/hw_sequencer.h" 39 #include "inc/compressor.h" 40 #include "inc/hw/dmcu.h" 41 #include "dml/display_mode_lib.h" 42 43 /* forward declaration */ 44 struct aux_payload; 45 struct set_config_cmd_payload; 46 struct dmub_notification; 47 48 #define DC_VER "3.2.237" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MIN_VIEWPORT_SIZE 12 54 #define MAX_NUM_EDP 2 55 56 /* Display Core Interfaces */ 57 struct dc_versions { 58 const char *dc_ver; 59 struct dmcu_version dmcu_version; 60 }; 61 62 enum dp_protocol_version { 63 DP_VERSION_1_4, 64 }; 65 66 enum dc_plane_type { 67 DC_PLANE_TYPE_INVALID, 68 DC_PLANE_TYPE_DCE_RGB, 69 DC_PLANE_TYPE_DCE_UNDERLAY, 70 DC_PLANE_TYPE_DCN_UNIVERSAL, 71 }; 72 73 // Sizes defined as multiples of 64KB 74 enum det_size { 75 DET_SIZE_DEFAULT = 0, 76 DET_SIZE_192KB = 3, 77 DET_SIZE_256KB = 4, 78 DET_SIZE_320KB = 5, 79 DET_SIZE_384KB = 6 80 }; 81 82 83 struct dc_plane_cap { 84 enum dc_plane_type type; 85 uint32_t per_pixel_alpha : 1; 86 struct { 87 uint32_t argb8888 : 1; 88 uint32_t nv12 : 1; 89 uint32_t fp16 : 1; 90 uint32_t p010 : 1; 91 uint32_t ayuv : 1; 92 } pixel_format_support; 93 // max upscaling factor x1000 94 // upscaling factors are always >= 1 95 // for example, 1080p -> 8K is 4.0, or 4000 raw value 96 struct { 97 uint32_t argb8888; 98 uint32_t nv12; 99 uint32_t fp16; 100 } max_upscale_factor; 101 // max downscale factor x1000 102 // downscale factors are always <= 1 103 // for example, 8K -> 1080p is 0.25, or 250 raw value 104 struct { 105 uint32_t argb8888; 106 uint32_t nv12; 107 uint32_t fp16; 108 } max_downscale_factor; 109 // minimal width/height 110 uint32_t min_width; 111 uint32_t min_height; 112 }; 113 114 /** 115 * DOC: color-management-caps 116 * 117 * **Color management caps (DPP and MPC)** 118 * 119 * Modules/color calculates various color operations which are translated to 120 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 121 * DCN1, every new generation comes with fairly major differences in color 122 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 123 * decide mapping to HW block based on logical capabilities. 124 */ 125 126 /** 127 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 128 * @srgb: RGB color space transfer func 129 * @bt2020: BT.2020 transfer func 130 * @gamma2_2: standard gamma 131 * @pq: perceptual quantizer transfer function 132 * @hlg: hybrid log–gamma transfer function 133 */ 134 struct rom_curve_caps { 135 uint16_t srgb : 1; 136 uint16_t bt2020 : 1; 137 uint16_t gamma2_2 : 1; 138 uint16_t pq : 1; 139 uint16_t hlg : 1; 140 }; 141 142 /** 143 * struct dpp_color_caps - color pipeline capabilities for display pipe and 144 * plane blocks 145 * 146 * @dcn_arch: all DCE generations treated the same 147 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 148 * just plain 256-entry lookup 149 * @icsc: input color space conversion 150 * @dgam_ram: programmable degamma LUT 151 * @post_csc: post color space conversion, before gamut remap 152 * @gamma_corr: degamma correction 153 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 154 * with MPC by setting mpc:shared_3d_lut flag 155 * @ogam_ram: programmable out/blend gamma LUT 156 * @ocsc: output color space conversion 157 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 158 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 159 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 160 * 161 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 162 */ 163 struct dpp_color_caps { 164 uint16_t dcn_arch : 1; 165 uint16_t input_lut_shared : 1; 166 uint16_t icsc : 1; 167 uint16_t dgam_ram : 1; 168 uint16_t post_csc : 1; 169 uint16_t gamma_corr : 1; 170 uint16_t hw_3d_lut : 1; 171 uint16_t ogam_ram : 1; 172 uint16_t ocsc : 1; 173 uint16_t dgam_rom_for_yuv : 1; 174 struct rom_curve_caps dgam_rom_caps; 175 struct rom_curve_caps ogam_rom_caps; 176 }; 177 178 /** 179 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 180 * plane combined blocks 181 * 182 * @gamut_remap: color transformation matrix 183 * @ogam_ram: programmable out gamma LUT 184 * @ocsc: output color space conversion matrix 185 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 186 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 187 * instance 188 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 189 */ 190 struct mpc_color_caps { 191 uint16_t gamut_remap : 1; 192 uint16_t ogam_ram : 1; 193 uint16_t ocsc : 1; 194 uint16_t num_3dluts : 3; 195 uint16_t shared_3d_lut:1; 196 struct rom_curve_caps ogam_rom_caps; 197 }; 198 199 /** 200 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 201 * @dpp: color pipes caps for DPP 202 * @mpc: color pipes caps for MPC 203 */ 204 struct dc_color_caps { 205 struct dpp_color_caps dpp; 206 struct mpc_color_caps mpc; 207 }; 208 209 struct dc_dmub_caps { 210 bool psr; 211 bool mclk_sw; 212 bool subvp_psr; 213 bool gecc_enable; 214 }; 215 216 struct dc_caps { 217 uint32_t max_streams; 218 uint32_t max_links; 219 uint32_t max_audios; 220 uint32_t max_slave_planes; 221 uint32_t max_slave_yuv_planes; 222 uint32_t max_slave_rgb_planes; 223 uint32_t max_planes; 224 uint32_t max_downscale_ratio; 225 uint32_t i2c_speed_in_khz; 226 uint32_t i2c_speed_in_khz_hdcp; 227 uint32_t dmdata_alloc_size; 228 unsigned int max_cursor_size; 229 unsigned int max_video_width; 230 unsigned int min_horizontal_blanking_period; 231 int linear_pitch_alignment; 232 bool dcc_const_color; 233 bool dynamic_audio; 234 bool is_apu; 235 bool dual_link_dvi; 236 bool post_blend_color_processing; 237 bool force_dp_tps4_for_cp2520; 238 bool disable_dp_clk_share; 239 bool psp_setup_panel_mode; 240 bool extended_aux_timeout_support; 241 bool dmcub_support; 242 bool zstate_support; 243 uint32_t num_of_internal_disp; 244 enum dp_protocol_version max_dp_protocol_version; 245 unsigned int mall_size_per_mem_channel; 246 unsigned int mall_size_total; 247 unsigned int cursor_cache_size; 248 struct dc_plane_cap planes[MAX_PLANES]; 249 struct dc_color_caps color; 250 struct dc_dmub_caps dmub_caps; 251 bool dp_hpo; 252 bool dp_hdmi21_pcon_support; 253 bool edp_dsc_support; 254 bool vbios_lttpr_aware; 255 bool vbios_lttpr_enable; 256 uint32_t max_otg_num; 257 uint32_t max_cab_allocation_bytes; 258 uint32_t cache_line_size; 259 uint32_t cache_num_ways; 260 uint16_t subvp_fw_processing_delay_us; 261 uint8_t subvp_drr_max_vblank_margin_us; 262 uint16_t subvp_prefetch_end_to_mall_start_us; 263 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 264 uint16_t subvp_pstate_allow_width_us; 265 uint16_t subvp_vertical_int_margin_us; 266 bool seamless_odm; 267 uint8_t subvp_drr_vblank_start_margin_us; 268 }; 269 270 struct dc_bug_wa { 271 bool no_connect_phy_config; 272 bool dedcn20_305_wa; 273 bool skip_clock_update; 274 bool lt_early_cr_pattern; 275 struct { 276 uint8_t uclk : 1; 277 uint8_t fclk : 1; 278 uint8_t dcfclk : 1; 279 uint8_t dcfclk_ds: 1; 280 } clock_update_disable_mask; 281 }; 282 struct dc_dcc_surface_param { 283 struct dc_size surface_size; 284 enum surface_pixel_format format; 285 enum swizzle_mode_values swizzle_mode; 286 enum dc_scan_direction scan; 287 }; 288 289 struct dc_dcc_setting { 290 unsigned int max_compressed_blk_size; 291 unsigned int max_uncompressed_blk_size; 292 bool independent_64b_blks; 293 //These bitfields to be used starting with DCN 294 struct { 295 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 296 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 297 uint32_t dcc_256_128_128 : 1; //available starting with DCN 298 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 299 } dcc_controls; 300 }; 301 302 struct dc_surface_dcc_cap { 303 union { 304 struct { 305 struct dc_dcc_setting rgb; 306 } grph; 307 308 struct { 309 struct dc_dcc_setting luma; 310 struct dc_dcc_setting chroma; 311 } video; 312 }; 313 314 bool capable; 315 bool const_color_support; 316 }; 317 318 struct dc_static_screen_params { 319 struct { 320 bool force_trigger; 321 bool cursor_update; 322 bool surface_update; 323 bool overlay_update; 324 } triggers; 325 unsigned int num_frames; 326 }; 327 328 329 /* Surface update type is used by dc_update_surfaces_and_stream 330 * The update type is determined at the very beginning of the function based 331 * on parameters passed in and decides how much programming (or updating) is 332 * going to be done during the call. 333 * 334 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 335 * logical calculations or hardware register programming. This update MUST be 336 * ISR safe on windows. Currently fast update will only be used to flip surface 337 * address. 338 * 339 * UPDATE_TYPE_MED is used for slower updates which require significant hw 340 * re-programming however do not affect bandwidth consumption or clock 341 * requirements. At present, this is the level at which front end updates 342 * that do not require us to run bw_calcs happen. These are in/out transfer func 343 * updates, viewport offset changes, recout size changes and pixel depth changes. 344 * This update can be done at ISR, but we want to minimize how often this happens. 345 * 346 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 347 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 348 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 349 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 350 * a full update. This cannot be done at ISR level and should be a rare event. 351 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 352 * underscan we don't expect to see this call at all. 353 */ 354 355 enum surface_update_type { 356 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 357 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 358 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 359 }; 360 361 /* Forward declaration*/ 362 struct dc; 363 struct dc_plane_state; 364 struct dc_state; 365 366 367 struct dc_cap_funcs { 368 bool (*get_dcc_compression_cap)(const struct dc *dc, 369 const struct dc_dcc_surface_param *input, 370 struct dc_surface_dcc_cap *output); 371 }; 372 373 struct link_training_settings; 374 375 union allow_lttpr_non_transparent_mode { 376 struct { 377 bool DP1_4A : 1; 378 bool DP2_0 : 1; 379 } bits; 380 unsigned char raw; 381 }; 382 383 /* Structure to hold configuration flags set by dm at dc creation. */ 384 struct dc_config { 385 bool gpu_vm_support; 386 bool disable_disp_pll_sharing; 387 bool fbc_support; 388 bool disable_fractional_pwm; 389 bool allow_seamless_boot_optimization; 390 bool seamless_boot_edp_requested; 391 bool edp_not_connected; 392 bool edp_no_power_sequencing; 393 bool force_enum_edp; 394 bool forced_clocks; 395 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 396 bool multi_mon_pp_mclk_switch; 397 bool disable_dmcu; 398 bool enable_4to1MPC; 399 bool enable_windowed_mpo_odm; 400 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 401 uint32_t allow_edp_hotplug_detection; 402 bool clamp_min_dcfclk; 403 uint64_t vblank_alignment_dto_params; 404 uint8_t vblank_alignment_max_frame_time_diff; 405 bool is_asymmetric_memory; 406 bool is_single_rank_dimm; 407 bool is_vmin_only_asic; 408 bool use_pipe_ctx_sync_logic; 409 bool ignore_dpref_ss; 410 bool enable_mipi_converter_optimization; 411 bool use_default_clock_table; 412 bool force_bios_enable_lttpr; 413 uint8_t force_bios_fixed_vs; 414 int sdpif_request_limit_words_per_umc; 415 bool use_old_fixed_vs_sequence; 416 bool disable_subvp_drr; 417 }; 418 419 enum visual_confirm { 420 VISUAL_CONFIRM_DISABLE = 0, 421 VISUAL_CONFIRM_SURFACE = 1, 422 VISUAL_CONFIRM_HDR = 2, 423 VISUAL_CONFIRM_MPCTREE = 4, 424 VISUAL_CONFIRM_PSR = 5, 425 VISUAL_CONFIRM_SWAPCHAIN = 6, 426 VISUAL_CONFIRM_FAMS = 7, 427 VISUAL_CONFIRM_SWIZZLE = 9, 428 VISUAL_CONFIRM_SUBVP = 14, 429 VISUAL_CONFIRM_MCLK_SWITCH = 16, 430 }; 431 432 enum dc_psr_power_opts { 433 psr_power_opt_invalid = 0x0, 434 psr_power_opt_smu_opt_static_screen = 0x1, 435 psr_power_opt_z10_static_screen = 0x10, 436 psr_power_opt_ds_disable_allow = 0x100, 437 }; 438 439 enum dml_hostvm_override_opts { 440 DML_HOSTVM_NO_OVERRIDE = 0x0, 441 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 442 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 443 }; 444 445 enum dcc_option { 446 DCC_ENABLE = 0, 447 DCC_DISABLE = 1, 448 DCC_HALF_REQ_DISALBE = 2, 449 }; 450 451 /** 452 * enum pipe_split_policy - Pipe split strategy supported by DCN 453 * 454 * This enum is used to define the pipe split policy supported by DCN. By 455 * default, DC favors MPC_SPLIT_DYNAMIC. 456 */ 457 enum pipe_split_policy { 458 /** 459 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 460 * pipe in order to bring the best trade-off between performance and 461 * power consumption. This is the recommended option. 462 */ 463 MPC_SPLIT_DYNAMIC = 0, 464 465 /** 466 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 467 * try any sort of split optimization. 468 */ 469 MPC_SPLIT_AVOID = 1, 470 471 /** 472 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 473 * optimize the pipe utilization when using a single display; if the 474 * user connects to a second display, DC will avoid pipe split. 475 */ 476 MPC_SPLIT_AVOID_MULT_DISP = 2, 477 }; 478 479 enum wm_report_mode { 480 WM_REPORT_DEFAULT = 0, 481 WM_REPORT_OVERRIDE = 1, 482 }; 483 enum dtm_pstate{ 484 dtm_level_p0 = 0,/*highest voltage*/ 485 dtm_level_p1, 486 dtm_level_p2, 487 dtm_level_p3, 488 dtm_level_p4,/*when active_display_count = 0*/ 489 }; 490 491 enum dcn_pwr_state { 492 DCN_PWR_STATE_UNKNOWN = -1, 493 DCN_PWR_STATE_MISSION_MODE = 0, 494 DCN_PWR_STATE_LOW_POWER = 3, 495 }; 496 497 enum dcn_zstate_support_state { 498 DCN_ZSTATE_SUPPORT_UNKNOWN, 499 DCN_ZSTATE_SUPPORT_ALLOW, 500 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 501 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 502 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 503 DCN_ZSTATE_SUPPORT_DISALLOW, 504 }; 505 506 /** 507 * struct dc_clocks - DC pipe clocks 508 * 509 * For any clocks that may differ per pipe only the max is stored in this 510 * structure 511 */ 512 struct dc_clocks { 513 int dispclk_khz; 514 int actual_dispclk_khz; 515 int dppclk_khz; 516 int actual_dppclk_khz; 517 int disp_dpp_voltage_level_khz; 518 int dcfclk_khz; 519 int socclk_khz; 520 int dcfclk_deep_sleep_khz; 521 int fclk_khz; 522 int phyclk_khz; 523 int dramclk_khz; 524 bool p_state_change_support; 525 enum dcn_zstate_support_state zstate_support; 526 bool dtbclk_en; 527 int ref_dtbclk_khz; 528 bool fclk_p_state_change_support; 529 enum dcn_pwr_state pwr_state; 530 /* 531 * Elements below are not compared for the purposes of 532 * optimization required 533 */ 534 bool prev_p_state_change_support; 535 bool fclk_prev_p_state_change_support; 536 int num_ways; 537 538 /* 539 * @fw_based_mclk_switching 540 * 541 * DC has a mechanism that leverage the variable refresh rate to switch 542 * memory clock in cases that we have a large latency to achieve the 543 * memory clock change and a short vblank window. DC has some 544 * requirements to enable this feature, and this field describes if the 545 * system support or not such a feature. 546 */ 547 bool fw_based_mclk_switching; 548 bool fw_based_mclk_switching_shut_down; 549 int prev_num_ways; 550 enum dtm_pstate dtm_level; 551 int max_supported_dppclk_khz; 552 int max_supported_dispclk_khz; 553 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 554 int bw_dispclk_khz; 555 }; 556 557 struct dc_bw_validation_profile { 558 bool enable; 559 560 unsigned long long total_ticks; 561 unsigned long long voltage_level_ticks; 562 unsigned long long watermark_ticks; 563 unsigned long long rq_dlg_ticks; 564 565 unsigned long long total_count; 566 unsigned long long skip_fast_count; 567 unsigned long long skip_pass_count; 568 unsigned long long skip_fail_count; 569 }; 570 571 #define BW_VAL_TRACE_SETUP() \ 572 unsigned long long end_tick = 0; \ 573 unsigned long long voltage_level_tick = 0; \ 574 unsigned long long watermark_tick = 0; \ 575 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 576 dm_get_timestamp(dc->ctx) : 0 577 578 #define BW_VAL_TRACE_COUNT() \ 579 if (dc->debug.bw_val_profile.enable) \ 580 dc->debug.bw_val_profile.total_count++ 581 582 #define BW_VAL_TRACE_SKIP(status) \ 583 if (dc->debug.bw_val_profile.enable) { \ 584 if (!voltage_level_tick) \ 585 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 586 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 587 } 588 589 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 590 if (dc->debug.bw_val_profile.enable) \ 591 voltage_level_tick = dm_get_timestamp(dc->ctx) 592 593 #define BW_VAL_TRACE_END_WATERMARKS() \ 594 if (dc->debug.bw_val_profile.enable) \ 595 watermark_tick = dm_get_timestamp(dc->ctx) 596 597 #define BW_VAL_TRACE_FINISH() \ 598 if (dc->debug.bw_val_profile.enable) { \ 599 end_tick = dm_get_timestamp(dc->ctx); \ 600 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 601 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 602 if (watermark_tick) { \ 603 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 604 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 605 } \ 606 } 607 608 union mem_low_power_enable_options { 609 struct { 610 bool vga: 1; 611 bool i2c: 1; 612 bool dmcu: 1; 613 bool dscl: 1; 614 bool cm: 1; 615 bool mpc: 1; 616 bool optc: 1; 617 bool vpg: 1; 618 bool afmt: 1; 619 } bits; 620 uint32_t u32All; 621 }; 622 623 union root_clock_optimization_options { 624 struct { 625 bool dpp: 1; 626 bool dsc: 1; 627 bool hdmistream: 1; 628 bool hdmichar: 1; 629 bool dpstream: 1; 630 bool symclk32_se: 1; 631 bool symclk32_le: 1; 632 bool symclk_fe: 1; 633 bool physymclk: 1; 634 bool dpiasymclk: 1; 635 uint32_t reserved: 22; 636 } bits; 637 uint32_t u32All; 638 }; 639 640 union dpia_debug_options { 641 struct { 642 uint32_t disable_dpia:1; /* bit 0 */ 643 uint32_t force_non_lttpr:1; /* bit 1 */ 644 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 645 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 646 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 647 uint32_t reserved:27; 648 } bits; 649 uint32_t raw; 650 }; 651 652 /* AUX wake work around options 653 * 0: enable/disable work around 654 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 655 * 15-2: reserved 656 * 31-16: timeout in ms 657 */ 658 union aux_wake_wa_options { 659 struct { 660 uint32_t enable_wa : 1; 661 uint32_t use_default_timeout : 1; 662 uint32_t rsvd: 14; 663 uint32_t timeout_ms : 16; 664 } bits; 665 uint32_t raw; 666 }; 667 668 struct dc_debug_data { 669 uint32_t ltFailCount; 670 uint32_t i2cErrorCount; 671 uint32_t auxErrorCount; 672 }; 673 674 struct dc_phy_addr_space_config { 675 struct { 676 uint64_t start_addr; 677 uint64_t end_addr; 678 uint64_t fb_top; 679 uint64_t fb_offset; 680 uint64_t fb_base; 681 uint64_t agp_top; 682 uint64_t agp_bot; 683 uint64_t agp_base; 684 } system_aperture; 685 686 struct { 687 uint64_t page_table_start_addr; 688 uint64_t page_table_end_addr; 689 uint64_t page_table_base_addr; 690 bool base_addr_is_mc_addr; 691 } gart_config; 692 693 bool valid; 694 bool is_hvm_enabled; 695 uint64_t page_table_default_page_addr; 696 }; 697 698 struct dc_virtual_addr_space_config { 699 uint64_t page_table_base_addr; 700 uint64_t page_table_start_addr; 701 uint64_t page_table_end_addr; 702 uint32_t page_table_block_size_in_bytes; 703 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 704 }; 705 706 struct dc_bounding_box_overrides { 707 int sr_exit_time_ns; 708 int sr_enter_plus_exit_time_ns; 709 int sr_exit_z8_time_ns; 710 int sr_enter_plus_exit_z8_time_ns; 711 int urgent_latency_ns; 712 int percent_of_ideal_drambw; 713 int dram_clock_change_latency_ns; 714 int dummy_clock_change_latency_ns; 715 int fclk_clock_change_latency_ns; 716 /* This forces a hard min on the DCFCLK we use 717 * for DML. Unlike the debug option for forcing 718 * DCFCLK, this override affects watermark calculations 719 */ 720 int min_dcfclk_mhz; 721 }; 722 723 struct dc_state; 724 struct resource_pool; 725 struct dce_hwseq; 726 struct link_service; 727 728 /** 729 * struct dc_debug_options - DC debug struct 730 * 731 * This struct provides a simple mechanism for developers to change some 732 * configurations, enable/disable features, and activate extra debug options. 733 * This can be very handy to narrow down whether some specific feature is 734 * causing an issue or not. 735 */ 736 struct dc_debug_options { 737 bool native422_support; 738 bool disable_dsc; 739 enum visual_confirm visual_confirm; 740 int visual_confirm_rect_height; 741 742 bool sanity_checks; 743 bool max_disp_clk; 744 bool surface_trace; 745 bool timing_trace; 746 bool clock_trace; 747 bool validation_trace; 748 bool bandwidth_calcs_trace; 749 int max_downscale_src_width; 750 751 /* stutter efficiency related */ 752 bool disable_stutter; 753 bool use_max_lb; 754 enum dcc_option disable_dcc; 755 756 /** 757 * @pipe_split_policy: Define which pipe split policy is used by the 758 * display core. 759 */ 760 enum pipe_split_policy pipe_split_policy; 761 bool force_single_disp_pipe_split; 762 bool voltage_align_fclk; 763 bool disable_min_fclk; 764 765 bool disable_dfs_bypass; 766 bool disable_dpp_power_gate; 767 bool disable_hubp_power_gate; 768 bool disable_dsc_power_gate; 769 int dsc_min_slice_height_override; 770 int dsc_bpp_increment_div; 771 bool disable_pplib_wm_range; 772 enum wm_report_mode pplib_wm_report_mode; 773 unsigned int min_disp_clk_khz; 774 unsigned int min_dpp_clk_khz; 775 unsigned int min_dram_clk_khz; 776 int sr_exit_time_dpm0_ns; 777 int sr_enter_plus_exit_time_dpm0_ns; 778 int sr_exit_time_ns; 779 int sr_enter_plus_exit_time_ns; 780 int sr_exit_z8_time_ns; 781 int sr_enter_plus_exit_z8_time_ns; 782 int urgent_latency_ns; 783 uint32_t underflow_assert_delay_us; 784 int percent_of_ideal_drambw; 785 int dram_clock_change_latency_ns; 786 bool optimized_watermark; 787 int always_scale; 788 bool disable_pplib_clock_request; 789 bool disable_clock_gate; 790 bool disable_mem_low_power; 791 bool pstate_enabled; 792 bool disable_dmcu; 793 bool force_abm_enable; 794 bool disable_stereo_support; 795 bool vsr_support; 796 bool performance_trace; 797 bool az_endpoint_mute_only; 798 bool always_use_regamma; 799 bool recovery_enabled; 800 bool avoid_vbios_exec_table; 801 bool scl_reset_length10; 802 bool hdmi20_disable; 803 bool skip_detection_link_training; 804 uint32_t edid_read_retry_times; 805 unsigned int force_odm_combine; //bit vector based on otg inst 806 unsigned int seamless_boot_odm_combine; 807 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 808 int minimum_z8_residency_time; 809 bool disable_z9_mpc; 810 unsigned int force_fclk_khz; 811 bool enable_tri_buf; 812 bool dmub_offload_enabled; 813 bool dmcub_emulation; 814 bool disable_idle_power_optimizations; 815 unsigned int mall_size_override; 816 unsigned int mall_additional_timer_percent; 817 bool mall_error_as_fatal; 818 bool dmub_command_table; /* for testing only */ 819 struct dc_bw_validation_profile bw_val_profile; 820 bool disable_fec; 821 bool disable_48mhz_pwrdwn; 822 /* This forces a hard min on the DCFCLK requested to SMU/PP 823 * watermarks are not affected. 824 */ 825 unsigned int force_min_dcfclk_mhz; 826 int dwb_fi_phase; 827 bool disable_timing_sync; 828 bool cm_in_bypass; 829 int force_clock_mode;/*every mode change.*/ 830 831 bool disable_dram_clock_change_vactive_support; 832 bool validate_dml_output; 833 bool enable_dmcub_surface_flip; 834 bool usbc_combo_phy_reset_wa; 835 bool enable_dram_clock_change_one_display_vactive; 836 /* TODO - remove once tested */ 837 bool legacy_dp2_lt; 838 bool set_mst_en_for_sst; 839 bool disable_uhbr; 840 bool force_dp2_lt_fallback_method; 841 bool ignore_cable_id; 842 union mem_low_power_enable_options enable_mem_low_power; 843 union root_clock_optimization_options root_clock_optimization; 844 bool hpo_optimization; 845 bool force_vblank_alignment; 846 847 /* Enable dmub aux for legacy ddc */ 848 bool enable_dmub_aux_for_legacy_ddc; 849 bool disable_fams; 850 /* FEC/PSR1 sequence enable delay in 100us */ 851 uint8_t fec_enable_delay_in100us; 852 bool enable_driver_sequence_debug; 853 enum det_size crb_alloc_policy; 854 int crb_alloc_policy_min_disp_count; 855 bool disable_z10; 856 bool enable_z9_disable_interface; 857 bool psr_skip_crtc_disable; 858 union dpia_debug_options dpia_debug; 859 bool disable_fixed_vs_aux_timeout_wa; 860 bool force_disable_subvp; 861 bool force_subvp_mclk_switch; 862 bool allow_sw_cursor_fallback; 863 unsigned int force_subvp_num_ways; 864 unsigned int force_mall_ss_num_ways; 865 bool alloc_extra_way_for_cursor; 866 uint32_t subvp_extra_lines; 867 bool force_usr_allow; 868 /* uses value at boot and disables switch */ 869 bool disable_dtb_ref_clk_switch; 870 bool extended_blank_optimization; 871 union aux_wake_wa_options aux_wake_wa; 872 uint32_t mst_start_top_delay; 873 uint8_t psr_power_use_phy_fsm; 874 enum dml_hostvm_override_opts dml_hostvm_override; 875 bool dml_disallow_alternate_prefetch_modes; 876 bool use_legacy_soc_bb_mechanism; 877 bool exit_idle_opt_for_cursor_updates; 878 bool enable_single_display_2to1_odm_policy; 879 bool enable_double_buffered_dsc_pg_support; 880 bool enable_dp_dig_pixel_rate_div_policy; 881 enum lttpr_mode lttpr_mode_override; 882 unsigned int dsc_delay_factor_wa_x1000; 883 unsigned int min_prefetch_in_strobe_ns; 884 bool disable_unbounded_requesting; 885 bool dig_fifo_off_in_blank; 886 bool temp_mst_deallocation_sequence; 887 bool override_dispclk_programming; 888 bool disable_fpo_optimizations; 889 bool support_eDP1_5; 890 uint32_t fpo_vactive_margin_us; 891 bool disable_fpo_vactive; 892 bool disable_boot_optimizations; 893 bool override_odm_optimization; 894 bool minimize_dispclk_using_odm; 895 bool disable_subvp_high_refresh; 896 bool disable_dp_plus_plus_wa; 897 uint32_t fpo_vactive_min_active_margin_us; 898 uint32_t fpo_vactive_max_blank_us; 899 bool enable_legacy_fast_update; 900 bool disable_dc_mode_overwrite; 901 }; 902 903 struct gpu_info_soc_bounding_box_v1_0; 904 struct dc { 905 struct dc_debug_options debug; 906 struct dc_versions versions; 907 struct dc_caps caps; 908 struct dc_cap_funcs cap_funcs; 909 struct dc_config config; 910 struct dc_bounding_box_overrides bb_overrides; 911 struct dc_bug_wa work_arounds; 912 struct dc_context *ctx; 913 struct dc_phy_addr_space_config vm_pa_config; 914 915 uint8_t link_count; 916 struct dc_link *links[MAX_PIPES * 2]; 917 struct link_service *link_srv; 918 919 struct dc_state *current_state; 920 struct resource_pool *res_pool; 921 922 struct clk_mgr *clk_mgr; 923 924 /* Display Engine Clock levels */ 925 struct dm_pp_clock_levels sclk_lvls; 926 927 /* Inputs into BW and WM calculations. */ 928 struct bw_calcs_dceip *bw_dceip; 929 struct bw_calcs_vbios *bw_vbios; 930 struct dcn_soc_bounding_box *dcn_soc; 931 struct dcn_ip_params *dcn_ip; 932 struct display_mode_lib dml; 933 934 /* HW functions */ 935 struct hw_sequencer_funcs hwss; 936 struct dce_hwseq *hwseq; 937 938 /* Require to optimize clocks and bandwidth for added/removed planes */ 939 bool optimized_required; 940 bool wm_optimized_required; 941 bool idle_optimizations_allowed; 942 bool enable_c20_dtm_b0; 943 944 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 945 946 /* FBC compressor */ 947 struct compressor *fbc_compressor; 948 949 struct dc_debug_data debug_data; 950 struct dpcd_vendor_signature vendor_signature; 951 952 const char *build_id; 953 struct vm_helper *vm_helper; 954 955 uint32_t *dcn_reg_offsets; 956 uint32_t *nbio_reg_offsets; 957 958 /* Scratch memory */ 959 struct { 960 struct { 961 /* 962 * For matching clock_limits table in driver with table 963 * from PMFW. 964 */ 965 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 966 } update_bw_bounding_box; 967 } scratch; 968 }; 969 970 enum frame_buffer_mode { 971 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 972 FRAME_BUFFER_MODE_ZFB_ONLY, 973 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 974 } ; 975 976 struct dchub_init_data { 977 int64_t zfb_phys_addr_base; 978 int64_t zfb_mc_base_addr; 979 uint64_t zfb_size_in_byte; 980 enum frame_buffer_mode fb_mode; 981 bool dchub_initialzied; 982 bool dchub_info_valid; 983 }; 984 985 struct dc_init_data { 986 struct hw_asic_id asic_id; 987 void *driver; /* ctx */ 988 struct cgs_device *cgs_device; 989 struct dc_bounding_box_overrides bb_overrides; 990 991 int num_virtual_links; 992 /* 993 * If 'vbios_override' not NULL, it will be called instead 994 * of the real VBIOS. Intended use is Diagnostics on FPGA. 995 */ 996 struct dc_bios *vbios_override; 997 enum dce_environment dce_environment; 998 999 struct dmub_offload_funcs *dmub_if; 1000 struct dc_reg_helper_state *dmub_offload; 1001 1002 struct dc_config flags; 1003 uint64_t log_mask; 1004 1005 struct dpcd_vendor_signature vendor_signature; 1006 bool force_smu_not_present; 1007 /* 1008 * IP offset for run time initializaion of register addresses 1009 * 1010 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1011 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1012 * before them. 1013 */ 1014 uint32_t *dcn_reg_offsets; 1015 uint32_t *nbio_reg_offsets; 1016 }; 1017 1018 struct dc_callback_init { 1019 struct cp_psp cp_psp; 1020 }; 1021 1022 struct dc *dc_create(const struct dc_init_data *init_params); 1023 void dc_hardware_init(struct dc *dc); 1024 1025 int dc_get_vmid_use_vector(struct dc *dc); 1026 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1027 /* Returns the number of vmids supported */ 1028 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1029 void dc_init_callbacks(struct dc *dc, 1030 const struct dc_callback_init *init_params); 1031 void dc_deinit_callbacks(struct dc *dc); 1032 void dc_destroy(struct dc **dc); 1033 1034 /* Surface Interfaces */ 1035 1036 enum { 1037 TRANSFER_FUNC_POINTS = 1025 1038 }; 1039 1040 struct dc_hdr_static_metadata { 1041 /* display chromaticities and white point in units of 0.00001 */ 1042 unsigned int chromaticity_green_x; 1043 unsigned int chromaticity_green_y; 1044 unsigned int chromaticity_blue_x; 1045 unsigned int chromaticity_blue_y; 1046 unsigned int chromaticity_red_x; 1047 unsigned int chromaticity_red_y; 1048 unsigned int chromaticity_white_point_x; 1049 unsigned int chromaticity_white_point_y; 1050 1051 uint32_t min_luminance; 1052 uint32_t max_luminance; 1053 uint32_t maximum_content_light_level; 1054 uint32_t maximum_frame_average_light_level; 1055 }; 1056 1057 enum dc_transfer_func_type { 1058 TF_TYPE_PREDEFINED, 1059 TF_TYPE_DISTRIBUTED_POINTS, 1060 TF_TYPE_BYPASS, 1061 TF_TYPE_HWPWL 1062 }; 1063 1064 struct dc_transfer_func_distributed_points { 1065 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1066 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1067 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1068 1069 uint16_t end_exponent; 1070 uint16_t x_point_at_y1_red; 1071 uint16_t x_point_at_y1_green; 1072 uint16_t x_point_at_y1_blue; 1073 }; 1074 1075 enum dc_transfer_func_predefined { 1076 TRANSFER_FUNCTION_SRGB, 1077 TRANSFER_FUNCTION_BT709, 1078 TRANSFER_FUNCTION_PQ, 1079 TRANSFER_FUNCTION_LINEAR, 1080 TRANSFER_FUNCTION_UNITY, 1081 TRANSFER_FUNCTION_HLG, 1082 TRANSFER_FUNCTION_HLG12, 1083 TRANSFER_FUNCTION_GAMMA22, 1084 TRANSFER_FUNCTION_GAMMA24, 1085 TRANSFER_FUNCTION_GAMMA26 1086 }; 1087 1088 1089 struct dc_transfer_func { 1090 struct kref refcount; 1091 enum dc_transfer_func_type type; 1092 enum dc_transfer_func_predefined tf; 1093 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1094 uint32_t sdr_ref_white_level; 1095 union { 1096 struct pwl_params pwl; 1097 struct dc_transfer_func_distributed_points tf_pts; 1098 }; 1099 }; 1100 1101 1102 union dc_3dlut_state { 1103 struct { 1104 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1105 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1106 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1107 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1108 uint32_t mpc_rmu1_mux:4; 1109 uint32_t mpc_rmu2_mux:4; 1110 uint32_t reserved:15; 1111 } bits; 1112 uint32_t raw; 1113 }; 1114 1115 1116 struct dc_3dlut { 1117 struct kref refcount; 1118 struct tetrahedral_params lut_3d; 1119 struct fixed31_32 hdr_multiplier; 1120 union dc_3dlut_state state; 1121 }; 1122 /* 1123 * This structure is filled in by dc_surface_get_status and contains 1124 * the last requested address and the currently active address so the called 1125 * can determine if there are any outstanding flips 1126 */ 1127 struct dc_plane_status { 1128 struct dc_plane_address requested_address; 1129 struct dc_plane_address current_address; 1130 bool is_flip_pending; 1131 bool is_right_eye; 1132 }; 1133 1134 union surface_update_flags { 1135 1136 struct { 1137 uint32_t addr_update:1; 1138 /* Medium updates */ 1139 uint32_t dcc_change:1; 1140 uint32_t color_space_change:1; 1141 uint32_t horizontal_mirror_change:1; 1142 uint32_t per_pixel_alpha_change:1; 1143 uint32_t global_alpha_change:1; 1144 uint32_t hdr_mult:1; 1145 uint32_t rotation_change:1; 1146 uint32_t swizzle_change:1; 1147 uint32_t scaling_change:1; 1148 uint32_t position_change:1; 1149 uint32_t in_transfer_func_change:1; 1150 uint32_t input_csc_change:1; 1151 uint32_t coeff_reduction_change:1; 1152 uint32_t output_tf_change:1; 1153 uint32_t pixel_format_change:1; 1154 uint32_t plane_size_change:1; 1155 uint32_t gamut_remap_change:1; 1156 1157 /* Full updates */ 1158 uint32_t new_plane:1; 1159 uint32_t bpp_change:1; 1160 uint32_t gamma_change:1; 1161 uint32_t bandwidth_change:1; 1162 uint32_t clock_change:1; 1163 uint32_t stereo_format_change:1; 1164 uint32_t lut_3d:1; 1165 uint32_t tmz_changed:1; 1166 uint32_t full_update:1; 1167 } bits; 1168 1169 uint32_t raw; 1170 }; 1171 1172 struct dc_plane_state { 1173 struct dc_plane_address address; 1174 struct dc_plane_flip_time time; 1175 bool triplebuffer_flips; 1176 struct scaling_taps scaling_quality; 1177 struct rect src_rect; 1178 struct rect dst_rect; 1179 struct rect clip_rect; 1180 1181 struct plane_size plane_size; 1182 union dc_tiling_info tiling_info; 1183 1184 struct dc_plane_dcc_param dcc; 1185 1186 struct dc_gamma *gamma_correction; 1187 struct dc_transfer_func *in_transfer_func; 1188 struct dc_bias_and_scale *bias_and_scale; 1189 struct dc_csc_transform input_csc_color_matrix; 1190 struct fixed31_32 coeff_reduction_factor; 1191 struct fixed31_32 hdr_mult; 1192 struct colorspace_transform gamut_remap_matrix; 1193 1194 // TODO: No longer used, remove 1195 struct dc_hdr_static_metadata hdr_static_ctx; 1196 1197 enum dc_color_space color_space; 1198 1199 struct dc_3dlut *lut3d_func; 1200 struct dc_transfer_func *in_shaper_func; 1201 struct dc_transfer_func *blend_tf; 1202 1203 struct dc_transfer_func *gamcor_tf; 1204 enum surface_pixel_format format; 1205 enum dc_rotation_angle rotation; 1206 enum plane_stereo_format stereo_format; 1207 1208 bool is_tiling_rotated; 1209 bool per_pixel_alpha; 1210 bool pre_multiplied_alpha; 1211 bool global_alpha; 1212 int global_alpha_value; 1213 bool visible; 1214 bool flip_immediate; 1215 bool horizontal_mirror; 1216 int layer_index; 1217 1218 union surface_update_flags update_flags; 1219 bool flip_int_enabled; 1220 bool skip_manual_trigger; 1221 1222 /* private to DC core */ 1223 struct dc_plane_status status; 1224 struct dc_context *ctx; 1225 1226 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1227 bool force_full_update; 1228 1229 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1230 1231 /* private to dc_surface.c */ 1232 enum dc_irq_source irq_source; 1233 struct kref refcount; 1234 struct tg_color visual_confirm_color; 1235 1236 bool is_statically_allocated; 1237 }; 1238 1239 struct dc_plane_info { 1240 struct plane_size plane_size; 1241 union dc_tiling_info tiling_info; 1242 struct dc_plane_dcc_param dcc; 1243 enum surface_pixel_format format; 1244 enum dc_rotation_angle rotation; 1245 enum plane_stereo_format stereo_format; 1246 enum dc_color_space color_space; 1247 bool horizontal_mirror; 1248 bool visible; 1249 bool per_pixel_alpha; 1250 bool pre_multiplied_alpha; 1251 bool global_alpha; 1252 int global_alpha_value; 1253 bool input_csc_enabled; 1254 int layer_index; 1255 }; 1256 1257 struct dc_scaling_info { 1258 struct rect src_rect; 1259 struct rect dst_rect; 1260 struct rect clip_rect; 1261 struct scaling_taps scaling_quality; 1262 }; 1263 1264 struct dc_surface_update { 1265 struct dc_plane_state *surface; 1266 1267 /* isr safe update parameters. null means no updates */ 1268 const struct dc_flip_addrs *flip_addr; 1269 const struct dc_plane_info *plane_info; 1270 const struct dc_scaling_info *scaling_info; 1271 struct fixed31_32 hdr_mult; 1272 /* following updates require alloc/sleep/spin that is not isr safe, 1273 * null means no updates 1274 */ 1275 const struct dc_gamma *gamma; 1276 const struct dc_transfer_func *in_transfer_func; 1277 1278 const struct dc_csc_transform *input_csc_color_matrix; 1279 const struct fixed31_32 *coeff_reduction_factor; 1280 const struct dc_transfer_func *func_shaper; 1281 const struct dc_3dlut *lut3d_func; 1282 const struct dc_transfer_func *blend_tf; 1283 const struct colorspace_transform *gamut_remap_matrix; 1284 }; 1285 1286 /* 1287 * Create a new surface with default parameters; 1288 */ 1289 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1290 const struct dc_plane_status *dc_plane_get_status( 1291 const struct dc_plane_state *plane_state); 1292 1293 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1294 void dc_plane_state_release(struct dc_plane_state *plane_state); 1295 1296 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1297 void dc_gamma_release(struct dc_gamma **dc_gamma); 1298 struct dc_gamma *dc_create_gamma(void); 1299 1300 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1301 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1302 struct dc_transfer_func *dc_create_transfer_func(void); 1303 1304 struct dc_3dlut *dc_create_3dlut_func(void); 1305 void dc_3dlut_func_release(struct dc_3dlut *lut); 1306 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1307 1308 void dc_post_update_surfaces_to_stream( 1309 struct dc *dc); 1310 1311 #include "dc_stream.h" 1312 1313 /** 1314 * struct dc_validation_set - Struct to store surface/stream associations for validation 1315 */ 1316 struct dc_validation_set { 1317 /** 1318 * @stream: Stream state properties 1319 */ 1320 struct dc_stream_state *stream; 1321 1322 /** 1323 * @plane_state: Surface state 1324 */ 1325 struct dc_plane_state *plane_states[MAX_SURFACES]; 1326 1327 /** 1328 * @plane_count: Total of active planes 1329 */ 1330 uint8_t plane_count; 1331 }; 1332 1333 bool dc_validate_boot_timing(const struct dc *dc, 1334 const struct dc_sink *sink, 1335 struct dc_crtc_timing *crtc_timing); 1336 1337 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1338 1339 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1340 1341 enum dc_status dc_validate_with_context(struct dc *dc, 1342 const struct dc_validation_set set[], 1343 int set_count, 1344 struct dc_state *context, 1345 bool fast_validate); 1346 1347 bool dc_set_generic_gpio_for_stereo(bool enable, 1348 struct gpio_service *gpio_service); 1349 1350 /* 1351 * fast_validate: we return after determining if we can support the new state, 1352 * but before we populate the programming info 1353 */ 1354 enum dc_status dc_validate_global_state( 1355 struct dc *dc, 1356 struct dc_state *new_ctx, 1357 bool fast_validate); 1358 1359 1360 void dc_resource_state_construct( 1361 const struct dc *dc, 1362 struct dc_state *dst_ctx); 1363 1364 bool dc_acquire_release_mpc_3dlut( 1365 struct dc *dc, bool acquire, 1366 struct dc_stream_state *stream, 1367 struct dc_3dlut **lut, 1368 struct dc_transfer_func **shaper); 1369 1370 void dc_resource_state_copy_construct( 1371 const struct dc_state *src_ctx, 1372 struct dc_state *dst_ctx); 1373 1374 void dc_resource_state_copy_construct_current( 1375 const struct dc *dc, 1376 struct dc_state *dst_ctx); 1377 1378 void dc_resource_state_destruct(struct dc_state *context); 1379 1380 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1381 1382 enum dc_status dc_commit_streams(struct dc *dc, 1383 struct dc_stream_state *streams[], 1384 uint8_t stream_count); 1385 1386 struct dc_state *dc_create_state(struct dc *dc); 1387 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1388 void dc_retain_state(struct dc_state *context); 1389 void dc_release_state(struct dc_state *context); 1390 1391 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1392 struct dc_stream_state *stream, 1393 int mpcc_inst); 1394 1395 1396 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1397 1398 /* The function returns minimum bandwidth required to drive a given timing 1399 * return - minimum required timing bandwidth in kbps. 1400 */ 1401 uint32_t dc_bandwidth_in_kbps_from_timing(const struct dc_crtc_timing *timing); 1402 1403 /* Link Interfaces */ 1404 /* 1405 * A link contains one or more sinks and their connected status. 1406 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1407 */ 1408 struct dc_link { 1409 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1410 unsigned int sink_count; 1411 struct dc_sink *local_sink; 1412 unsigned int link_index; 1413 enum dc_connection_type type; 1414 enum signal_type connector_signal; 1415 enum dc_irq_source irq_source_hpd; 1416 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1417 1418 bool is_hpd_filter_disabled; 1419 bool dp_ss_off; 1420 1421 /** 1422 * @link_state_valid: 1423 * 1424 * If there is no link and local sink, this variable should be set to 1425 * false. Otherwise, it should be set to true; usually, the function 1426 * core_link_enable_stream sets this field to true. 1427 */ 1428 bool link_state_valid; 1429 bool aux_access_disabled; 1430 bool sync_lt_in_progress; 1431 bool skip_stream_reenable; 1432 bool is_internal_display; 1433 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1434 bool is_dig_mapping_flexible; 1435 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1436 bool is_hpd_pending; /* Indicates a new received hpd */ 1437 bool is_automated; /* Indicates automated testing */ 1438 1439 bool edp_sink_present; 1440 1441 struct dp_trace dp_trace; 1442 1443 /* caps is the same as reported_link_cap. link_traing use 1444 * reported_link_cap. Will clean up. TODO 1445 */ 1446 struct dc_link_settings reported_link_cap; 1447 struct dc_link_settings verified_link_cap; 1448 struct dc_link_settings cur_link_settings; 1449 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1450 struct dc_link_settings preferred_link_setting; 1451 /* preferred_training_settings are override values that 1452 * come from DM. DM is responsible for the memory 1453 * management of the override pointers. 1454 */ 1455 struct dc_link_training_overrides preferred_training_settings; 1456 struct dp_audio_test_data audio_test_data; 1457 1458 uint8_t ddc_hw_inst; 1459 1460 uint8_t hpd_src; 1461 1462 uint8_t link_enc_hw_inst; 1463 /* DIG link encoder ID. Used as index in link encoder resource pool. 1464 * For links with fixed mapping to DIG, this is not changed after dc_link 1465 * object creation. 1466 */ 1467 enum engine_id eng_id; 1468 1469 bool test_pattern_enabled; 1470 union compliance_test_state compliance_test_state; 1471 1472 void *priv; 1473 1474 struct ddc_service *ddc; 1475 1476 enum dp_panel_mode panel_mode; 1477 bool aux_mode; 1478 1479 /* Private to DC core */ 1480 1481 const struct dc *dc; 1482 1483 struct dc_context *ctx; 1484 1485 struct panel_cntl *panel_cntl; 1486 struct link_encoder *link_enc; 1487 struct graphics_object_id link_id; 1488 /* Endpoint type distinguishes display endpoints which do not have entries 1489 * in the BIOS connector table from those that do. Helps when tracking link 1490 * encoder to display endpoint assignments. 1491 */ 1492 enum display_endpoint_type ep_type; 1493 union ddi_channel_mapping ddi_channel_mapping; 1494 struct connector_device_tag_info device_tag; 1495 struct dpcd_caps dpcd_caps; 1496 uint32_t dongle_max_pix_clk; 1497 unsigned short chip_caps; 1498 unsigned int dpcd_sink_count; 1499 struct hdcp_caps hdcp_caps; 1500 enum edp_revision edp_revision; 1501 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1502 1503 struct psr_settings psr_settings; 1504 1505 /* Drive settings read from integrated info table */ 1506 struct dc_lane_settings bios_forced_drive_settings; 1507 1508 /* Vendor specific LTTPR workaround variables */ 1509 uint8_t vendor_specific_lttpr_link_rate_wa; 1510 bool apply_vendor_specific_lttpr_link_rate_wa; 1511 1512 /* MST record stream using this link */ 1513 struct link_flags { 1514 bool dp_keep_receiver_powered; 1515 bool dp_skip_DID2; 1516 bool dp_skip_reset_segment; 1517 bool dp_skip_fs_144hz; 1518 bool dp_mot_reset_segment; 1519 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1520 bool dpia_mst_dsc_always_on; 1521 /* Forced DPIA into TBT3 compatibility mode. */ 1522 bool dpia_forced_tbt3_mode; 1523 bool dongle_mode_timing_override; 1524 bool blank_stream_on_ocs_change; 1525 } wa_flags; 1526 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1527 1528 struct dc_link_status link_status; 1529 struct dprx_states dprx_states; 1530 1531 struct gpio *hpd_gpio; 1532 enum dc_link_fec_state fec_state; 1533 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1534 1535 struct dc_panel_config panel_config; 1536 struct phy_state phy_state; 1537 // BW ALLOCATON USB4 ONLY 1538 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1539 }; 1540 1541 /* Return an enumerated dc_link. 1542 * dc_link order is constant and determined at 1543 * boot time. They cannot be created or destroyed. 1544 * Use dc_get_caps() to get number of links. 1545 */ 1546 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1547 1548 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1549 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1550 const struct dc_link *link, 1551 unsigned int *inst_out); 1552 1553 /* Return an array of link pointers to edp links. */ 1554 void dc_get_edp_links(const struct dc *dc, 1555 struct dc_link **edp_links, 1556 int *edp_num); 1557 1558 /* The function initiates detection handshake over the given link. It first 1559 * determines if there are display connections over the link. If so it initiates 1560 * detection protocols supported by the connected receiver device. The function 1561 * contains protocol specific handshake sequences which are sometimes mandatory 1562 * to establish a proper connection between TX and RX. So it is always 1563 * recommended to call this function as the first link operation upon HPD event 1564 * or power up event. Upon completion, the function will update link structure 1565 * in place based on latest RX capabilities. The function may also cause dpms 1566 * to be reset to off for all currently enabled streams to the link. It is DM's 1567 * responsibility to serialize detection and DPMS updates. 1568 * 1569 * @reason - Indicate which event triggers this detection. dc may customize 1570 * detection flow depending on the triggering events. 1571 * return false - if detection is not fully completed. This could happen when 1572 * there is an unrecoverable error during detection or detection is partially 1573 * completed (detection has been delegated to dm mst manager ie. 1574 * link->connection_type == dc_connection_mst_branch when returning false). 1575 * return true - detection is completed, link has been fully updated with latest 1576 * detection result. 1577 */ 1578 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1579 1580 struct dc_sink_init_data; 1581 1582 /* When link connection type is dc_connection_mst_branch, remote sink can be 1583 * added to the link. The interface creates a remote sink and associates it with 1584 * current link. The sink will be retained by link until remove remote sink is 1585 * called. 1586 * 1587 * @dc_link - link the remote sink will be added to. 1588 * @edid - byte array of EDID raw data. 1589 * @len - size of the edid in byte 1590 * @init_data - 1591 */ 1592 struct dc_sink *dc_link_add_remote_sink( 1593 struct dc_link *dc_link, 1594 const uint8_t *edid, 1595 int len, 1596 struct dc_sink_init_data *init_data); 1597 1598 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1599 * @link - link the sink should be removed from 1600 * @sink - sink to be removed. 1601 */ 1602 void dc_link_remove_remote_sink( 1603 struct dc_link *link, 1604 struct dc_sink *sink); 1605 1606 /* Enable HPD interrupt handler for a given link */ 1607 void dc_link_enable_hpd(const struct dc_link *link); 1608 1609 /* Disable HPD interrupt handler for a given link */ 1610 void dc_link_disable_hpd(const struct dc_link *link); 1611 1612 /* determine if there is a sink connected to the link 1613 * 1614 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1615 * return - false if an unexpected error occurs, true otherwise. 1616 * 1617 * NOTE: This function doesn't detect downstream sink connections i.e 1618 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1619 * return dc_connection_single if the branch device is connected despite of 1620 * downstream sink's connection status. 1621 */ 1622 bool dc_link_detect_connection_type(struct dc_link *link, 1623 enum dc_connection_type *type); 1624 1625 /* query current hpd pin value 1626 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1627 * 1628 */ 1629 bool dc_link_get_hpd_state(struct dc_link *link); 1630 1631 /* Getter for cached link status from given link */ 1632 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1633 1634 /* enable/disable hardware HPD filter. 1635 * 1636 * @link - The link the HPD pin is associated with. 1637 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1638 * handler once after no HPD change has been detected within dc default HPD 1639 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1640 * pulses within default HPD interval, no HPD event will be received until HPD 1641 * toggles have stopped. Then HPD event will be queued to irq handler once after 1642 * dc default HPD filtering interval since last HPD event. 1643 * 1644 * @enable = false - disable hardware HPD filter. HPD event will be queued 1645 * immediately to irq handler after no HPD change has been detected within 1646 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1647 */ 1648 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1649 1650 /* submit i2c read/write payloads through ddc channel 1651 * @link_index - index to a link with ddc in i2c mode 1652 * @cmd - i2c command structure 1653 * return - true if success, false otherwise. 1654 */ 1655 bool dc_submit_i2c( 1656 struct dc *dc, 1657 uint32_t link_index, 1658 struct i2c_command *cmd); 1659 1660 /* submit i2c read/write payloads through oem channel 1661 * @link_index - index to a link with ddc in i2c mode 1662 * @cmd - i2c command structure 1663 * return - true if success, false otherwise. 1664 */ 1665 bool dc_submit_i2c_oem( 1666 struct dc *dc, 1667 struct i2c_command *cmd); 1668 1669 enum aux_return_code_type; 1670 /* Attempt to transfer the given aux payload. This function does not perform 1671 * retries or handle error states. The reply is returned in the payload->reply 1672 * and the result through operation_result. Returns the number of bytes 1673 * transferred,or -1 on a failure. 1674 */ 1675 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1676 struct aux_payload *payload, 1677 enum aux_return_code_type *operation_result); 1678 1679 bool dc_is_oem_i2c_device_present( 1680 struct dc *dc, 1681 size_t slave_address 1682 ); 1683 1684 /* return true if the connected receiver supports the hdcp version */ 1685 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1686 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1687 1688 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1689 * 1690 * TODO - When defer_handling is true the function will have a different purpose. 1691 * It no longer does complete hpd rx irq handling. We should create a separate 1692 * interface specifically for this case. 1693 * 1694 * Return: 1695 * true - Downstream port status changed. DM should call DC to do the 1696 * detection. 1697 * false - no change in Downstream port status. No further action required 1698 * from DM. 1699 */ 1700 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1701 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1702 bool defer_handling, bool *has_left_work); 1703 /* handle DP specs define test automation sequence*/ 1704 void dc_link_dp_handle_automated_test(struct dc_link *link); 1705 1706 /* handle DP Link loss sequence and try to recover RX link loss with best 1707 * effort 1708 */ 1709 void dc_link_dp_handle_link_loss(struct dc_link *link); 1710 1711 /* Determine if hpd rx irq should be handled or ignored 1712 * return true - hpd rx irq should be handled. 1713 * return false - it is safe to ignore hpd rx irq event 1714 */ 1715 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1716 1717 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1718 * @link - link the hpd irq data associated with 1719 * @hpd_irq_dpcd_data - input hpd irq data 1720 * return - true if hpd irq data indicates a link lost 1721 */ 1722 bool dc_link_check_link_loss_status(struct dc_link *link, 1723 union hpd_irq_data *hpd_irq_dpcd_data); 1724 1725 /* Read hpd rx irq data from a given link 1726 * @link - link where the hpd irq data should be read from 1727 * @irq_data - output hpd irq data 1728 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1729 * read has failed. 1730 */ 1731 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1732 struct dc_link *link, 1733 union hpd_irq_data *irq_data); 1734 1735 /* The function clears recorded DP RX states in the link. DM should call this 1736 * function when it is resuming from S3 power state to previously connected links. 1737 * 1738 * TODO - in the future we should consider to expand link resume interface to 1739 * support clearing previous rx states. So we don't have to rely on dm to call 1740 * this interface explicitly. 1741 */ 1742 void dc_link_clear_dprx_states(struct dc_link *link); 1743 1744 /* Destruct the mst topology of the link and reset the allocated payload table 1745 * 1746 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1747 * still wants to reset MST topology on an unplug event */ 1748 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1749 1750 /* The function calculates effective DP link bandwidth when a given link is 1751 * using the given link settings. 1752 * 1753 * return - total effective link bandwidth in kbps. 1754 */ 1755 uint32_t dc_link_bandwidth_kbps( 1756 const struct dc_link *link, 1757 const struct dc_link_settings *link_setting); 1758 1759 /* The function takes a snapshot of current link resource allocation state 1760 * @dc: pointer to dc of the dm calling this 1761 * @map: a dc link resource snapshot defined internally to dc. 1762 * 1763 * DM needs to capture a snapshot of current link resource allocation mapping 1764 * and store it in its persistent storage. 1765 * 1766 * Some of the link resource is using first come first serve policy. 1767 * The allocation mapping depends on original hotplug order. This information 1768 * is lost after driver is loaded next time. The snapshot is used in order to 1769 * restore link resource to its previous state so user will get consistent 1770 * link capability allocation across reboot. 1771 * 1772 */ 1773 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1774 1775 /* This function restores link resource allocation state from a snapshot 1776 * @dc: pointer to dc of the dm calling this 1777 * @map: a dc link resource snapshot defined internally to dc. 1778 * 1779 * DM needs to call this function after initial link detection on boot and 1780 * before first commit streams to restore link resource allocation state 1781 * from previous boot session. 1782 * 1783 * Some of the link resource is using first come first serve policy. 1784 * The allocation mapping depends on original hotplug order. This information 1785 * is lost after driver is loaded next time. The snapshot is used in order to 1786 * restore link resource to its previous state so user will get consistent 1787 * link capability allocation across reboot. 1788 * 1789 */ 1790 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1791 1792 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1793 * interface i.e stream_update->dsc_config 1794 */ 1795 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1796 1797 /* translate a raw link rate data to bandwidth in kbps */ 1798 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 1799 1800 /* determine the optimal bandwidth given link and required bw. 1801 * @link - current detected link 1802 * @req_bw - requested bandwidth in kbps 1803 * @link_settings - returned most optimal link settings that can fit the 1804 * requested bandwidth 1805 * return - false if link can't support requested bandwidth, true if link 1806 * settings is found. 1807 */ 1808 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1809 struct dc_link_settings *link_settings, 1810 uint32_t req_bw); 1811 1812 /* return the max dp link settings can be driven by the link without considering 1813 * connected RX device and its capability 1814 */ 1815 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1816 struct dc_link_settings *max_link_enc_cap); 1817 1818 /* determine when the link is driving MST mode, what DP link channel coding 1819 * format will be used. The decision will remain unchanged until next HPD event. 1820 * 1821 * @link - a link with DP RX connection 1822 * return - if stream is committed to this link with MST signal type, type of 1823 * channel coding format dc will choose. 1824 */ 1825 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1826 const struct dc_link *link); 1827 1828 /* get max dp link settings the link can enable with all things considered. (i.e 1829 * TX/RX/Cable capabilities and dp override policies. 1830 * 1831 * @link - a link with DP RX connection 1832 * return - max dp link settings the link can enable. 1833 * 1834 */ 1835 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 1836 1837 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 1838 * to a link with dp connector signal type. 1839 * @link - a link with dp connector signal type 1840 * return - true if connected, false otherwise 1841 */ 1842 bool dc_link_is_dp_sink_present(struct dc_link *link); 1843 1844 /* Force DP lane settings update to main-link video signal and notify the change 1845 * to DP RX via DPCD. This is a debug interface used for video signal integrity 1846 * tuning purpose. The interface assumes link has already been enabled with DP 1847 * signal. 1848 * 1849 * @lt_settings - a container structure with desired hw_lane_settings 1850 */ 1851 void dc_link_set_drive_settings(struct dc *dc, 1852 struct link_training_settings *lt_settings, 1853 struct dc_link *link); 1854 1855 /* Enable a test pattern in Link or PHY layer in an active link for compliance 1856 * test or debugging purpose. The test pattern will remain until next un-plug. 1857 * 1858 * @link - active link with DP signal output enabled. 1859 * @test_pattern - desired test pattern to output. 1860 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 1861 * @test_pattern_color_space - for video test pattern choose a desired color 1862 * space. 1863 * @p_link_settings - For PHY pattern choose a desired link settings 1864 * @p_custom_pattern - some test pattern will require a custom input to 1865 * customize some pattern details. Otherwise keep it to NULL. 1866 * @cust_pattern_size - size of the custom pattern input. 1867 * 1868 */ 1869 bool dc_link_dp_set_test_pattern( 1870 struct dc_link *link, 1871 enum dp_test_pattern test_pattern, 1872 enum dp_test_pattern_color_space test_pattern_color_space, 1873 const struct link_training_settings *p_link_settings, 1874 const unsigned char *p_custom_pattern, 1875 unsigned int cust_pattern_size); 1876 1877 /* Force DP link settings to always use a specific value until reboot to a 1878 * specific link. If link has already been enabled, the interface will also 1879 * switch to desired link settings immediately. This is a debug interface to 1880 * generic dp issue trouble shooting. 1881 */ 1882 void dc_link_set_preferred_link_settings(struct dc *dc, 1883 struct dc_link_settings *link_setting, 1884 struct dc_link *link); 1885 1886 /* Force DP link to customize a specific link training behavior by overriding to 1887 * standard DP specs defined protocol. This is a debug interface to trouble shoot 1888 * display specific link training issues or apply some display specific 1889 * workaround in link training. 1890 * 1891 * @link_settings - if not NULL, force preferred link settings to the link. 1892 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 1893 * will apply this particular override in future link training. If NULL is 1894 * passed in, dc resets previous overrides. 1895 * NOTE: DM must keep the memory from override pointers until DM resets preferred 1896 * training settings. 1897 */ 1898 void dc_link_set_preferred_training_settings(struct dc *dc, 1899 struct dc_link_settings *link_setting, 1900 struct dc_link_training_overrides *lt_overrides, 1901 struct dc_link *link, 1902 bool skip_immediate_retrain); 1903 1904 /* return - true if FEC is supported with connected DP RX, false otherwise */ 1905 bool dc_link_is_fec_supported(const struct dc_link *link); 1906 1907 /* query FEC enablement policy to determine if FEC will be enabled by dc during 1908 * link enablement. 1909 * return - true if FEC should be enabled, false otherwise. 1910 */ 1911 bool dc_link_should_enable_fec(const struct dc_link *link); 1912 1913 /* determine lttpr mode the current link should be enabled with a specific link 1914 * settings. 1915 */ 1916 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 1917 struct dc_link_settings *link_setting); 1918 1919 /* Force DP RX to update its power state. 1920 * NOTE: this interface doesn't update dp main-link. Calling this function will 1921 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 1922 * RX power state back upon finish DM specific execution requiring DP RX in a 1923 * specific power state. 1924 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 1925 * state. 1926 */ 1927 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 1928 1929 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 1930 * current value read from extended receiver cap from 02200h - 0220Fh. 1931 * Some DP RX has problems of providing accurate DP receiver caps from extended 1932 * field, this interface is a workaround to revert link back to use base caps. 1933 */ 1934 void dc_link_overwrite_extended_receiver_cap( 1935 struct dc_link *link); 1936 1937 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 1938 bool wait_for_hpd); 1939 1940 /* Set backlight level of an embedded panel (eDP, LVDS). 1941 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 1942 * and 16 bit fractional, where 1.0 is max backlight value. 1943 */ 1944 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 1945 uint32_t backlight_pwm_u16_16, 1946 uint32_t frame_ramp); 1947 1948 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 1949 bool dc_link_set_backlight_level_nits(struct dc_link *link, 1950 bool isHDR, 1951 uint32_t backlight_millinits, 1952 uint32_t transition_time_in_ms); 1953 1954 bool dc_link_get_backlight_level_nits(struct dc_link *link, 1955 uint32_t *backlight_millinits, 1956 uint32_t *backlight_millinits_peak); 1957 1958 int dc_link_get_backlight_level(const struct dc_link *dc_link); 1959 1960 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 1961 1962 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 1963 bool wait, bool force_static, const unsigned int *power_opts); 1964 1965 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 1966 1967 bool dc_link_setup_psr(struct dc_link *dc_link, 1968 const struct dc_stream_state *stream, struct psr_config *psr_config, 1969 struct psr_context *psr_context); 1970 1971 /* On eDP links this function call will stall until T12 has elapsed. 1972 * If the panel is not in power off state, this function will return 1973 * immediately. 1974 */ 1975 bool dc_link_wait_for_t12(struct dc_link *link); 1976 1977 /* Determine if dp trace has been initialized to reflect upto date result * 1978 * return - true if trace is initialized and has valid data. False dp trace 1979 * doesn't have valid result. 1980 */ 1981 bool dc_dp_trace_is_initialized(struct dc_link *link); 1982 1983 /* Query a dp trace flag to indicate if the current dp trace data has been 1984 * logged before 1985 */ 1986 bool dc_dp_trace_is_logged(struct dc_link *link, 1987 bool in_detection); 1988 1989 /* Set dp trace flag to indicate whether DM has already logged the current dp 1990 * trace data. DM can set is_logged to true upon logging and check 1991 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 1992 */ 1993 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 1994 bool in_detection, 1995 bool is_logged); 1996 1997 /* Obtain driver time stamp for last dp link training end. The time stamp is 1998 * formatted based on dm_get_timestamp DM function. 1999 * @in_detection - true to get link training end time stamp of last link 2000 * training in detection sequence. false to get link training end time stamp 2001 * of last link training in commit (dpms) sequence 2002 */ 2003 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2004 bool in_detection); 2005 2006 /* Get how many link training attempts dc has done with latest sequence. 2007 * @in_detection - true to get link training count of last link 2008 * training in detection sequence. false to get link training count of last link 2009 * training in commit (dpms) sequence 2010 */ 2011 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2012 bool in_detection); 2013 2014 /* Get how many link loss has happened since last link training attempts */ 2015 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2016 2017 /* 2018 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2019 */ 2020 /* 2021 * Send a request from DP-Tx requesting to allocate BW remotely after 2022 * allocating it locally. This will get processed by CM and a CB function 2023 * will be called. 2024 * 2025 * @link: pointer to the dc_link struct instance 2026 * @req_bw: The requested bw in Kbyte to allocated 2027 * 2028 * return: none 2029 */ 2030 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2031 2032 /* 2033 * Handle function for when the status of the Request above is complete. 2034 * We will find out the result of allocating on CM and update structs. 2035 * 2036 * @link: pointer to the dc_link struct instance 2037 * @bw: Allocated or Estimated BW depending on the result 2038 * @result: Response type 2039 * 2040 * return: none 2041 */ 2042 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2043 uint8_t bw, uint8_t result); 2044 2045 /* 2046 * Handle the USB4 BW Allocation related functionality here: 2047 * Plug => Try to allocate max bw from timing parameters supported by the sink 2048 * Unplug => de-allocate bw 2049 * 2050 * @link: pointer to the dc_link struct instance 2051 * @peak_bw: Peak bw used by the link/sink 2052 * 2053 * return: allocated bw else return 0 2054 */ 2055 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2056 struct dc_link *link, int peak_bw); 2057 2058 /* 2059 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2060 * available BW for each host router 2061 * 2062 * @dc: pointer to dc struct 2063 * @stream: pointer to all possible streams 2064 * @num_streams: number of valid DPIA streams 2065 * 2066 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2067 */ 2068 bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, 2069 const unsigned int count); 2070 2071 /* Sink Interfaces - A sink corresponds to a display output device */ 2072 2073 struct dc_container_id { 2074 // 128bit GUID in binary form 2075 unsigned char guid[16]; 2076 // 8 byte port ID -> ELD.PortID 2077 unsigned int portId[2]; 2078 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2079 unsigned short manufacturerName; 2080 // 2 byte product code -> ELD.ProductCode 2081 unsigned short productCode; 2082 }; 2083 2084 2085 struct dc_sink_dsc_caps { 2086 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2087 // 'false' if they are sink's DSC caps 2088 bool is_virtual_dpcd_dsc; 2089 #if defined(CONFIG_DRM_AMD_DC_FP) 2090 // 'true' if MST topology supports DSC passthrough for sink 2091 // 'false' if MST topology does not support DSC passthrough 2092 bool is_dsc_passthrough_supported; 2093 #endif 2094 struct dsc_dec_dpcd_caps dsc_dec_caps; 2095 }; 2096 2097 struct dc_sink_fec_caps { 2098 bool is_rx_fec_supported; 2099 bool is_topology_fec_supported; 2100 }; 2101 2102 struct scdc_caps { 2103 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2104 union hdmi_scdc_device_id_data device_id; 2105 }; 2106 2107 /* 2108 * The sink structure contains EDID and other display device properties 2109 */ 2110 struct dc_sink { 2111 enum signal_type sink_signal; 2112 struct dc_edid dc_edid; /* raw edid */ 2113 struct dc_edid_caps edid_caps; /* parse display caps */ 2114 struct dc_container_id *dc_container_id; 2115 uint32_t dongle_max_pix_clk; 2116 void *priv; 2117 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2118 bool converter_disable_audio; 2119 2120 struct scdc_caps scdc_caps; 2121 struct dc_sink_dsc_caps dsc_caps; 2122 struct dc_sink_fec_caps fec_caps; 2123 2124 bool is_vsc_sdp_colorimetry_supported; 2125 2126 /* private to DC core */ 2127 struct dc_link *link; 2128 struct dc_context *ctx; 2129 2130 uint32_t sink_id; 2131 2132 /* private to dc_sink.c */ 2133 // refcount must be the last member in dc_sink, since we want the 2134 // sink structure to be logically cloneable up to (but not including) 2135 // refcount 2136 struct kref refcount; 2137 }; 2138 2139 void dc_sink_retain(struct dc_sink *sink); 2140 void dc_sink_release(struct dc_sink *sink); 2141 2142 struct dc_sink_init_data { 2143 enum signal_type sink_signal; 2144 struct dc_link *link; 2145 uint32_t dongle_max_pix_clk; 2146 bool converter_disable_audio; 2147 }; 2148 2149 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2150 2151 /* Newer interfaces */ 2152 struct dc_cursor { 2153 struct dc_plane_address address; 2154 struct dc_cursor_attributes attributes; 2155 }; 2156 2157 2158 /* Interrupt interfaces */ 2159 enum dc_irq_source dc_interrupt_to_irq_source( 2160 struct dc *dc, 2161 uint32_t src_id, 2162 uint32_t ext_id); 2163 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2164 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2165 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2166 struct dc *dc, uint32_t link_index); 2167 2168 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2169 2170 /* Power Interfaces */ 2171 2172 void dc_set_power_state( 2173 struct dc *dc, 2174 enum dc_acpi_cm_power_state power_state); 2175 void dc_resume(struct dc *dc); 2176 2177 void dc_power_down_on_boot(struct dc *dc); 2178 2179 /* 2180 * HDCP Interfaces 2181 */ 2182 enum hdcp_message_status dc_process_hdcp_msg( 2183 enum signal_type signal, 2184 struct dc_link *link, 2185 struct hdcp_protection_message *message_info); 2186 bool dc_is_dmcu_initialized(struct dc *dc); 2187 2188 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2189 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2190 2191 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 2192 struct dc_cursor_attributes *cursor_attr); 2193 2194 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 2195 2196 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2197 void dc_unlock_memory_clock_frequency(struct dc *dc); 2198 2199 /* set min memory clock to the min required for current mode, max to maxDPM */ 2200 void dc_lock_memory_clock_frequency(struct dc *dc); 2201 2202 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2203 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2204 2205 /* cleanup on driver unload */ 2206 void dc_hardware_release(struct dc *dc); 2207 2208 /* disables fw based mclk switch */ 2209 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2210 2211 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2212 void dc_z10_restore(const struct dc *dc); 2213 void dc_z10_save_init(struct dc *dc); 2214 2215 bool dc_is_dmub_outbox_supported(struct dc *dc); 2216 bool dc_enable_dmub_notifications(struct dc *dc); 2217 2218 void dc_enable_dmub_outbox(struct dc *dc); 2219 2220 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2221 uint32_t link_index, 2222 struct aux_payload *payload); 2223 2224 /* Get dc link index from dpia port index */ 2225 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2226 uint8_t dpia_port_index); 2227 2228 bool dc_process_dmub_set_config_async(struct dc *dc, 2229 uint32_t link_index, 2230 struct set_config_cmd_payload *payload, 2231 struct dmub_notification *notify); 2232 2233 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2234 uint32_t link_index, 2235 uint8_t mst_alloc_slots, 2236 uint8_t *mst_slots_in_use); 2237 2238 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2239 uint32_t hpd_int_enable); 2240 2241 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2242 2243 /* DSC Interfaces */ 2244 #include "dc_dsc.h" 2245 2246 /* Disable acc mode Interfaces */ 2247 void dc_disable_accelerated_mode(struct dc *dc); 2248 2249 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2250 struct dc_stream_state *new_stream); 2251 2252 #endif /* DC_INTERFACE_H_ */ 2253