1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #define DC_VER "3.2.122" 46 47 #define MAX_SURFACES 3 48 #define MAX_PLANES 6 49 #define MAX_STREAMS 6 50 #define MAX_SINKS_PER_LINK 4 51 #define MIN_VIEWPORT_SIZE 12 52 53 /******************************************************************************* 54 * Display Core Interfaces 55 ******************************************************************************/ 56 struct dc_versions { 57 const char *dc_ver; 58 struct dmcu_version dmcu_version; 59 }; 60 61 enum dp_protocol_version { 62 DP_VERSION_1_4, 63 }; 64 65 enum dc_plane_type { 66 DC_PLANE_TYPE_INVALID, 67 DC_PLANE_TYPE_DCE_RGB, 68 DC_PLANE_TYPE_DCE_UNDERLAY, 69 DC_PLANE_TYPE_DCN_UNIVERSAL, 70 }; 71 72 struct dc_plane_cap { 73 enum dc_plane_type type; 74 uint32_t blends_with_above : 1; 75 uint32_t blends_with_below : 1; 76 uint32_t per_pixel_alpha : 1; 77 struct { 78 uint32_t argb8888 : 1; 79 uint32_t nv12 : 1; 80 uint32_t fp16 : 1; 81 uint32_t p010 : 1; 82 uint32_t ayuv : 1; 83 } pixel_format_support; 84 // max upscaling factor x1000 85 // upscaling factors are always >= 1 86 // for example, 1080p -> 8K is 4.0, or 4000 raw value 87 struct { 88 uint32_t argb8888; 89 uint32_t nv12; 90 uint32_t fp16; 91 } max_upscale_factor; 92 // max downscale factor x1000 93 // downscale factors are always <= 1 94 // for example, 8K -> 1080p is 0.25, or 250 raw value 95 struct { 96 uint32_t argb8888; 97 uint32_t nv12; 98 uint32_t fp16; 99 } max_downscale_factor; 100 // minimal width/height 101 uint32_t min_width; 102 uint32_t min_height; 103 }; 104 105 // Color management caps (DPP and MPC) 106 struct rom_curve_caps { 107 uint16_t srgb : 1; 108 uint16_t bt2020 : 1; 109 uint16_t gamma2_2 : 1; 110 uint16_t pq : 1; 111 uint16_t hlg : 1; 112 }; 113 114 struct dpp_color_caps { 115 uint16_t dcn_arch : 1; // all DCE generations treated the same 116 // input lut is different than most LUTs, just plain 256-entry lookup 117 uint16_t input_lut_shared : 1; // shared with DGAM 118 uint16_t icsc : 1; 119 uint16_t dgam_ram : 1; 120 uint16_t post_csc : 1; // before gamut remap 121 uint16_t gamma_corr : 1; 122 123 // hdr_mult and gamut remap always available in DPP (in that order) 124 // 3d lut implies shaper LUT, 125 // it may be shared with MPC - check MPC:shared_3d_lut flag 126 uint16_t hw_3d_lut : 1; 127 uint16_t ogam_ram : 1; // blnd gam 128 uint16_t ocsc : 1; 129 uint16_t dgam_rom_for_yuv : 1; 130 struct rom_curve_caps dgam_rom_caps; 131 struct rom_curve_caps ogam_rom_caps; 132 }; 133 134 struct mpc_color_caps { 135 uint16_t gamut_remap : 1; 136 uint16_t ogam_ram : 1; 137 uint16_t ocsc : 1; 138 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 139 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 140 141 struct rom_curve_caps ogam_rom_caps; 142 }; 143 144 struct dc_color_caps { 145 struct dpp_color_caps dpp; 146 struct mpc_color_caps mpc; 147 }; 148 149 struct dc_caps { 150 uint32_t max_streams; 151 uint32_t max_links; 152 uint32_t max_audios; 153 uint32_t max_slave_planes; 154 uint32_t max_planes; 155 uint32_t max_downscale_ratio; 156 uint32_t i2c_speed_in_khz; 157 uint32_t i2c_speed_in_khz_hdcp; 158 uint32_t dmdata_alloc_size; 159 unsigned int max_cursor_size; 160 unsigned int max_video_width; 161 unsigned int min_horizontal_blanking_period; 162 int linear_pitch_alignment; 163 bool dcc_const_color; 164 bool dynamic_audio; 165 bool is_apu; 166 bool dual_link_dvi; 167 bool post_blend_color_processing; 168 bool force_dp_tps4_for_cp2520; 169 bool disable_dp_clk_share; 170 bool psp_setup_panel_mode; 171 bool extended_aux_timeout_support; 172 bool dmcub_support; 173 uint32_t num_of_internal_disp; 174 enum dp_protocol_version max_dp_protocol_version; 175 unsigned int mall_size_per_mem_channel; 176 unsigned int mall_size_total; 177 unsigned int cursor_cache_size; 178 struct dc_plane_cap planes[MAX_PLANES]; 179 struct dc_color_caps color; 180 }; 181 182 struct dc_bug_wa { 183 bool no_connect_phy_config; 184 bool dedcn20_305_wa; 185 bool skip_clock_update; 186 bool lt_early_cr_pattern; 187 }; 188 189 struct dc_dcc_surface_param { 190 struct dc_size surface_size; 191 enum surface_pixel_format format; 192 enum swizzle_mode_values swizzle_mode; 193 enum dc_scan_direction scan; 194 }; 195 196 struct dc_dcc_setting { 197 unsigned int max_compressed_blk_size; 198 unsigned int max_uncompressed_blk_size; 199 bool independent_64b_blks; 200 #if defined(CONFIG_DRM_AMD_DC_DCN) 201 //These bitfields to be used starting with DCN 3.0 202 struct { 203 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 204 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 205 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 206 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 207 } dcc_controls; 208 #endif 209 }; 210 211 struct dc_surface_dcc_cap { 212 union { 213 struct { 214 struct dc_dcc_setting rgb; 215 } grph; 216 217 struct { 218 struct dc_dcc_setting luma; 219 struct dc_dcc_setting chroma; 220 } video; 221 }; 222 223 bool capable; 224 bool const_color_support; 225 }; 226 227 struct dc_static_screen_params { 228 struct { 229 bool force_trigger; 230 bool cursor_update; 231 bool surface_update; 232 bool overlay_update; 233 } triggers; 234 unsigned int num_frames; 235 }; 236 237 238 /* Surface update type is used by dc_update_surfaces_and_stream 239 * The update type is determined at the very beginning of the function based 240 * on parameters passed in and decides how much programming (or updating) is 241 * going to be done during the call. 242 * 243 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 244 * logical calculations or hardware register programming. This update MUST be 245 * ISR safe on windows. Currently fast update will only be used to flip surface 246 * address. 247 * 248 * UPDATE_TYPE_MED is used for slower updates which require significant hw 249 * re-programming however do not affect bandwidth consumption or clock 250 * requirements. At present, this is the level at which front end updates 251 * that do not require us to run bw_calcs happen. These are in/out transfer func 252 * updates, viewport offset changes, recout size changes and pixel depth changes. 253 * This update can be done at ISR, but we want to minimize how often this happens. 254 * 255 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 256 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 257 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 258 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 259 * a full update. This cannot be done at ISR level and should be a rare event. 260 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 261 * underscan we don't expect to see this call at all. 262 */ 263 264 enum surface_update_type { 265 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 266 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 267 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 268 }; 269 270 /* Forward declaration*/ 271 struct dc; 272 struct dc_plane_state; 273 struct dc_state; 274 275 276 struct dc_cap_funcs { 277 bool (*get_dcc_compression_cap)(const struct dc *dc, 278 const struct dc_dcc_surface_param *input, 279 struct dc_surface_dcc_cap *output); 280 }; 281 282 struct link_training_settings; 283 284 285 /* Structure to hold configuration flags set by dm at dc creation. */ 286 struct dc_config { 287 bool gpu_vm_support; 288 bool disable_disp_pll_sharing; 289 bool fbc_support; 290 bool optimize_edp_link_rate; 291 bool disable_fractional_pwm; 292 bool allow_seamless_boot_optimization; 293 bool power_down_display_on_boot; 294 bool edp_not_connected; 295 bool force_enum_edp; 296 bool forced_clocks; 297 bool allow_lttpr_non_transparent_mode; 298 bool multi_mon_pp_mclk_switch; 299 bool disable_dmcu; 300 bool enable_4to1MPC; 301 #if defined(CONFIG_DRM_AMD_DC_DCN) 302 bool clamp_min_dcfclk; 303 #endif 304 }; 305 306 enum visual_confirm { 307 VISUAL_CONFIRM_DISABLE = 0, 308 VISUAL_CONFIRM_SURFACE = 1, 309 VISUAL_CONFIRM_HDR = 2, 310 VISUAL_CONFIRM_MPCTREE = 4, 311 VISUAL_CONFIRM_PSR = 5, 312 }; 313 314 enum dcc_option { 315 DCC_ENABLE = 0, 316 DCC_DISABLE = 1, 317 DCC_HALF_REQ_DISALBE = 2, 318 }; 319 320 enum pipe_split_policy { 321 MPC_SPLIT_DYNAMIC = 0, 322 MPC_SPLIT_AVOID = 1, 323 MPC_SPLIT_AVOID_MULT_DISP = 2, 324 }; 325 326 enum wm_report_mode { 327 WM_REPORT_DEFAULT = 0, 328 WM_REPORT_OVERRIDE = 1, 329 }; 330 enum dtm_pstate{ 331 dtm_level_p0 = 0,/*highest voltage*/ 332 dtm_level_p1, 333 dtm_level_p2, 334 dtm_level_p3, 335 dtm_level_p4,/*when active_display_count = 0*/ 336 }; 337 338 enum dcn_pwr_state { 339 DCN_PWR_STATE_UNKNOWN = -1, 340 DCN_PWR_STATE_MISSION_MODE = 0, 341 DCN_PWR_STATE_LOW_POWER = 3, 342 }; 343 344 /* 345 * For any clocks that may differ per pipe 346 * only the max is stored in this structure 347 */ 348 struct dc_clocks { 349 int dispclk_khz; 350 int actual_dispclk_khz; 351 int dppclk_khz; 352 int actual_dppclk_khz; 353 int disp_dpp_voltage_level_khz; 354 int dcfclk_khz; 355 int socclk_khz; 356 int dcfclk_deep_sleep_khz; 357 int fclk_khz; 358 int phyclk_khz; 359 int dramclk_khz; 360 bool p_state_change_support; 361 enum dcn_pwr_state pwr_state; 362 /* 363 * Elements below are not compared for the purposes of 364 * optimization required 365 */ 366 bool prev_p_state_change_support; 367 enum dtm_pstate dtm_level; 368 int max_supported_dppclk_khz; 369 int max_supported_dispclk_khz; 370 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 371 int bw_dispclk_khz; 372 }; 373 374 struct dc_bw_validation_profile { 375 bool enable; 376 377 unsigned long long total_ticks; 378 unsigned long long voltage_level_ticks; 379 unsigned long long watermark_ticks; 380 unsigned long long rq_dlg_ticks; 381 382 unsigned long long total_count; 383 unsigned long long skip_fast_count; 384 unsigned long long skip_pass_count; 385 unsigned long long skip_fail_count; 386 }; 387 388 #define BW_VAL_TRACE_SETUP() \ 389 unsigned long long end_tick = 0; \ 390 unsigned long long voltage_level_tick = 0; \ 391 unsigned long long watermark_tick = 0; \ 392 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 393 dm_get_timestamp(dc->ctx) : 0 394 395 #define BW_VAL_TRACE_COUNT() \ 396 if (dc->debug.bw_val_profile.enable) \ 397 dc->debug.bw_val_profile.total_count++ 398 399 #define BW_VAL_TRACE_SKIP(status) \ 400 if (dc->debug.bw_val_profile.enable) { \ 401 if (!voltage_level_tick) \ 402 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 403 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 404 } 405 406 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 407 if (dc->debug.bw_val_profile.enable) \ 408 voltage_level_tick = dm_get_timestamp(dc->ctx) 409 410 #define BW_VAL_TRACE_END_WATERMARKS() \ 411 if (dc->debug.bw_val_profile.enable) \ 412 watermark_tick = dm_get_timestamp(dc->ctx) 413 414 #define BW_VAL_TRACE_FINISH() \ 415 if (dc->debug.bw_val_profile.enable) { \ 416 end_tick = dm_get_timestamp(dc->ctx); \ 417 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 418 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 419 if (watermark_tick) { \ 420 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 421 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 422 } \ 423 } 424 425 union mem_low_power_enable_options { 426 struct { 427 bool i2c: 1; 428 bool dmcu: 1; 429 bool dscl: 1; 430 bool cm: 1; 431 bool mpc: 1; 432 bool optc: 1; 433 } bits; 434 uint32_t u32All; 435 }; 436 437 struct dc_debug_options { 438 enum visual_confirm visual_confirm; 439 bool sanity_checks; 440 bool max_disp_clk; 441 bool surface_trace; 442 bool timing_trace; 443 bool clock_trace; 444 bool validation_trace; 445 bool bandwidth_calcs_trace; 446 int max_downscale_src_width; 447 448 /* stutter efficiency related */ 449 bool disable_stutter; 450 bool use_max_lb; 451 enum dcc_option disable_dcc; 452 enum pipe_split_policy pipe_split_policy; 453 bool force_single_disp_pipe_split; 454 bool voltage_align_fclk; 455 456 bool disable_dfs_bypass; 457 bool disable_dpp_power_gate; 458 bool disable_hubp_power_gate; 459 bool disable_dsc_power_gate; 460 int dsc_min_slice_height_override; 461 int dsc_bpp_increment_div; 462 bool native422_support; 463 bool disable_pplib_wm_range; 464 enum wm_report_mode pplib_wm_report_mode; 465 unsigned int min_disp_clk_khz; 466 unsigned int min_dpp_clk_khz; 467 int sr_exit_time_dpm0_ns; 468 int sr_enter_plus_exit_time_dpm0_ns; 469 int sr_exit_time_ns; 470 int sr_enter_plus_exit_time_ns; 471 int urgent_latency_ns; 472 uint32_t underflow_assert_delay_us; 473 int percent_of_ideal_drambw; 474 int dram_clock_change_latency_ns; 475 bool optimized_watermark; 476 int always_scale; 477 bool disable_pplib_clock_request; 478 bool disable_clock_gate; 479 bool disable_mem_low_power; 480 bool disable_dmcu; 481 bool disable_psr; 482 bool force_abm_enable; 483 bool disable_stereo_support; 484 bool vsr_support; 485 bool performance_trace; 486 bool az_endpoint_mute_only; 487 bool always_use_regamma; 488 bool recovery_enabled; 489 bool avoid_vbios_exec_table; 490 bool scl_reset_length10; 491 bool hdmi20_disable; 492 bool skip_detection_link_training; 493 uint32_t edid_read_retry_times; 494 bool remove_disconnect_edp; 495 unsigned int force_odm_combine; //bit vector based on otg inst 496 #if defined(CONFIG_DRM_AMD_DC_DCN) 497 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 498 #endif 499 unsigned int force_fclk_khz; 500 bool enable_tri_buf; 501 bool dmub_offload_enabled; 502 bool dmcub_emulation; 503 #if defined(CONFIG_DRM_AMD_DC_DCN) 504 bool disable_idle_power_optimizations; 505 unsigned int mall_size_override; 506 unsigned int mall_additional_timer_percent; 507 bool mall_error_as_fatal; 508 #endif 509 bool dmub_command_table; /* for testing only */ 510 struct dc_bw_validation_profile bw_val_profile; 511 bool disable_fec; 512 bool disable_48mhz_pwrdwn; 513 /* This forces a hard min on the DCFCLK requested to SMU/PP 514 * watermarks are not affected. 515 */ 516 unsigned int force_min_dcfclk_mhz; 517 #if defined(CONFIG_DRM_AMD_DC_DCN) 518 int dwb_fi_phase; 519 #endif 520 bool disable_timing_sync; 521 bool cm_in_bypass; 522 int force_clock_mode;/*every mode change.*/ 523 524 bool disable_dram_clock_change_vactive_support; 525 bool validate_dml_output; 526 bool enable_dmcub_surface_flip; 527 bool usbc_combo_phy_reset_wa; 528 bool disable_dsc; 529 bool enable_dram_clock_change_one_display_vactive; 530 union mem_low_power_enable_options enable_mem_low_power; 531 }; 532 533 struct dc_debug_data { 534 uint32_t ltFailCount; 535 uint32_t i2cErrorCount; 536 uint32_t auxErrorCount; 537 }; 538 539 struct dc_phy_addr_space_config { 540 struct { 541 uint64_t start_addr; 542 uint64_t end_addr; 543 uint64_t fb_top; 544 uint64_t fb_offset; 545 uint64_t fb_base; 546 uint64_t agp_top; 547 uint64_t agp_bot; 548 uint64_t agp_base; 549 } system_aperture; 550 551 struct { 552 uint64_t page_table_start_addr; 553 uint64_t page_table_end_addr; 554 uint64_t page_table_base_addr; 555 } gart_config; 556 557 bool valid; 558 bool is_hvm_enabled; 559 uint64_t page_table_default_page_addr; 560 }; 561 562 struct dc_virtual_addr_space_config { 563 uint64_t page_table_base_addr; 564 uint64_t page_table_start_addr; 565 uint64_t page_table_end_addr; 566 uint32_t page_table_block_size_in_bytes; 567 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 568 }; 569 570 struct dc_bounding_box_overrides { 571 int sr_exit_time_ns; 572 int sr_enter_plus_exit_time_ns; 573 int urgent_latency_ns; 574 int percent_of_ideal_drambw; 575 int dram_clock_change_latency_ns; 576 int dummy_clock_change_latency_ns; 577 /* This forces a hard min on the DCFCLK we use 578 * for DML. Unlike the debug option for forcing 579 * DCFCLK, this override affects watermark calculations 580 */ 581 int min_dcfclk_mhz; 582 }; 583 584 struct dc_state; 585 struct resource_pool; 586 struct dce_hwseq; 587 struct gpu_info_soc_bounding_box_v1_0; 588 struct dc { 589 struct dc_versions versions; 590 struct dc_caps caps; 591 struct dc_cap_funcs cap_funcs; 592 struct dc_config config; 593 struct dc_debug_options debug; 594 struct dc_bounding_box_overrides bb_overrides; 595 struct dc_bug_wa work_arounds; 596 struct dc_context *ctx; 597 struct dc_phy_addr_space_config vm_pa_config; 598 599 uint8_t link_count; 600 struct dc_link *links[MAX_PIPES * 2]; 601 602 struct dc_state *current_state; 603 struct resource_pool *res_pool; 604 605 struct clk_mgr *clk_mgr; 606 607 /* Display Engine Clock levels */ 608 struct dm_pp_clock_levels sclk_lvls; 609 610 /* Inputs into BW and WM calculations. */ 611 struct bw_calcs_dceip *bw_dceip; 612 struct bw_calcs_vbios *bw_vbios; 613 #ifdef CONFIG_DRM_AMD_DC_DCN 614 struct dcn_soc_bounding_box *dcn_soc; 615 struct dcn_ip_params *dcn_ip; 616 struct display_mode_lib dml; 617 #endif 618 619 /* HW functions */ 620 struct hw_sequencer_funcs hwss; 621 struct dce_hwseq *hwseq; 622 623 /* Require to optimize clocks and bandwidth for added/removed planes */ 624 bool optimized_required; 625 bool wm_optimized_required; 626 #if defined(CONFIG_DRM_AMD_DC_DCN) 627 bool idle_optimizations_allowed; 628 #endif 629 630 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 631 int optimize_seamless_boot_streams; 632 633 /* FBC compressor */ 634 struct compressor *fbc_compressor; 635 636 struct dc_debug_data debug_data; 637 struct dpcd_vendor_signature vendor_signature; 638 639 const char *build_id; 640 struct vm_helper *vm_helper; 641 }; 642 643 enum frame_buffer_mode { 644 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 645 FRAME_BUFFER_MODE_ZFB_ONLY, 646 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 647 } ; 648 649 struct dchub_init_data { 650 int64_t zfb_phys_addr_base; 651 int64_t zfb_mc_base_addr; 652 uint64_t zfb_size_in_byte; 653 enum frame_buffer_mode fb_mode; 654 bool dchub_initialzied; 655 bool dchub_info_valid; 656 }; 657 658 struct dc_init_data { 659 struct hw_asic_id asic_id; 660 void *driver; /* ctx */ 661 struct cgs_device *cgs_device; 662 struct dc_bounding_box_overrides bb_overrides; 663 664 int num_virtual_links; 665 /* 666 * If 'vbios_override' not NULL, it will be called instead 667 * of the real VBIOS. Intended use is Diagnostics on FPGA. 668 */ 669 struct dc_bios *vbios_override; 670 enum dce_environment dce_environment; 671 672 struct dmub_offload_funcs *dmub_if; 673 struct dc_reg_helper_state *dmub_offload; 674 675 struct dc_config flags; 676 uint64_t log_mask; 677 678 struct dpcd_vendor_signature vendor_signature; 679 #if defined(CONFIG_DRM_AMD_DC_DCN) 680 bool force_smu_not_present; 681 #endif 682 }; 683 684 struct dc_callback_init { 685 #ifdef CONFIG_DRM_AMD_DC_HDCP 686 struct cp_psp cp_psp; 687 #else 688 uint8_t reserved; 689 #endif 690 }; 691 692 struct dc *dc_create(const struct dc_init_data *init_params); 693 void dc_hardware_init(struct dc *dc); 694 695 int dc_get_vmid_use_vector(struct dc *dc); 696 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 697 /* Returns the number of vmids supported */ 698 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 699 void dc_init_callbacks(struct dc *dc, 700 const struct dc_callback_init *init_params); 701 void dc_deinit_callbacks(struct dc *dc); 702 void dc_destroy(struct dc **dc); 703 704 /******************************************************************************* 705 * Surface Interfaces 706 ******************************************************************************/ 707 708 enum { 709 TRANSFER_FUNC_POINTS = 1025 710 }; 711 712 struct dc_hdr_static_metadata { 713 /* display chromaticities and white point in units of 0.00001 */ 714 unsigned int chromaticity_green_x; 715 unsigned int chromaticity_green_y; 716 unsigned int chromaticity_blue_x; 717 unsigned int chromaticity_blue_y; 718 unsigned int chromaticity_red_x; 719 unsigned int chromaticity_red_y; 720 unsigned int chromaticity_white_point_x; 721 unsigned int chromaticity_white_point_y; 722 723 uint32_t min_luminance; 724 uint32_t max_luminance; 725 uint32_t maximum_content_light_level; 726 uint32_t maximum_frame_average_light_level; 727 }; 728 729 enum dc_transfer_func_type { 730 TF_TYPE_PREDEFINED, 731 TF_TYPE_DISTRIBUTED_POINTS, 732 TF_TYPE_BYPASS, 733 TF_TYPE_HWPWL 734 }; 735 736 struct dc_transfer_func_distributed_points { 737 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 738 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 739 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 740 741 uint16_t end_exponent; 742 uint16_t x_point_at_y1_red; 743 uint16_t x_point_at_y1_green; 744 uint16_t x_point_at_y1_blue; 745 }; 746 747 enum dc_transfer_func_predefined { 748 TRANSFER_FUNCTION_SRGB, 749 TRANSFER_FUNCTION_BT709, 750 TRANSFER_FUNCTION_PQ, 751 TRANSFER_FUNCTION_LINEAR, 752 TRANSFER_FUNCTION_UNITY, 753 TRANSFER_FUNCTION_HLG, 754 TRANSFER_FUNCTION_HLG12, 755 TRANSFER_FUNCTION_GAMMA22, 756 TRANSFER_FUNCTION_GAMMA24, 757 TRANSFER_FUNCTION_GAMMA26 758 }; 759 760 761 struct dc_transfer_func { 762 struct kref refcount; 763 enum dc_transfer_func_type type; 764 enum dc_transfer_func_predefined tf; 765 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 766 uint32_t sdr_ref_white_level; 767 union { 768 struct pwl_params pwl; 769 struct dc_transfer_func_distributed_points tf_pts; 770 }; 771 }; 772 773 774 union dc_3dlut_state { 775 struct { 776 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 777 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 778 uint32_t rmu_mux_num:3; /*index of mux to use*/ 779 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 780 uint32_t mpc_rmu1_mux:4; 781 uint32_t mpc_rmu2_mux:4; 782 uint32_t reserved:15; 783 } bits; 784 uint32_t raw; 785 }; 786 787 788 struct dc_3dlut { 789 struct kref refcount; 790 struct tetrahedral_params lut_3d; 791 struct fixed31_32 hdr_multiplier; 792 union dc_3dlut_state state; 793 }; 794 /* 795 * This structure is filled in by dc_surface_get_status and contains 796 * the last requested address and the currently active address so the called 797 * can determine if there are any outstanding flips 798 */ 799 struct dc_plane_status { 800 struct dc_plane_address requested_address; 801 struct dc_plane_address current_address; 802 bool is_flip_pending; 803 bool is_right_eye; 804 }; 805 806 union surface_update_flags { 807 808 struct { 809 uint32_t addr_update:1; 810 /* Medium updates */ 811 uint32_t dcc_change:1; 812 uint32_t color_space_change:1; 813 uint32_t horizontal_mirror_change:1; 814 uint32_t per_pixel_alpha_change:1; 815 uint32_t global_alpha_change:1; 816 uint32_t hdr_mult:1; 817 uint32_t rotation_change:1; 818 uint32_t swizzle_change:1; 819 uint32_t scaling_change:1; 820 uint32_t position_change:1; 821 uint32_t in_transfer_func_change:1; 822 uint32_t input_csc_change:1; 823 uint32_t coeff_reduction_change:1; 824 uint32_t output_tf_change:1; 825 uint32_t pixel_format_change:1; 826 uint32_t plane_size_change:1; 827 uint32_t gamut_remap_change:1; 828 829 /* Full updates */ 830 uint32_t new_plane:1; 831 uint32_t bpp_change:1; 832 uint32_t gamma_change:1; 833 uint32_t bandwidth_change:1; 834 uint32_t clock_change:1; 835 uint32_t stereo_format_change:1; 836 uint32_t full_update:1; 837 } bits; 838 839 uint32_t raw; 840 }; 841 842 struct dc_plane_state { 843 struct dc_plane_address address; 844 struct dc_plane_flip_time time; 845 bool triplebuffer_flips; 846 struct scaling_taps scaling_quality; 847 struct rect src_rect; 848 struct rect dst_rect; 849 struct rect clip_rect; 850 851 struct plane_size plane_size; 852 union dc_tiling_info tiling_info; 853 854 struct dc_plane_dcc_param dcc; 855 856 struct dc_gamma *gamma_correction; 857 struct dc_transfer_func *in_transfer_func; 858 struct dc_bias_and_scale *bias_and_scale; 859 struct dc_csc_transform input_csc_color_matrix; 860 struct fixed31_32 coeff_reduction_factor; 861 struct fixed31_32 hdr_mult; 862 struct colorspace_transform gamut_remap_matrix; 863 864 // TODO: No longer used, remove 865 struct dc_hdr_static_metadata hdr_static_ctx; 866 867 enum dc_color_space color_space; 868 869 struct dc_3dlut *lut3d_func; 870 struct dc_transfer_func *in_shaper_func; 871 struct dc_transfer_func *blend_tf; 872 873 #if defined(CONFIG_DRM_AMD_DC_DCN) 874 struct dc_transfer_func *gamcor_tf; 875 #endif 876 enum surface_pixel_format format; 877 enum dc_rotation_angle rotation; 878 enum plane_stereo_format stereo_format; 879 880 bool is_tiling_rotated; 881 bool per_pixel_alpha; 882 bool global_alpha; 883 int global_alpha_value; 884 bool visible; 885 bool flip_immediate; 886 bool horizontal_mirror; 887 int layer_index; 888 889 union surface_update_flags update_flags; 890 bool flip_int_enabled; 891 /* private to DC core */ 892 struct dc_plane_status status; 893 struct dc_context *ctx; 894 895 /* HACK: Workaround for forcing full reprogramming under some conditions */ 896 bool force_full_update; 897 898 /* private to dc_surface.c */ 899 enum dc_irq_source irq_source; 900 struct kref refcount; 901 }; 902 903 struct dc_plane_info { 904 struct plane_size plane_size; 905 union dc_tiling_info tiling_info; 906 struct dc_plane_dcc_param dcc; 907 enum surface_pixel_format format; 908 enum dc_rotation_angle rotation; 909 enum plane_stereo_format stereo_format; 910 enum dc_color_space color_space; 911 bool horizontal_mirror; 912 bool visible; 913 bool per_pixel_alpha; 914 bool global_alpha; 915 int global_alpha_value; 916 bool input_csc_enabled; 917 int layer_index; 918 }; 919 920 struct dc_scaling_info { 921 struct rect src_rect; 922 struct rect dst_rect; 923 struct rect clip_rect; 924 struct scaling_taps scaling_quality; 925 }; 926 927 struct dc_surface_update { 928 struct dc_plane_state *surface; 929 930 /* isr safe update parameters. null means no updates */ 931 const struct dc_flip_addrs *flip_addr; 932 const struct dc_plane_info *plane_info; 933 const struct dc_scaling_info *scaling_info; 934 struct fixed31_32 hdr_mult; 935 /* following updates require alloc/sleep/spin that is not isr safe, 936 * null means no updates 937 */ 938 const struct dc_gamma *gamma; 939 const struct dc_transfer_func *in_transfer_func; 940 941 const struct dc_csc_transform *input_csc_color_matrix; 942 const struct fixed31_32 *coeff_reduction_factor; 943 const struct dc_transfer_func *func_shaper; 944 const struct dc_3dlut *lut3d_func; 945 const struct dc_transfer_func *blend_tf; 946 const struct colorspace_transform *gamut_remap_matrix; 947 }; 948 949 /* 950 * Create a new surface with default parameters; 951 */ 952 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 953 const struct dc_plane_status *dc_plane_get_status( 954 const struct dc_plane_state *plane_state); 955 956 void dc_plane_state_retain(struct dc_plane_state *plane_state); 957 void dc_plane_state_release(struct dc_plane_state *plane_state); 958 959 void dc_gamma_retain(struct dc_gamma *dc_gamma); 960 void dc_gamma_release(struct dc_gamma **dc_gamma); 961 struct dc_gamma *dc_create_gamma(void); 962 963 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 964 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 965 struct dc_transfer_func *dc_create_transfer_func(void); 966 967 struct dc_3dlut *dc_create_3dlut_func(void); 968 void dc_3dlut_func_release(struct dc_3dlut *lut); 969 void dc_3dlut_func_retain(struct dc_3dlut *lut); 970 /* 971 * This structure holds a surface address. There could be multiple addresses 972 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 973 * as frame durations and DCC format can also be set. 974 */ 975 struct dc_flip_addrs { 976 struct dc_plane_address address; 977 unsigned int flip_timestamp_in_us; 978 bool flip_immediate; 979 /* TODO: add flip duration for FreeSync */ 980 bool triplebuffer_flips; 981 }; 982 983 void dc_post_update_surfaces_to_stream( 984 struct dc *dc); 985 986 #include "dc_stream.h" 987 988 /* 989 * Structure to store surface/stream associations for validation 990 */ 991 struct dc_validation_set { 992 struct dc_stream_state *stream; 993 struct dc_plane_state *plane_states[MAX_SURFACES]; 994 uint8_t plane_count; 995 }; 996 997 bool dc_validate_seamless_boot_timing(const struct dc *dc, 998 const struct dc_sink *sink, 999 struct dc_crtc_timing *crtc_timing); 1000 1001 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1002 1003 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1004 1005 bool dc_set_generic_gpio_for_stereo(bool enable, 1006 struct gpio_service *gpio_service); 1007 1008 /* 1009 * fast_validate: we return after determining if we can support the new state, 1010 * but before we populate the programming info 1011 */ 1012 enum dc_status dc_validate_global_state( 1013 struct dc *dc, 1014 struct dc_state *new_ctx, 1015 bool fast_validate); 1016 1017 1018 void dc_resource_state_construct( 1019 const struct dc *dc, 1020 struct dc_state *dst_ctx); 1021 1022 #if defined(CONFIG_DRM_AMD_DC_DCN) 1023 bool dc_acquire_release_mpc_3dlut( 1024 struct dc *dc, bool acquire, 1025 struct dc_stream_state *stream, 1026 struct dc_3dlut **lut, 1027 struct dc_transfer_func **shaper); 1028 #endif 1029 1030 void dc_resource_state_copy_construct( 1031 const struct dc_state *src_ctx, 1032 struct dc_state *dst_ctx); 1033 1034 void dc_resource_state_copy_construct_current( 1035 const struct dc *dc, 1036 struct dc_state *dst_ctx); 1037 1038 void dc_resource_state_destruct(struct dc_state *context); 1039 1040 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1041 1042 /* 1043 * TODO update to make it about validation sets 1044 * Set up streams and links associated to drive sinks 1045 * The streams parameter is an absolute set of all active streams. 1046 * 1047 * After this call: 1048 * Phy, Encoder, Timing Generator are programmed and enabled. 1049 * New streams are enabled with blank stream; no memory read. 1050 */ 1051 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1052 1053 void dc_power_down_on_boot(struct dc *dc); 1054 1055 struct dc_state *dc_create_state(struct dc *dc); 1056 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1057 void dc_retain_state(struct dc_state *context); 1058 void dc_release_state(struct dc_state *context); 1059 1060 /******************************************************************************* 1061 * Link Interfaces 1062 ******************************************************************************/ 1063 1064 struct dpcd_caps { 1065 union dpcd_rev dpcd_rev; 1066 union max_lane_count max_ln_count; 1067 union max_down_spread max_down_spread; 1068 union dprx_feature dprx_feature; 1069 1070 /* valid only for eDP v1.4 or higher*/ 1071 uint8_t edp_supported_link_rates_count; 1072 enum dc_link_rate edp_supported_link_rates[8]; 1073 1074 /* dongle type (DP converter, CV smart dongle) */ 1075 enum display_dongle_type dongle_type; 1076 /* branch device or sink device */ 1077 bool is_branch_dev; 1078 /* Dongle's downstream count. */ 1079 union sink_count sink_count; 1080 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1081 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1082 struct dc_dongle_caps dongle_caps; 1083 1084 uint32_t sink_dev_id; 1085 int8_t sink_dev_id_str[6]; 1086 int8_t sink_hw_revision; 1087 int8_t sink_fw_revision[2]; 1088 1089 uint32_t branch_dev_id; 1090 int8_t branch_dev_name[6]; 1091 int8_t branch_hw_revision; 1092 int8_t branch_fw_revision[2]; 1093 1094 bool allow_invalid_MSA_timing_param; 1095 bool panel_mode_edp; 1096 bool dpcd_display_control_capable; 1097 bool ext_receiver_cap_field_present; 1098 bool dynamic_backlight_capable_edp; 1099 union dpcd_fec_capability fec_cap; 1100 struct dpcd_dsc_capabilities dsc_caps; 1101 struct dc_lttpr_caps lttpr_caps; 1102 struct psr_caps psr_caps; 1103 1104 }; 1105 1106 union dpcd_sink_ext_caps { 1107 struct { 1108 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1109 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1110 */ 1111 uint8_t sdr_aux_backlight_control : 1; 1112 uint8_t hdr_aux_backlight_control : 1; 1113 uint8_t reserved_1 : 2; 1114 uint8_t oled : 1; 1115 uint8_t reserved : 3; 1116 } bits; 1117 uint8_t raw; 1118 }; 1119 1120 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1121 union hdcp_rx_caps { 1122 struct { 1123 uint8_t version; 1124 uint8_t reserved; 1125 struct { 1126 uint8_t repeater : 1; 1127 uint8_t hdcp_capable : 1; 1128 uint8_t reserved : 6; 1129 } byte0; 1130 } fields; 1131 uint8_t raw[3]; 1132 }; 1133 1134 union hdcp_bcaps { 1135 struct { 1136 uint8_t HDCP_CAPABLE:1; 1137 uint8_t REPEATER:1; 1138 uint8_t RESERVED:6; 1139 } bits; 1140 uint8_t raw; 1141 }; 1142 1143 struct hdcp_caps { 1144 union hdcp_rx_caps rx_caps; 1145 union hdcp_bcaps bcaps; 1146 }; 1147 #endif 1148 1149 #include "dc_link.h" 1150 1151 #if defined(CONFIG_DRM_AMD_DC_DCN) 1152 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1153 1154 #endif 1155 /******************************************************************************* 1156 * Sink Interfaces - A sink corresponds to a display output device 1157 ******************************************************************************/ 1158 1159 struct dc_container_id { 1160 // 128bit GUID in binary form 1161 unsigned char guid[16]; 1162 // 8 byte port ID -> ELD.PortID 1163 unsigned int portId[2]; 1164 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1165 unsigned short manufacturerName; 1166 // 2 byte product code -> ELD.ProductCode 1167 unsigned short productCode; 1168 }; 1169 1170 1171 struct dc_sink_dsc_caps { 1172 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1173 // 'false' if they are sink's DSC caps 1174 bool is_virtual_dpcd_dsc; 1175 struct dsc_dec_dpcd_caps dsc_dec_caps; 1176 }; 1177 1178 struct dc_sink_fec_caps { 1179 bool is_rx_fec_supported; 1180 bool is_topology_fec_supported; 1181 }; 1182 1183 /* 1184 * The sink structure contains EDID and other display device properties 1185 */ 1186 struct dc_sink { 1187 enum signal_type sink_signal; 1188 struct dc_edid dc_edid; /* raw edid */ 1189 struct dc_edid_caps edid_caps; /* parse display caps */ 1190 struct dc_container_id *dc_container_id; 1191 uint32_t dongle_max_pix_clk; 1192 void *priv; 1193 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1194 bool converter_disable_audio; 1195 1196 struct dc_sink_dsc_caps dsc_caps; 1197 struct dc_sink_fec_caps fec_caps; 1198 1199 bool is_vsc_sdp_colorimetry_supported; 1200 1201 /* private to DC core */ 1202 struct dc_link *link; 1203 struct dc_context *ctx; 1204 1205 uint32_t sink_id; 1206 1207 /* private to dc_sink.c */ 1208 // refcount must be the last member in dc_sink, since we want the 1209 // sink structure to be logically cloneable up to (but not including) 1210 // refcount 1211 struct kref refcount; 1212 }; 1213 1214 void dc_sink_retain(struct dc_sink *sink); 1215 void dc_sink_release(struct dc_sink *sink); 1216 1217 struct dc_sink_init_data { 1218 enum signal_type sink_signal; 1219 struct dc_link *link; 1220 uint32_t dongle_max_pix_clk; 1221 bool converter_disable_audio; 1222 }; 1223 1224 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1225 1226 /* Newer interfaces */ 1227 struct dc_cursor { 1228 struct dc_plane_address address; 1229 struct dc_cursor_attributes attributes; 1230 }; 1231 1232 1233 /******************************************************************************* 1234 * Interrupt interfaces 1235 ******************************************************************************/ 1236 enum dc_irq_source dc_interrupt_to_irq_source( 1237 struct dc *dc, 1238 uint32_t src_id, 1239 uint32_t ext_id); 1240 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1241 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1242 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1243 struct dc *dc, uint32_t link_index); 1244 1245 /******************************************************************************* 1246 * Power Interfaces 1247 ******************************************************************************/ 1248 1249 void dc_set_power_state( 1250 struct dc *dc, 1251 enum dc_acpi_cm_power_state power_state); 1252 void dc_resume(struct dc *dc); 1253 1254 void dc_power_down_on_boot(struct dc *dc); 1255 1256 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1257 /* 1258 * HDCP Interfaces 1259 */ 1260 enum hdcp_message_status dc_process_hdcp_msg( 1261 enum signal_type signal, 1262 struct dc_link *link, 1263 struct hdcp_protection_message *message_info); 1264 #endif 1265 bool dc_is_dmcu_initialized(struct dc *dc); 1266 1267 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1268 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1269 #if defined(CONFIG_DRM_AMD_DC_DCN) 1270 1271 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1272 struct dc_cursor_attributes *cursor_attr); 1273 1274 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1275 1276 /* 1277 * blank all streams, and set min and max memory clock to 1278 * lowest and highest DPM level, respectively 1279 */ 1280 void dc_unlock_memory_clock_frequency(struct dc *dc); 1281 1282 /* 1283 * set min memory clock to the min required for current mode, 1284 * max to maxDPM, and unblank streams 1285 */ 1286 void dc_lock_memory_clock_frequency(struct dc *dc); 1287 1288 /* cleanup on driver unload */ 1289 void dc_hardware_release(struct dc *dc); 1290 1291 #endif 1292 1293 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1294 1295 /******************************************************************************* 1296 * DSC Interfaces 1297 ******************************************************************************/ 1298 #include "dc_dsc.h" 1299 #endif /* DC_INTERFACE_H_ */ 1300