1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "hdcp_msg_types.h" 33 #include "gpio_types.h" 34 #include "link_service_types.h" 35 #include "grph_object_ctrl_defs.h" 36 #include <inc/hw/opp.h> 37 38 #include "inc/hw_sequencer.h" 39 #include "inc/compressor.h" 40 #include "inc/hw/dmcu.h" 41 #include "dml/display_mode_lib.h" 42 43 struct abm_save_restore; 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.247" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MIN_VIEWPORT_SIZE 12 56 #define MAX_NUM_EDP 2 57 58 /* Display Core Interfaces */ 59 struct dc_versions { 60 const char *dc_ver; 61 struct dmcu_version dmcu_version; 62 }; 63 64 enum dp_protocol_version { 65 DP_VERSION_1_4 = 0, 66 DP_VERSION_2_1, 67 DP_VERSION_UNKNOWN, 68 }; 69 70 enum dc_plane_type { 71 DC_PLANE_TYPE_INVALID, 72 DC_PLANE_TYPE_DCE_RGB, 73 DC_PLANE_TYPE_DCE_UNDERLAY, 74 DC_PLANE_TYPE_DCN_UNIVERSAL, 75 }; 76 77 // Sizes defined as multiples of 64KB 78 enum det_size { 79 DET_SIZE_DEFAULT = 0, 80 DET_SIZE_192KB = 3, 81 DET_SIZE_256KB = 4, 82 DET_SIZE_320KB = 5, 83 DET_SIZE_384KB = 6 84 }; 85 86 87 struct dc_plane_cap { 88 enum dc_plane_type type; 89 uint32_t per_pixel_alpha : 1; 90 struct { 91 uint32_t argb8888 : 1; 92 uint32_t nv12 : 1; 93 uint32_t fp16 : 1; 94 uint32_t p010 : 1; 95 uint32_t ayuv : 1; 96 } pixel_format_support; 97 // max upscaling factor x1000 98 // upscaling factors are always >= 1 99 // for example, 1080p -> 8K is 4.0, or 4000 raw value 100 struct { 101 uint32_t argb8888; 102 uint32_t nv12; 103 uint32_t fp16; 104 } max_upscale_factor; 105 // max downscale factor x1000 106 // downscale factors are always <= 1 107 // for example, 8K -> 1080p is 0.25, or 250 raw value 108 struct { 109 uint32_t argb8888; 110 uint32_t nv12; 111 uint32_t fp16; 112 } max_downscale_factor; 113 // minimal width/height 114 uint32_t min_width; 115 uint32_t min_height; 116 }; 117 118 /** 119 * DOC: color-management-caps 120 * 121 * **Color management caps (DPP and MPC)** 122 * 123 * Modules/color calculates various color operations which are translated to 124 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 125 * DCN1, every new generation comes with fairly major differences in color 126 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 127 * decide mapping to HW block based on logical capabilities. 128 */ 129 130 /** 131 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 132 * @srgb: RGB color space transfer func 133 * @bt2020: BT.2020 transfer func 134 * @gamma2_2: standard gamma 135 * @pq: perceptual quantizer transfer function 136 * @hlg: hybrid log–gamma transfer function 137 */ 138 struct rom_curve_caps { 139 uint16_t srgb : 1; 140 uint16_t bt2020 : 1; 141 uint16_t gamma2_2 : 1; 142 uint16_t pq : 1; 143 uint16_t hlg : 1; 144 }; 145 146 /** 147 * struct dpp_color_caps - color pipeline capabilities for display pipe and 148 * plane blocks 149 * 150 * @dcn_arch: all DCE generations treated the same 151 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 152 * just plain 256-entry lookup 153 * @icsc: input color space conversion 154 * @dgam_ram: programmable degamma LUT 155 * @post_csc: post color space conversion, before gamut remap 156 * @gamma_corr: degamma correction 157 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 158 * with MPC by setting mpc:shared_3d_lut flag 159 * @ogam_ram: programmable out/blend gamma LUT 160 * @ocsc: output color space conversion 161 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 162 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 163 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 164 * 165 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 166 */ 167 struct dpp_color_caps { 168 uint16_t dcn_arch : 1; 169 uint16_t input_lut_shared : 1; 170 uint16_t icsc : 1; 171 uint16_t dgam_ram : 1; 172 uint16_t post_csc : 1; 173 uint16_t gamma_corr : 1; 174 uint16_t hw_3d_lut : 1; 175 uint16_t ogam_ram : 1; 176 uint16_t ocsc : 1; 177 uint16_t dgam_rom_for_yuv : 1; 178 struct rom_curve_caps dgam_rom_caps; 179 struct rom_curve_caps ogam_rom_caps; 180 }; 181 182 /** 183 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 184 * plane combined blocks 185 * 186 * @gamut_remap: color transformation matrix 187 * @ogam_ram: programmable out gamma LUT 188 * @ocsc: output color space conversion matrix 189 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 190 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 191 * instance 192 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 193 */ 194 struct mpc_color_caps { 195 uint16_t gamut_remap : 1; 196 uint16_t ogam_ram : 1; 197 uint16_t ocsc : 1; 198 uint16_t num_3dluts : 3; 199 uint16_t shared_3d_lut:1; 200 struct rom_curve_caps ogam_rom_caps; 201 }; 202 203 /** 204 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 205 * @dpp: color pipes caps for DPP 206 * @mpc: color pipes caps for MPC 207 */ 208 struct dc_color_caps { 209 struct dpp_color_caps dpp; 210 struct mpc_color_caps mpc; 211 }; 212 213 struct dc_dmub_caps { 214 bool psr; 215 bool mclk_sw; 216 bool subvp_psr; 217 bool gecc_enable; 218 }; 219 220 struct dc_caps { 221 uint32_t max_streams; 222 uint32_t max_links; 223 uint32_t max_audios; 224 uint32_t max_slave_planes; 225 uint32_t max_slave_yuv_planes; 226 uint32_t max_slave_rgb_planes; 227 uint32_t max_planes; 228 uint32_t max_downscale_ratio; 229 uint32_t i2c_speed_in_khz; 230 uint32_t i2c_speed_in_khz_hdcp; 231 uint32_t dmdata_alloc_size; 232 unsigned int max_cursor_size; 233 unsigned int max_video_width; 234 unsigned int min_horizontal_blanking_period; 235 int linear_pitch_alignment; 236 bool dcc_const_color; 237 bool dynamic_audio; 238 bool is_apu; 239 bool dual_link_dvi; 240 bool post_blend_color_processing; 241 bool force_dp_tps4_for_cp2520; 242 bool disable_dp_clk_share; 243 bool psp_setup_panel_mode; 244 bool extended_aux_timeout_support; 245 bool dmcub_support; 246 bool zstate_support; 247 uint32_t num_of_internal_disp; 248 enum dp_protocol_version max_dp_protocol_version; 249 unsigned int mall_size_per_mem_channel; 250 unsigned int mall_size_total; 251 unsigned int cursor_cache_size; 252 struct dc_plane_cap planes[MAX_PLANES]; 253 struct dc_color_caps color; 254 struct dc_dmub_caps dmub_caps; 255 bool dp_hpo; 256 bool dp_hdmi21_pcon_support; 257 bool edp_dsc_support; 258 bool vbios_lttpr_aware; 259 bool vbios_lttpr_enable; 260 uint32_t max_otg_num; 261 uint32_t max_cab_allocation_bytes; 262 uint32_t cache_line_size; 263 uint32_t cache_num_ways; 264 uint16_t subvp_fw_processing_delay_us; 265 uint8_t subvp_drr_max_vblank_margin_us; 266 uint16_t subvp_prefetch_end_to_mall_start_us; 267 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 268 uint16_t subvp_pstate_allow_width_us; 269 uint16_t subvp_vertical_int_margin_us; 270 bool seamless_odm; 271 uint32_t max_v_total; 272 uint8_t subvp_drr_vblank_start_margin_us; 273 }; 274 275 struct dc_bug_wa { 276 bool no_connect_phy_config; 277 bool dedcn20_305_wa; 278 bool skip_clock_update; 279 bool lt_early_cr_pattern; 280 struct { 281 uint8_t uclk : 1; 282 uint8_t fclk : 1; 283 uint8_t dcfclk : 1; 284 uint8_t dcfclk_ds: 1; 285 } clock_update_disable_mask; 286 }; 287 struct dc_dcc_surface_param { 288 struct dc_size surface_size; 289 enum surface_pixel_format format; 290 enum swizzle_mode_values swizzle_mode; 291 enum dc_scan_direction scan; 292 }; 293 294 struct dc_dcc_setting { 295 unsigned int max_compressed_blk_size; 296 unsigned int max_uncompressed_blk_size; 297 bool independent_64b_blks; 298 //These bitfields to be used starting with DCN 299 struct { 300 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 301 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 302 uint32_t dcc_256_128_128 : 1; //available starting with DCN 303 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 304 } dcc_controls; 305 }; 306 307 struct dc_surface_dcc_cap { 308 union { 309 struct { 310 struct dc_dcc_setting rgb; 311 } grph; 312 313 struct { 314 struct dc_dcc_setting luma; 315 struct dc_dcc_setting chroma; 316 } video; 317 }; 318 319 bool capable; 320 bool const_color_support; 321 }; 322 323 struct dc_static_screen_params { 324 struct { 325 bool force_trigger; 326 bool cursor_update; 327 bool surface_update; 328 bool overlay_update; 329 } triggers; 330 unsigned int num_frames; 331 }; 332 333 334 /* Surface update type is used by dc_update_surfaces_and_stream 335 * The update type is determined at the very beginning of the function based 336 * on parameters passed in and decides how much programming (or updating) is 337 * going to be done during the call. 338 * 339 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 340 * logical calculations or hardware register programming. This update MUST be 341 * ISR safe on windows. Currently fast update will only be used to flip surface 342 * address. 343 * 344 * UPDATE_TYPE_MED is used for slower updates which require significant hw 345 * re-programming however do not affect bandwidth consumption or clock 346 * requirements. At present, this is the level at which front end updates 347 * that do not require us to run bw_calcs happen. These are in/out transfer func 348 * updates, viewport offset changes, recout size changes and pixel depth changes. 349 * This update can be done at ISR, but we want to minimize how often this happens. 350 * 351 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 352 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 353 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 354 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 355 * a full update. This cannot be done at ISR level and should be a rare event. 356 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 357 * underscan we don't expect to see this call at all. 358 */ 359 360 enum surface_update_type { 361 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 362 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 363 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 364 }; 365 366 /* Forward declaration*/ 367 struct dc; 368 struct dc_plane_state; 369 struct dc_state; 370 371 372 struct dc_cap_funcs { 373 bool (*get_dcc_compression_cap)(const struct dc *dc, 374 const struct dc_dcc_surface_param *input, 375 struct dc_surface_dcc_cap *output); 376 }; 377 378 struct link_training_settings; 379 380 union allow_lttpr_non_transparent_mode { 381 struct { 382 bool DP1_4A : 1; 383 bool DP2_0 : 1; 384 } bits; 385 unsigned char raw; 386 }; 387 388 /* Structure to hold configuration flags set by dm at dc creation. */ 389 struct dc_config { 390 bool gpu_vm_support; 391 bool disable_disp_pll_sharing; 392 bool fbc_support; 393 bool disable_fractional_pwm; 394 bool allow_seamless_boot_optimization; 395 bool seamless_boot_edp_requested; 396 bool edp_not_connected; 397 bool edp_no_power_sequencing; 398 bool force_enum_edp; 399 bool forced_clocks; 400 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 401 bool multi_mon_pp_mclk_switch; 402 bool disable_dmcu; 403 bool enable_4to1MPC; 404 bool enable_windowed_mpo_odm; 405 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 406 uint32_t allow_edp_hotplug_detection; 407 bool clamp_min_dcfclk; 408 uint64_t vblank_alignment_dto_params; 409 uint8_t vblank_alignment_max_frame_time_diff; 410 bool is_asymmetric_memory; 411 bool is_single_rank_dimm; 412 bool is_vmin_only_asic; 413 bool use_pipe_ctx_sync_logic; 414 bool ignore_dpref_ss; 415 bool enable_mipi_converter_optimization; 416 bool use_default_clock_table; 417 bool force_bios_enable_lttpr; 418 uint8_t force_bios_fixed_vs; 419 int sdpif_request_limit_words_per_umc; 420 bool use_old_fixed_vs_sequence; 421 bool dc_mode_clk_limit_support; 422 }; 423 424 enum visual_confirm { 425 VISUAL_CONFIRM_DISABLE = 0, 426 VISUAL_CONFIRM_SURFACE = 1, 427 VISUAL_CONFIRM_HDR = 2, 428 VISUAL_CONFIRM_MPCTREE = 4, 429 VISUAL_CONFIRM_PSR = 5, 430 VISUAL_CONFIRM_SWAPCHAIN = 6, 431 VISUAL_CONFIRM_FAMS = 7, 432 VISUAL_CONFIRM_SWIZZLE = 9, 433 VISUAL_CONFIRM_REPLAY = 12, 434 VISUAL_CONFIRM_SUBVP = 14, 435 VISUAL_CONFIRM_MCLK_SWITCH = 16, 436 }; 437 438 enum dc_psr_power_opts { 439 psr_power_opt_invalid = 0x0, 440 psr_power_opt_smu_opt_static_screen = 0x1, 441 psr_power_opt_z10_static_screen = 0x10, 442 psr_power_opt_ds_disable_allow = 0x100, 443 }; 444 445 enum dml_hostvm_override_opts { 446 DML_HOSTVM_NO_OVERRIDE = 0x0, 447 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 448 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 449 }; 450 451 enum dcc_option { 452 DCC_ENABLE = 0, 453 DCC_DISABLE = 1, 454 DCC_HALF_REQ_DISALBE = 2, 455 }; 456 457 /** 458 * enum pipe_split_policy - Pipe split strategy supported by DCN 459 * 460 * This enum is used to define the pipe split policy supported by DCN. By 461 * default, DC favors MPC_SPLIT_DYNAMIC. 462 */ 463 enum pipe_split_policy { 464 /** 465 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 466 * pipe in order to bring the best trade-off between performance and 467 * power consumption. This is the recommended option. 468 */ 469 MPC_SPLIT_DYNAMIC = 0, 470 471 /** 472 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 473 * try any sort of split optimization. 474 */ 475 MPC_SPLIT_AVOID = 1, 476 477 /** 478 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 479 * optimize the pipe utilization when using a single display; if the 480 * user connects to a second display, DC will avoid pipe split. 481 */ 482 MPC_SPLIT_AVOID_MULT_DISP = 2, 483 }; 484 485 enum wm_report_mode { 486 WM_REPORT_DEFAULT = 0, 487 WM_REPORT_OVERRIDE = 1, 488 }; 489 enum dtm_pstate{ 490 dtm_level_p0 = 0,/*highest voltage*/ 491 dtm_level_p1, 492 dtm_level_p2, 493 dtm_level_p3, 494 dtm_level_p4,/*when active_display_count = 0*/ 495 }; 496 497 enum dcn_pwr_state { 498 DCN_PWR_STATE_UNKNOWN = -1, 499 DCN_PWR_STATE_MISSION_MODE = 0, 500 DCN_PWR_STATE_LOW_POWER = 3, 501 }; 502 503 enum dcn_zstate_support_state { 504 DCN_ZSTATE_SUPPORT_UNKNOWN, 505 DCN_ZSTATE_SUPPORT_ALLOW, 506 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 507 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 508 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 509 DCN_ZSTATE_SUPPORT_DISALLOW, 510 }; 511 512 /* 513 * struct dc_clocks - DC pipe clocks 514 * 515 * For any clocks that may differ per pipe only the max is stored in this 516 * structure 517 */ 518 struct dc_clocks { 519 int dispclk_khz; 520 int actual_dispclk_khz; 521 int dppclk_khz; 522 int actual_dppclk_khz; 523 int disp_dpp_voltage_level_khz; 524 int dcfclk_khz; 525 int socclk_khz; 526 int dcfclk_deep_sleep_khz; 527 int fclk_khz; 528 int phyclk_khz; 529 int dramclk_khz; 530 bool p_state_change_support; 531 enum dcn_zstate_support_state zstate_support; 532 bool dtbclk_en; 533 int ref_dtbclk_khz; 534 bool fclk_p_state_change_support; 535 enum dcn_pwr_state pwr_state; 536 /* 537 * Elements below are not compared for the purposes of 538 * optimization required 539 */ 540 bool prev_p_state_change_support; 541 bool fclk_prev_p_state_change_support; 542 int num_ways; 543 544 /* 545 * @fw_based_mclk_switching 546 * 547 * DC has a mechanism that leverage the variable refresh rate to switch 548 * memory clock in cases that we have a large latency to achieve the 549 * memory clock change and a short vblank window. DC has some 550 * requirements to enable this feature, and this field describes if the 551 * system support or not such a feature. 552 */ 553 bool fw_based_mclk_switching; 554 bool fw_based_mclk_switching_shut_down; 555 int prev_num_ways; 556 enum dtm_pstate dtm_level; 557 int max_supported_dppclk_khz; 558 int max_supported_dispclk_khz; 559 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 560 int bw_dispclk_khz; 561 }; 562 563 struct dc_bw_validation_profile { 564 bool enable; 565 566 unsigned long long total_ticks; 567 unsigned long long voltage_level_ticks; 568 unsigned long long watermark_ticks; 569 unsigned long long rq_dlg_ticks; 570 571 unsigned long long total_count; 572 unsigned long long skip_fast_count; 573 unsigned long long skip_pass_count; 574 unsigned long long skip_fail_count; 575 }; 576 577 #define BW_VAL_TRACE_SETUP() \ 578 unsigned long long end_tick = 0; \ 579 unsigned long long voltage_level_tick = 0; \ 580 unsigned long long watermark_tick = 0; \ 581 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 582 dm_get_timestamp(dc->ctx) : 0 583 584 #define BW_VAL_TRACE_COUNT() \ 585 if (dc->debug.bw_val_profile.enable) \ 586 dc->debug.bw_val_profile.total_count++ 587 588 #define BW_VAL_TRACE_SKIP(status) \ 589 if (dc->debug.bw_val_profile.enable) { \ 590 if (!voltage_level_tick) \ 591 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 592 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 593 } 594 595 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 596 if (dc->debug.bw_val_profile.enable) \ 597 voltage_level_tick = dm_get_timestamp(dc->ctx) 598 599 #define BW_VAL_TRACE_END_WATERMARKS() \ 600 if (dc->debug.bw_val_profile.enable) \ 601 watermark_tick = dm_get_timestamp(dc->ctx) 602 603 #define BW_VAL_TRACE_FINISH() \ 604 if (dc->debug.bw_val_profile.enable) { \ 605 end_tick = dm_get_timestamp(dc->ctx); \ 606 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 607 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 608 if (watermark_tick) { \ 609 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 610 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 611 } \ 612 } 613 614 union mem_low_power_enable_options { 615 struct { 616 bool vga: 1; 617 bool i2c: 1; 618 bool dmcu: 1; 619 bool dscl: 1; 620 bool cm: 1; 621 bool mpc: 1; 622 bool optc: 1; 623 bool vpg: 1; 624 bool afmt: 1; 625 } bits; 626 uint32_t u32All; 627 }; 628 629 union root_clock_optimization_options { 630 struct { 631 bool dpp: 1; 632 bool dsc: 1; 633 bool hdmistream: 1; 634 bool hdmichar: 1; 635 bool dpstream: 1; 636 bool symclk32_se: 1; 637 bool symclk32_le: 1; 638 bool symclk_fe: 1; 639 bool physymclk: 1; 640 bool dpiasymclk: 1; 641 uint32_t reserved: 22; 642 } bits; 643 uint32_t u32All; 644 }; 645 646 union dpia_debug_options { 647 struct { 648 uint32_t disable_dpia:1; /* bit 0 */ 649 uint32_t force_non_lttpr:1; /* bit 1 */ 650 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 651 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 652 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 653 uint32_t reserved:27; 654 } bits; 655 uint32_t raw; 656 }; 657 658 /* AUX wake work around options 659 * 0: enable/disable work around 660 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 661 * 15-2: reserved 662 * 31-16: timeout in ms 663 */ 664 union aux_wake_wa_options { 665 struct { 666 uint32_t enable_wa : 1; 667 uint32_t use_default_timeout : 1; 668 uint32_t rsvd: 14; 669 uint32_t timeout_ms : 16; 670 } bits; 671 uint32_t raw; 672 }; 673 674 struct dc_debug_data { 675 uint32_t ltFailCount; 676 uint32_t i2cErrorCount; 677 uint32_t auxErrorCount; 678 }; 679 680 struct dc_phy_addr_space_config { 681 struct { 682 uint64_t start_addr; 683 uint64_t end_addr; 684 uint64_t fb_top; 685 uint64_t fb_offset; 686 uint64_t fb_base; 687 uint64_t agp_top; 688 uint64_t agp_bot; 689 uint64_t agp_base; 690 } system_aperture; 691 692 struct { 693 uint64_t page_table_start_addr; 694 uint64_t page_table_end_addr; 695 uint64_t page_table_base_addr; 696 bool base_addr_is_mc_addr; 697 } gart_config; 698 699 bool valid; 700 bool is_hvm_enabled; 701 uint64_t page_table_default_page_addr; 702 }; 703 704 struct dc_virtual_addr_space_config { 705 uint64_t page_table_base_addr; 706 uint64_t page_table_start_addr; 707 uint64_t page_table_end_addr; 708 uint32_t page_table_block_size_in_bytes; 709 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 710 }; 711 712 struct dc_bounding_box_overrides { 713 int sr_exit_time_ns; 714 int sr_enter_plus_exit_time_ns; 715 int sr_exit_z8_time_ns; 716 int sr_enter_plus_exit_z8_time_ns; 717 int urgent_latency_ns; 718 int percent_of_ideal_drambw; 719 int dram_clock_change_latency_ns; 720 int dummy_clock_change_latency_ns; 721 int fclk_clock_change_latency_ns; 722 /* This forces a hard min on the DCFCLK we use 723 * for DML. Unlike the debug option for forcing 724 * DCFCLK, this override affects watermark calculations 725 */ 726 int min_dcfclk_mhz; 727 }; 728 729 struct dc_state; 730 struct resource_pool; 731 struct dce_hwseq; 732 struct link_service; 733 734 /* 735 * struct dc_debug_options - DC debug struct 736 * 737 * This struct provides a simple mechanism for developers to change some 738 * configurations, enable/disable features, and activate extra debug options. 739 * This can be very handy to narrow down whether some specific feature is 740 * causing an issue or not. 741 */ 742 struct dc_debug_options { 743 bool native422_support; 744 bool disable_dsc; 745 enum visual_confirm visual_confirm; 746 int visual_confirm_rect_height; 747 748 bool sanity_checks; 749 bool max_disp_clk; 750 bool surface_trace; 751 bool timing_trace; 752 bool clock_trace; 753 bool validation_trace; 754 bool bandwidth_calcs_trace; 755 int max_downscale_src_width; 756 757 /* stutter efficiency related */ 758 bool disable_stutter; 759 bool use_max_lb; 760 enum dcc_option disable_dcc; 761 762 /* 763 * @pipe_split_policy: Define which pipe split policy is used by the 764 * display core. 765 */ 766 enum pipe_split_policy pipe_split_policy; 767 bool force_single_disp_pipe_split; 768 bool voltage_align_fclk; 769 bool disable_min_fclk; 770 771 bool disable_dfs_bypass; 772 bool disable_dpp_power_gate; 773 bool disable_hubp_power_gate; 774 bool disable_dsc_power_gate; 775 int dsc_min_slice_height_override; 776 int dsc_bpp_increment_div; 777 bool disable_pplib_wm_range; 778 enum wm_report_mode pplib_wm_report_mode; 779 unsigned int min_disp_clk_khz; 780 unsigned int min_dpp_clk_khz; 781 unsigned int min_dram_clk_khz; 782 int sr_exit_time_dpm0_ns; 783 int sr_enter_plus_exit_time_dpm0_ns; 784 int sr_exit_time_ns; 785 int sr_enter_plus_exit_time_ns; 786 int sr_exit_z8_time_ns; 787 int sr_enter_plus_exit_z8_time_ns; 788 int urgent_latency_ns; 789 uint32_t underflow_assert_delay_us; 790 int percent_of_ideal_drambw; 791 int dram_clock_change_latency_ns; 792 bool optimized_watermark; 793 int always_scale; 794 bool disable_pplib_clock_request; 795 bool disable_clock_gate; 796 bool disable_mem_low_power; 797 bool pstate_enabled; 798 bool disable_dmcu; 799 bool force_abm_enable; 800 bool disable_stereo_support; 801 bool vsr_support; 802 bool performance_trace; 803 bool az_endpoint_mute_only; 804 bool always_use_regamma; 805 bool recovery_enabled; 806 bool avoid_vbios_exec_table; 807 bool scl_reset_length10; 808 bool hdmi20_disable; 809 bool skip_detection_link_training; 810 uint32_t edid_read_retry_times; 811 unsigned int force_odm_combine; //bit vector based on otg inst 812 unsigned int seamless_boot_odm_combine; 813 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 814 int minimum_z8_residency_time; 815 bool disable_z9_mpc; 816 unsigned int force_fclk_khz; 817 bool enable_tri_buf; 818 bool dmub_offload_enabled; 819 bool dmcub_emulation; 820 bool disable_idle_power_optimizations; 821 unsigned int mall_size_override; 822 unsigned int mall_additional_timer_percent; 823 bool mall_error_as_fatal; 824 bool dmub_command_table; /* for testing only */ 825 struct dc_bw_validation_profile bw_val_profile; 826 bool disable_fec; 827 bool disable_48mhz_pwrdwn; 828 /* This forces a hard min on the DCFCLK requested to SMU/PP 829 * watermarks are not affected. 830 */ 831 unsigned int force_min_dcfclk_mhz; 832 int dwb_fi_phase; 833 bool disable_timing_sync; 834 bool cm_in_bypass; 835 int force_clock_mode;/*every mode change.*/ 836 837 bool disable_dram_clock_change_vactive_support; 838 bool validate_dml_output; 839 bool enable_dmcub_surface_flip; 840 bool usbc_combo_phy_reset_wa; 841 bool enable_dram_clock_change_one_display_vactive; 842 /* TODO - remove once tested */ 843 bool legacy_dp2_lt; 844 bool set_mst_en_for_sst; 845 bool disable_uhbr; 846 bool force_dp2_lt_fallback_method; 847 bool ignore_cable_id; 848 union mem_low_power_enable_options enable_mem_low_power; 849 union root_clock_optimization_options root_clock_optimization; 850 bool hpo_optimization; 851 bool force_vblank_alignment; 852 853 /* Enable dmub aux for legacy ddc */ 854 bool enable_dmub_aux_for_legacy_ddc; 855 bool disable_fams; 856 bool disable_fams_gaming; 857 /* FEC/PSR1 sequence enable delay in 100us */ 858 uint8_t fec_enable_delay_in100us; 859 bool enable_driver_sequence_debug; 860 enum det_size crb_alloc_policy; 861 int crb_alloc_policy_min_disp_count; 862 bool disable_z10; 863 bool enable_z9_disable_interface; 864 bool psr_skip_crtc_disable; 865 union dpia_debug_options dpia_debug; 866 bool disable_fixed_vs_aux_timeout_wa; 867 uint32_t fixed_vs_aux_delay_config_wa; 868 bool force_disable_subvp; 869 bool force_subvp_mclk_switch; 870 bool allow_sw_cursor_fallback; 871 unsigned int force_subvp_num_ways; 872 unsigned int force_mall_ss_num_ways; 873 bool alloc_extra_way_for_cursor; 874 uint32_t subvp_extra_lines; 875 bool force_usr_allow; 876 /* uses value at boot and disables switch */ 877 bool disable_dtb_ref_clk_switch; 878 bool extended_blank_optimization; 879 union aux_wake_wa_options aux_wake_wa; 880 uint32_t mst_start_top_delay; 881 uint8_t psr_power_use_phy_fsm; 882 enum dml_hostvm_override_opts dml_hostvm_override; 883 bool dml_disallow_alternate_prefetch_modes; 884 bool use_legacy_soc_bb_mechanism; 885 bool exit_idle_opt_for_cursor_updates; 886 bool enable_single_display_2to1_odm_policy; 887 bool enable_double_buffered_dsc_pg_support; 888 bool enable_dp_dig_pixel_rate_div_policy; 889 enum lttpr_mode lttpr_mode_override; 890 unsigned int dsc_delay_factor_wa_x1000; 891 unsigned int min_prefetch_in_strobe_ns; 892 bool disable_unbounded_requesting; 893 bool dig_fifo_off_in_blank; 894 bool temp_mst_deallocation_sequence; 895 bool override_dispclk_programming; 896 bool disable_fpo_optimizations; 897 bool support_eDP1_5; 898 uint32_t fpo_vactive_margin_us; 899 bool disable_fpo_vactive; 900 bool disable_boot_optimizations; 901 bool override_odm_optimization; 902 bool minimize_dispclk_using_odm; 903 bool disable_subvp_high_refresh; 904 bool disable_dp_plus_plus_wa; 905 uint32_t fpo_vactive_min_active_margin_us; 906 uint32_t fpo_vactive_max_blank_us; 907 bool enable_legacy_fast_update; 908 bool disable_dc_mode_overwrite; 909 bool replay_skip_crtc_disabled; 910 }; 911 912 struct gpu_info_soc_bounding_box_v1_0; 913 914 /* Generic structure that can be used to query properties of DC. More fields 915 * can be added as required. 916 */ 917 struct dc_current_properties { 918 unsigned int cursor_size_limit; 919 }; 920 921 struct dc { 922 struct dc_debug_options debug; 923 struct dc_versions versions; 924 struct dc_caps caps; 925 struct dc_cap_funcs cap_funcs; 926 struct dc_config config; 927 struct dc_bounding_box_overrides bb_overrides; 928 struct dc_bug_wa work_arounds; 929 struct dc_context *ctx; 930 struct dc_phy_addr_space_config vm_pa_config; 931 932 uint8_t link_count; 933 struct dc_link *links[MAX_PIPES * 2]; 934 struct link_service *link_srv; 935 936 struct dc_state *current_state; 937 struct resource_pool *res_pool; 938 939 struct clk_mgr *clk_mgr; 940 941 /* Display Engine Clock levels */ 942 struct dm_pp_clock_levels sclk_lvls; 943 944 /* Inputs into BW and WM calculations. */ 945 struct bw_calcs_dceip *bw_dceip; 946 struct bw_calcs_vbios *bw_vbios; 947 struct dcn_soc_bounding_box *dcn_soc; 948 struct dcn_ip_params *dcn_ip; 949 struct display_mode_lib dml; 950 951 /* HW functions */ 952 struct hw_sequencer_funcs hwss; 953 struct dce_hwseq *hwseq; 954 955 /* Require to optimize clocks and bandwidth for added/removed planes */ 956 bool optimized_required; 957 bool wm_optimized_required; 958 bool idle_optimizations_allowed; 959 bool enable_c20_dtm_b0; 960 961 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 962 963 /* FBC compressor */ 964 struct compressor *fbc_compressor; 965 966 struct dc_debug_data debug_data; 967 struct dpcd_vendor_signature vendor_signature; 968 969 const char *build_id; 970 struct vm_helper *vm_helper; 971 972 uint32_t *dcn_reg_offsets; 973 uint32_t *nbio_reg_offsets; 974 975 /* Scratch memory */ 976 struct { 977 struct { 978 /* 979 * For matching clock_limits table in driver with table 980 * from PMFW. 981 */ 982 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 983 } update_bw_bounding_box; 984 } scratch; 985 }; 986 987 enum frame_buffer_mode { 988 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 989 FRAME_BUFFER_MODE_ZFB_ONLY, 990 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 991 } ; 992 993 struct dchub_init_data { 994 int64_t zfb_phys_addr_base; 995 int64_t zfb_mc_base_addr; 996 uint64_t zfb_size_in_byte; 997 enum frame_buffer_mode fb_mode; 998 bool dchub_initialzied; 999 bool dchub_info_valid; 1000 }; 1001 1002 struct dc_init_data { 1003 struct hw_asic_id asic_id; 1004 void *driver; /* ctx */ 1005 struct cgs_device *cgs_device; 1006 struct dc_bounding_box_overrides bb_overrides; 1007 1008 int num_virtual_links; 1009 /* 1010 * If 'vbios_override' not NULL, it will be called instead 1011 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1012 */ 1013 struct dc_bios *vbios_override; 1014 enum dce_environment dce_environment; 1015 1016 struct dmub_offload_funcs *dmub_if; 1017 struct dc_reg_helper_state *dmub_offload; 1018 1019 struct dc_config flags; 1020 uint64_t log_mask; 1021 1022 struct dpcd_vendor_signature vendor_signature; 1023 bool force_smu_not_present; 1024 /* 1025 * IP offset for run time initializaion of register addresses 1026 * 1027 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1028 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1029 * before them. 1030 */ 1031 uint32_t *dcn_reg_offsets; 1032 uint32_t *nbio_reg_offsets; 1033 }; 1034 1035 struct dc_callback_init { 1036 struct cp_psp cp_psp; 1037 }; 1038 1039 struct dc *dc_create(const struct dc_init_data *init_params); 1040 void dc_hardware_init(struct dc *dc); 1041 1042 int dc_get_vmid_use_vector(struct dc *dc); 1043 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1044 /* Returns the number of vmids supported */ 1045 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1046 void dc_init_callbacks(struct dc *dc, 1047 const struct dc_callback_init *init_params); 1048 void dc_deinit_callbacks(struct dc *dc); 1049 void dc_destroy(struct dc **dc); 1050 1051 /* Surface Interfaces */ 1052 1053 enum { 1054 TRANSFER_FUNC_POINTS = 1025 1055 }; 1056 1057 struct dc_hdr_static_metadata { 1058 /* display chromaticities and white point in units of 0.00001 */ 1059 unsigned int chromaticity_green_x; 1060 unsigned int chromaticity_green_y; 1061 unsigned int chromaticity_blue_x; 1062 unsigned int chromaticity_blue_y; 1063 unsigned int chromaticity_red_x; 1064 unsigned int chromaticity_red_y; 1065 unsigned int chromaticity_white_point_x; 1066 unsigned int chromaticity_white_point_y; 1067 1068 uint32_t min_luminance; 1069 uint32_t max_luminance; 1070 uint32_t maximum_content_light_level; 1071 uint32_t maximum_frame_average_light_level; 1072 }; 1073 1074 enum dc_transfer_func_type { 1075 TF_TYPE_PREDEFINED, 1076 TF_TYPE_DISTRIBUTED_POINTS, 1077 TF_TYPE_BYPASS, 1078 TF_TYPE_HWPWL 1079 }; 1080 1081 struct dc_transfer_func_distributed_points { 1082 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1083 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1084 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1085 1086 uint16_t end_exponent; 1087 uint16_t x_point_at_y1_red; 1088 uint16_t x_point_at_y1_green; 1089 uint16_t x_point_at_y1_blue; 1090 }; 1091 1092 enum dc_transfer_func_predefined { 1093 TRANSFER_FUNCTION_SRGB, 1094 TRANSFER_FUNCTION_BT709, 1095 TRANSFER_FUNCTION_PQ, 1096 TRANSFER_FUNCTION_LINEAR, 1097 TRANSFER_FUNCTION_UNITY, 1098 TRANSFER_FUNCTION_HLG, 1099 TRANSFER_FUNCTION_HLG12, 1100 TRANSFER_FUNCTION_GAMMA22, 1101 TRANSFER_FUNCTION_GAMMA24, 1102 TRANSFER_FUNCTION_GAMMA26 1103 }; 1104 1105 1106 struct dc_transfer_func { 1107 struct kref refcount; 1108 enum dc_transfer_func_type type; 1109 enum dc_transfer_func_predefined tf; 1110 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1111 uint32_t sdr_ref_white_level; 1112 union { 1113 struct pwl_params pwl; 1114 struct dc_transfer_func_distributed_points tf_pts; 1115 }; 1116 }; 1117 1118 1119 union dc_3dlut_state { 1120 struct { 1121 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1122 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1123 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1124 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1125 uint32_t mpc_rmu1_mux:4; 1126 uint32_t mpc_rmu2_mux:4; 1127 uint32_t reserved:15; 1128 } bits; 1129 uint32_t raw; 1130 }; 1131 1132 1133 struct dc_3dlut { 1134 struct kref refcount; 1135 struct tetrahedral_params lut_3d; 1136 struct fixed31_32 hdr_multiplier; 1137 union dc_3dlut_state state; 1138 }; 1139 /* 1140 * This structure is filled in by dc_surface_get_status and contains 1141 * the last requested address and the currently active address so the called 1142 * can determine if there are any outstanding flips 1143 */ 1144 struct dc_plane_status { 1145 struct dc_plane_address requested_address; 1146 struct dc_plane_address current_address; 1147 bool is_flip_pending; 1148 bool is_right_eye; 1149 }; 1150 1151 union surface_update_flags { 1152 1153 struct { 1154 uint32_t addr_update:1; 1155 /* Medium updates */ 1156 uint32_t dcc_change:1; 1157 uint32_t color_space_change:1; 1158 uint32_t horizontal_mirror_change:1; 1159 uint32_t per_pixel_alpha_change:1; 1160 uint32_t global_alpha_change:1; 1161 uint32_t hdr_mult:1; 1162 uint32_t rotation_change:1; 1163 uint32_t swizzle_change:1; 1164 uint32_t scaling_change:1; 1165 uint32_t position_change:1; 1166 uint32_t in_transfer_func_change:1; 1167 uint32_t input_csc_change:1; 1168 uint32_t coeff_reduction_change:1; 1169 uint32_t output_tf_change:1; 1170 uint32_t pixel_format_change:1; 1171 uint32_t plane_size_change:1; 1172 uint32_t gamut_remap_change:1; 1173 1174 /* Full updates */ 1175 uint32_t new_plane:1; 1176 uint32_t bpp_change:1; 1177 uint32_t gamma_change:1; 1178 uint32_t bandwidth_change:1; 1179 uint32_t clock_change:1; 1180 uint32_t stereo_format_change:1; 1181 uint32_t lut_3d:1; 1182 uint32_t tmz_changed:1; 1183 uint32_t full_update:1; 1184 } bits; 1185 1186 uint32_t raw; 1187 }; 1188 1189 struct dc_plane_state { 1190 struct dc_plane_address address; 1191 struct dc_plane_flip_time time; 1192 bool triplebuffer_flips; 1193 struct scaling_taps scaling_quality; 1194 struct rect src_rect; 1195 struct rect dst_rect; 1196 struct rect clip_rect; 1197 1198 struct plane_size plane_size; 1199 union dc_tiling_info tiling_info; 1200 1201 struct dc_plane_dcc_param dcc; 1202 1203 struct dc_gamma *gamma_correction; 1204 struct dc_transfer_func *in_transfer_func; 1205 struct dc_bias_and_scale *bias_and_scale; 1206 struct dc_csc_transform input_csc_color_matrix; 1207 struct fixed31_32 coeff_reduction_factor; 1208 struct fixed31_32 hdr_mult; 1209 struct colorspace_transform gamut_remap_matrix; 1210 1211 // TODO: No longer used, remove 1212 struct dc_hdr_static_metadata hdr_static_ctx; 1213 1214 enum dc_color_space color_space; 1215 1216 struct dc_3dlut *lut3d_func; 1217 struct dc_transfer_func *in_shaper_func; 1218 struct dc_transfer_func *blend_tf; 1219 1220 struct dc_transfer_func *gamcor_tf; 1221 enum surface_pixel_format format; 1222 enum dc_rotation_angle rotation; 1223 enum plane_stereo_format stereo_format; 1224 1225 bool is_tiling_rotated; 1226 bool per_pixel_alpha; 1227 bool pre_multiplied_alpha; 1228 bool global_alpha; 1229 int global_alpha_value; 1230 bool visible; 1231 bool flip_immediate; 1232 bool horizontal_mirror; 1233 int layer_index; 1234 1235 union surface_update_flags update_flags; 1236 bool flip_int_enabled; 1237 bool skip_manual_trigger; 1238 1239 /* private to DC core */ 1240 struct dc_plane_status status; 1241 struct dc_context *ctx; 1242 1243 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1244 bool force_full_update; 1245 1246 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1247 1248 /* private to dc_surface.c */ 1249 enum dc_irq_source irq_source; 1250 struct kref refcount; 1251 struct tg_color visual_confirm_color; 1252 1253 bool is_statically_allocated; 1254 }; 1255 1256 struct dc_plane_info { 1257 struct plane_size plane_size; 1258 union dc_tiling_info tiling_info; 1259 struct dc_plane_dcc_param dcc; 1260 enum surface_pixel_format format; 1261 enum dc_rotation_angle rotation; 1262 enum plane_stereo_format stereo_format; 1263 enum dc_color_space color_space; 1264 bool horizontal_mirror; 1265 bool visible; 1266 bool per_pixel_alpha; 1267 bool pre_multiplied_alpha; 1268 bool global_alpha; 1269 int global_alpha_value; 1270 bool input_csc_enabled; 1271 int layer_index; 1272 }; 1273 1274 struct dc_scaling_info { 1275 struct rect src_rect; 1276 struct rect dst_rect; 1277 struct rect clip_rect; 1278 struct scaling_taps scaling_quality; 1279 }; 1280 1281 struct dc_fast_update { 1282 const struct dc_flip_addrs *flip_addr; 1283 const struct dc_gamma *gamma; 1284 const struct colorspace_transform *gamut_remap_matrix; 1285 const struct dc_csc_transform *input_csc_color_matrix; 1286 const struct fixed31_32 *coeff_reduction_factor; 1287 struct dc_transfer_func *out_transfer_func; 1288 struct dc_csc_transform *output_csc_transform; 1289 }; 1290 1291 struct dc_surface_update { 1292 struct dc_plane_state *surface; 1293 1294 /* isr safe update parameters. null means no updates */ 1295 const struct dc_flip_addrs *flip_addr; 1296 const struct dc_plane_info *plane_info; 1297 const struct dc_scaling_info *scaling_info; 1298 struct fixed31_32 hdr_mult; 1299 /* following updates require alloc/sleep/spin that is not isr safe, 1300 * null means no updates 1301 */ 1302 const struct dc_gamma *gamma; 1303 const struct dc_transfer_func *in_transfer_func; 1304 1305 const struct dc_csc_transform *input_csc_color_matrix; 1306 const struct fixed31_32 *coeff_reduction_factor; 1307 const struct dc_transfer_func *func_shaper; 1308 const struct dc_3dlut *lut3d_func; 1309 const struct dc_transfer_func *blend_tf; 1310 const struct colorspace_transform *gamut_remap_matrix; 1311 }; 1312 1313 /* 1314 * Create a new surface with default parameters; 1315 */ 1316 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1317 const struct dc_plane_status *dc_plane_get_status( 1318 const struct dc_plane_state *plane_state); 1319 1320 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1321 void dc_plane_state_release(struct dc_plane_state *plane_state); 1322 1323 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1324 void dc_gamma_release(struct dc_gamma **dc_gamma); 1325 struct dc_gamma *dc_create_gamma(void); 1326 1327 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1328 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1329 struct dc_transfer_func *dc_create_transfer_func(void); 1330 1331 struct dc_3dlut *dc_create_3dlut_func(void); 1332 void dc_3dlut_func_release(struct dc_3dlut *lut); 1333 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1334 1335 void dc_post_update_surfaces_to_stream( 1336 struct dc *dc); 1337 1338 #include "dc_stream.h" 1339 1340 /** 1341 * struct dc_validation_set - Struct to store surface/stream associations for validation 1342 */ 1343 struct dc_validation_set { 1344 /** 1345 * @stream: Stream state properties 1346 */ 1347 struct dc_stream_state *stream; 1348 1349 /** 1350 * @plane_states: Surface state 1351 */ 1352 struct dc_plane_state *plane_states[MAX_SURFACES]; 1353 1354 /** 1355 * @plane_count: Total of active planes 1356 */ 1357 uint8_t plane_count; 1358 }; 1359 1360 bool dc_validate_boot_timing(const struct dc *dc, 1361 const struct dc_sink *sink, 1362 struct dc_crtc_timing *crtc_timing); 1363 1364 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1365 1366 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1367 1368 enum dc_status dc_validate_with_context(struct dc *dc, 1369 const struct dc_validation_set set[], 1370 int set_count, 1371 struct dc_state *context, 1372 bool fast_validate); 1373 1374 bool dc_set_generic_gpio_for_stereo(bool enable, 1375 struct gpio_service *gpio_service); 1376 1377 /* 1378 * fast_validate: we return after determining if we can support the new state, 1379 * but before we populate the programming info 1380 */ 1381 enum dc_status dc_validate_global_state( 1382 struct dc *dc, 1383 struct dc_state *new_ctx, 1384 bool fast_validate); 1385 1386 1387 void dc_resource_state_construct( 1388 const struct dc *dc, 1389 struct dc_state *dst_ctx); 1390 1391 bool dc_acquire_release_mpc_3dlut( 1392 struct dc *dc, bool acquire, 1393 struct dc_stream_state *stream, 1394 struct dc_3dlut **lut, 1395 struct dc_transfer_func **shaper); 1396 1397 void dc_resource_state_copy_construct( 1398 const struct dc_state *src_ctx, 1399 struct dc_state *dst_ctx); 1400 1401 void dc_resource_state_copy_construct_current( 1402 const struct dc *dc, 1403 struct dc_state *dst_ctx); 1404 1405 void dc_resource_state_destruct(struct dc_state *context); 1406 1407 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1408 1409 enum dc_status dc_commit_streams(struct dc *dc, 1410 struct dc_stream_state *streams[], 1411 uint8_t stream_count); 1412 1413 struct dc_state *dc_create_state(struct dc *dc); 1414 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1415 void dc_retain_state(struct dc_state *context); 1416 void dc_release_state(struct dc_state *context); 1417 1418 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1419 struct dc_stream_state *stream, 1420 int mpcc_inst); 1421 1422 1423 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1424 1425 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1426 1427 /* The function returns minimum bandwidth required to drive a given timing 1428 * return - minimum required timing bandwidth in kbps. 1429 */ 1430 uint32_t dc_bandwidth_in_kbps_from_timing( 1431 const struct dc_crtc_timing *timing, 1432 const enum dc_link_encoding_format link_encoding); 1433 1434 /* Link Interfaces */ 1435 /* 1436 * A link contains one or more sinks and their connected status. 1437 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1438 */ 1439 struct dc_link { 1440 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1441 unsigned int sink_count; 1442 struct dc_sink *local_sink; 1443 unsigned int link_index; 1444 enum dc_connection_type type; 1445 enum signal_type connector_signal; 1446 enum dc_irq_source irq_source_hpd; 1447 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1448 1449 bool is_hpd_filter_disabled; 1450 bool dp_ss_off; 1451 1452 /** 1453 * @link_state_valid: 1454 * 1455 * If there is no link and local sink, this variable should be set to 1456 * false. Otherwise, it should be set to true; usually, the function 1457 * core_link_enable_stream sets this field to true. 1458 */ 1459 bool link_state_valid; 1460 bool aux_access_disabled; 1461 bool sync_lt_in_progress; 1462 bool skip_stream_reenable; 1463 bool is_internal_display; 1464 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1465 bool is_dig_mapping_flexible; 1466 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1467 bool is_hpd_pending; /* Indicates a new received hpd */ 1468 bool is_automated; /* Indicates automated testing */ 1469 1470 bool edp_sink_present; 1471 1472 struct dp_trace dp_trace; 1473 1474 /* caps is the same as reported_link_cap. link_traing use 1475 * reported_link_cap. Will clean up. TODO 1476 */ 1477 struct dc_link_settings reported_link_cap; 1478 struct dc_link_settings verified_link_cap; 1479 struct dc_link_settings cur_link_settings; 1480 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1481 struct dc_link_settings preferred_link_setting; 1482 /* preferred_training_settings are override values that 1483 * come from DM. DM is responsible for the memory 1484 * management of the override pointers. 1485 */ 1486 struct dc_link_training_overrides preferred_training_settings; 1487 struct dp_audio_test_data audio_test_data; 1488 1489 uint8_t ddc_hw_inst; 1490 1491 uint8_t hpd_src; 1492 1493 uint8_t link_enc_hw_inst; 1494 /* DIG link encoder ID. Used as index in link encoder resource pool. 1495 * For links with fixed mapping to DIG, this is not changed after dc_link 1496 * object creation. 1497 */ 1498 enum engine_id eng_id; 1499 enum engine_id dpia_preferred_eng_id; 1500 1501 bool test_pattern_enabled; 1502 enum dp_test_pattern current_test_pattern; 1503 union compliance_test_state compliance_test_state; 1504 1505 void *priv; 1506 1507 struct ddc_service *ddc; 1508 1509 enum dp_panel_mode panel_mode; 1510 bool aux_mode; 1511 1512 /* Private to DC core */ 1513 1514 const struct dc *dc; 1515 1516 struct dc_context *ctx; 1517 1518 struct panel_cntl *panel_cntl; 1519 struct link_encoder *link_enc; 1520 struct graphics_object_id link_id; 1521 /* Endpoint type distinguishes display endpoints which do not have entries 1522 * in the BIOS connector table from those that do. Helps when tracking link 1523 * encoder to display endpoint assignments. 1524 */ 1525 enum display_endpoint_type ep_type; 1526 union ddi_channel_mapping ddi_channel_mapping; 1527 struct connector_device_tag_info device_tag; 1528 struct dpcd_caps dpcd_caps; 1529 uint32_t dongle_max_pix_clk; 1530 unsigned short chip_caps; 1531 unsigned int dpcd_sink_count; 1532 struct hdcp_caps hdcp_caps; 1533 enum edp_revision edp_revision; 1534 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1535 1536 struct backlight_settings backlight_settings; 1537 struct psr_settings psr_settings; 1538 1539 struct replay_settings replay_settings; 1540 1541 /* Drive settings read from integrated info table */ 1542 struct dc_lane_settings bios_forced_drive_settings; 1543 1544 /* Vendor specific LTTPR workaround variables */ 1545 uint8_t vendor_specific_lttpr_link_rate_wa; 1546 bool apply_vendor_specific_lttpr_link_rate_wa; 1547 1548 /* MST record stream using this link */ 1549 struct link_flags { 1550 bool dp_keep_receiver_powered; 1551 bool dp_skip_DID2; 1552 bool dp_skip_reset_segment; 1553 bool dp_skip_fs_144hz; 1554 bool dp_mot_reset_segment; 1555 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1556 bool dpia_mst_dsc_always_on; 1557 /* Forced DPIA into TBT3 compatibility mode. */ 1558 bool dpia_forced_tbt3_mode; 1559 bool dongle_mode_timing_override; 1560 bool blank_stream_on_ocs_change; 1561 bool read_dpcd204h_on_irq_hpd; 1562 } wa_flags; 1563 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1564 1565 struct dc_link_status link_status; 1566 struct dprx_states dprx_states; 1567 1568 struct gpio *hpd_gpio; 1569 enum dc_link_fec_state fec_state; 1570 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1571 1572 struct dc_panel_config panel_config; 1573 struct phy_state phy_state; 1574 // BW ALLOCATON USB4 ONLY 1575 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1576 }; 1577 1578 /* Return an enumerated dc_link. 1579 * dc_link order is constant and determined at 1580 * boot time. They cannot be created or destroyed. 1581 * Use dc_get_caps() to get number of links. 1582 */ 1583 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1584 1585 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1586 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1587 const struct dc_link *link, 1588 unsigned int *inst_out); 1589 1590 /* Return an array of link pointers to edp links. */ 1591 void dc_get_edp_links(const struct dc *dc, 1592 struct dc_link **edp_links, 1593 int *edp_num); 1594 1595 /* The function initiates detection handshake over the given link. It first 1596 * determines if there are display connections over the link. If so it initiates 1597 * detection protocols supported by the connected receiver device. The function 1598 * contains protocol specific handshake sequences which are sometimes mandatory 1599 * to establish a proper connection between TX and RX. So it is always 1600 * recommended to call this function as the first link operation upon HPD event 1601 * or power up event. Upon completion, the function will update link structure 1602 * in place based on latest RX capabilities. The function may also cause dpms 1603 * to be reset to off for all currently enabled streams to the link. It is DM's 1604 * responsibility to serialize detection and DPMS updates. 1605 * 1606 * @reason - Indicate which event triggers this detection. dc may customize 1607 * detection flow depending on the triggering events. 1608 * return false - if detection is not fully completed. This could happen when 1609 * there is an unrecoverable error during detection or detection is partially 1610 * completed (detection has been delegated to dm mst manager ie. 1611 * link->connection_type == dc_connection_mst_branch when returning false). 1612 * return true - detection is completed, link has been fully updated with latest 1613 * detection result. 1614 */ 1615 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1616 1617 struct dc_sink_init_data; 1618 1619 /* When link connection type is dc_connection_mst_branch, remote sink can be 1620 * added to the link. The interface creates a remote sink and associates it with 1621 * current link. The sink will be retained by link until remove remote sink is 1622 * called. 1623 * 1624 * @dc_link - link the remote sink will be added to. 1625 * @edid - byte array of EDID raw data. 1626 * @len - size of the edid in byte 1627 * @init_data - 1628 */ 1629 struct dc_sink *dc_link_add_remote_sink( 1630 struct dc_link *dc_link, 1631 const uint8_t *edid, 1632 int len, 1633 struct dc_sink_init_data *init_data); 1634 1635 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1636 * @link - link the sink should be removed from 1637 * @sink - sink to be removed. 1638 */ 1639 void dc_link_remove_remote_sink( 1640 struct dc_link *link, 1641 struct dc_sink *sink); 1642 1643 /* Enable HPD interrupt handler for a given link */ 1644 void dc_link_enable_hpd(const struct dc_link *link); 1645 1646 /* Disable HPD interrupt handler for a given link */ 1647 void dc_link_disable_hpd(const struct dc_link *link); 1648 1649 /* determine if there is a sink connected to the link 1650 * 1651 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1652 * return - false if an unexpected error occurs, true otherwise. 1653 * 1654 * NOTE: This function doesn't detect downstream sink connections i.e 1655 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1656 * return dc_connection_single if the branch device is connected despite of 1657 * downstream sink's connection status. 1658 */ 1659 bool dc_link_detect_connection_type(struct dc_link *link, 1660 enum dc_connection_type *type); 1661 1662 /* query current hpd pin value 1663 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1664 * 1665 */ 1666 bool dc_link_get_hpd_state(struct dc_link *link); 1667 1668 /* Getter for cached link status from given link */ 1669 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1670 1671 /* enable/disable hardware HPD filter. 1672 * 1673 * @link - The link the HPD pin is associated with. 1674 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1675 * handler once after no HPD change has been detected within dc default HPD 1676 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1677 * pulses within default HPD interval, no HPD event will be received until HPD 1678 * toggles have stopped. Then HPD event will be queued to irq handler once after 1679 * dc default HPD filtering interval since last HPD event. 1680 * 1681 * @enable = false - disable hardware HPD filter. HPD event will be queued 1682 * immediately to irq handler after no HPD change has been detected within 1683 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1684 */ 1685 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1686 1687 /* submit i2c read/write payloads through ddc channel 1688 * @link_index - index to a link with ddc in i2c mode 1689 * @cmd - i2c command structure 1690 * return - true if success, false otherwise. 1691 */ 1692 bool dc_submit_i2c( 1693 struct dc *dc, 1694 uint32_t link_index, 1695 struct i2c_command *cmd); 1696 1697 /* submit i2c read/write payloads through oem channel 1698 * @link_index - index to a link with ddc in i2c mode 1699 * @cmd - i2c command structure 1700 * return - true if success, false otherwise. 1701 */ 1702 bool dc_submit_i2c_oem( 1703 struct dc *dc, 1704 struct i2c_command *cmd); 1705 1706 enum aux_return_code_type; 1707 /* Attempt to transfer the given aux payload. This function does not perform 1708 * retries or handle error states. The reply is returned in the payload->reply 1709 * and the result through operation_result. Returns the number of bytes 1710 * transferred,or -1 on a failure. 1711 */ 1712 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1713 struct aux_payload *payload, 1714 enum aux_return_code_type *operation_result); 1715 1716 bool dc_is_oem_i2c_device_present( 1717 struct dc *dc, 1718 size_t slave_address 1719 ); 1720 1721 /* return true if the connected receiver supports the hdcp version */ 1722 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1723 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1724 1725 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1726 * 1727 * TODO - When defer_handling is true the function will have a different purpose. 1728 * It no longer does complete hpd rx irq handling. We should create a separate 1729 * interface specifically for this case. 1730 * 1731 * Return: 1732 * true - Downstream port status changed. DM should call DC to do the 1733 * detection. 1734 * false - no change in Downstream port status. No further action required 1735 * from DM. 1736 */ 1737 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1738 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1739 bool defer_handling, bool *has_left_work); 1740 /* handle DP specs define test automation sequence*/ 1741 void dc_link_dp_handle_automated_test(struct dc_link *link); 1742 1743 /* handle DP Link loss sequence and try to recover RX link loss with best 1744 * effort 1745 */ 1746 void dc_link_dp_handle_link_loss(struct dc_link *link); 1747 1748 /* Determine if hpd rx irq should be handled or ignored 1749 * return true - hpd rx irq should be handled. 1750 * return false - it is safe to ignore hpd rx irq event 1751 */ 1752 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1753 1754 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1755 * @link - link the hpd irq data associated with 1756 * @hpd_irq_dpcd_data - input hpd irq data 1757 * return - true if hpd irq data indicates a link lost 1758 */ 1759 bool dc_link_check_link_loss_status(struct dc_link *link, 1760 union hpd_irq_data *hpd_irq_dpcd_data); 1761 1762 /* Read hpd rx irq data from a given link 1763 * @link - link where the hpd irq data should be read from 1764 * @irq_data - output hpd irq data 1765 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1766 * read has failed. 1767 */ 1768 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1769 struct dc_link *link, 1770 union hpd_irq_data *irq_data); 1771 1772 /* The function clears recorded DP RX states in the link. DM should call this 1773 * function when it is resuming from S3 power state to previously connected links. 1774 * 1775 * TODO - in the future we should consider to expand link resume interface to 1776 * support clearing previous rx states. So we don't have to rely on dm to call 1777 * this interface explicitly. 1778 */ 1779 void dc_link_clear_dprx_states(struct dc_link *link); 1780 1781 /* Destruct the mst topology of the link and reset the allocated payload table 1782 * 1783 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1784 * still wants to reset MST topology on an unplug event */ 1785 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1786 1787 /* The function calculates effective DP link bandwidth when a given link is 1788 * using the given link settings. 1789 * 1790 * return - total effective link bandwidth in kbps. 1791 */ 1792 uint32_t dc_link_bandwidth_kbps( 1793 const struct dc_link *link, 1794 const struct dc_link_settings *link_setting); 1795 1796 /* The function takes a snapshot of current link resource allocation state 1797 * @dc: pointer to dc of the dm calling this 1798 * @map: a dc link resource snapshot defined internally to dc. 1799 * 1800 * DM needs to capture a snapshot of current link resource allocation mapping 1801 * and store it in its persistent storage. 1802 * 1803 * Some of the link resource is using first come first serve policy. 1804 * The allocation mapping depends on original hotplug order. This information 1805 * is lost after driver is loaded next time. The snapshot is used in order to 1806 * restore link resource to its previous state so user will get consistent 1807 * link capability allocation across reboot. 1808 * 1809 */ 1810 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1811 1812 /* This function restores link resource allocation state from a snapshot 1813 * @dc: pointer to dc of the dm calling this 1814 * @map: a dc link resource snapshot defined internally to dc. 1815 * 1816 * DM needs to call this function after initial link detection on boot and 1817 * before first commit streams to restore link resource allocation state 1818 * from previous boot session. 1819 * 1820 * Some of the link resource is using first come first serve policy. 1821 * The allocation mapping depends on original hotplug order. This information 1822 * is lost after driver is loaded next time. The snapshot is used in order to 1823 * restore link resource to its previous state so user will get consistent 1824 * link capability allocation across reboot. 1825 * 1826 */ 1827 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1828 1829 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1830 * interface i.e stream_update->dsc_config 1831 */ 1832 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1833 1834 /* translate a raw link rate data to bandwidth in kbps */ 1835 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 1836 1837 /* determine the optimal bandwidth given link and required bw. 1838 * @link - current detected link 1839 * @req_bw - requested bandwidth in kbps 1840 * @link_settings - returned most optimal link settings that can fit the 1841 * requested bandwidth 1842 * return - false if link can't support requested bandwidth, true if link 1843 * settings is found. 1844 */ 1845 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1846 struct dc_link_settings *link_settings, 1847 uint32_t req_bw); 1848 1849 /* return the max dp link settings can be driven by the link without considering 1850 * connected RX device and its capability 1851 */ 1852 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1853 struct dc_link_settings *max_link_enc_cap); 1854 1855 /* determine when the link is driving MST mode, what DP link channel coding 1856 * format will be used. The decision will remain unchanged until next HPD event. 1857 * 1858 * @link - a link with DP RX connection 1859 * return - if stream is committed to this link with MST signal type, type of 1860 * channel coding format dc will choose. 1861 */ 1862 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1863 const struct dc_link *link); 1864 1865 /* get max dp link settings the link can enable with all things considered. (i.e 1866 * TX/RX/Cable capabilities and dp override policies. 1867 * 1868 * @link - a link with DP RX connection 1869 * return - max dp link settings the link can enable. 1870 * 1871 */ 1872 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 1873 1874 /* Get the highest encoding format that the link supports; highest meaning the 1875 * encoding format which supports the maximum bandwidth. 1876 * 1877 * @link - a link with DP RX connection 1878 * return - highest encoding format link supports. 1879 */ 1880 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 1881 1882 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 1883 * to a link with dp connector signal type. 1884 * @link - a link with dp connector signal type 1885 * return - true if connected, false otherwise 1886 */ 1887 bool dc_link_is_dp_sink_present(struct dc_link *link); 1888 1889 /* Force DP lane settings update to main-link video signal and notify the change 1890 * to DP RX via DPCD. This is a debug interface used for video signal integrity 1891 * tuning purpose. The interface assumes link has already been enabled with DP 1892 * signal. 1893 * 1894 * @lt_settings - a container structure with desired hw_lane_settings 1895 */ 1896 void dc_link_set_drive_settings(struct dc *dc, 1897 struct link_training_settings *lt_settings, 1898 struct dc_link *link); 1899 1900 /* Enable a test pattern in Link or PHY layer in an active link for compliance 1901 * test or debugging purpose. The test pattern will remain until next un-plug. 1902 * 1903 * @link - active link with DP signal output enabled. 1904 * @test_pattern - desired test pattern to output. 1905 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 1906 * @test_pattern_color_space - for video test pattern choose a desired color 1907 * space. 1908 * @p_link_settings - For PHY pattern choose a desired link settings 1909 * @p_custom_pattern - some test pattern will require a custom input to 1910 * customize some pattern details. Otherwise keep it to NULL. 1911 * @cust_pattern_size - size of the custom pattern input. 1912 * 1913 */ 1914 bool dc_link_dp_set_test_pattern( 1915 struct dc_link *link, 1916 enum dp_test_pattern test_pattern, 1917 enum dp_test_pattern_color_space test_pattern_color_space, 1918 const struct link_training_settings *p_link_settings, 1919 const unsigned char *p_custom_pattern, 1920 unsigned int cust_pattern_size); 1921 1922 /* Force DP link settings to always use a specific value until reboot to a 1923 * specific link. If link has already been enabled, the interface will also 1924 * switch to desired link settings immediately. This is a debug interface to 1925 * generic dp issue trouble shooting. 1926 */ 1927 void dc_link_set_preferred_link_settings(struct dc *dc, 1928 struct dc_link_settings *link_setting, 1929 struct dc_link *link); 1930 1931 /* Force DP link to customize a specific link training behavior by overriding to 1932 * standard DP specs defined protocol. This is a debug interface to trouble shoot 1933 * display specific link training issues or apply some display specific 1934 * workaround in link training. 1935 * 1936 * @link_settings - if not NULL, force preferred link settings to the link. 1937 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 1938 * will apply this particular override in future link training. If NULL is 1939 * passed in, dc resets previous overrides. 1940 * NOTE: DM must keep the memory from override pointers until DM resets preferred 1941 * training settings. 1942 */ 1943 void dc_link_set_preferred_training_settings(struct dc *dc, 1944 struct dc_link_settings *link_setting, 1945 struct dc_link_training_overrides *lt_overrides, 1946 struct dc_link *link, 1947 bool skip_immediate_retrain); 1948 1949 /* return - true if FEC is supported with connected DP RX, false otherwise */ 1950 bool dc_link_is_fec_supported(const struct dc_link *link); 1951 1952 /* query FEC enablement policy to determine if FEC will be enabled by dc during 1953 * link enablement. 1954 * return - true if FEC should be enabled, false otherwise. 1955 */ 1956 bool dc_link_should_enable_fec(const struct dc_link *link); 1957 1958 /* determine lttpr mode the current link should be enabled with a specific link 1959 * settings. 1960 */ 1961 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 1962 struct dc_link_settings *link_setting); 1963 1964 /* Force DP RX to update its power state. 1965 * NOTE: this interface doesn't update dp main-link. Calling this function will 1966 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 1967 * RX power state back upon finish DM specific execution requiring DP RX in a 1968 * specific power state. 1969 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 1970 * state. 1971 */ 1972 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 1973 1974 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 1975 * current value read from extended receiver cap from 02200h - 0220Fh. 1976 * Some DP RX has problems of providing accurate DP receiver caps from extended 1977 * field, this interface is a workaround to revert link back to use base caps. 1978 */ 1979 void dc_link_overwrite_extended_receiver_cap( 1980 struct dc_link *link); 1981 1982 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 1983 bool wait_for_hpd); 1984 1985 /* Set backlight level of an embedded panel (eDP, LVDS). 1986 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 1987 * and 16 bit fractional, where 1.0 is max backlight value. 1988 */ 1989 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 1990 uint32_t backlight_pwm_u16_16, 1991 uint32_t frame_ramp); 1992 1993 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 1994 bool dc_link_set_backlight_level_nits(struct dc_link *link, 1995 bool isHDR, 1996 uint32_t backlight_millinits, 1997 uint32_t transition_time_in_ms); 1998 1999 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2000 uint32_t *backlight_millinits, 2001 uint32_t *backlight_millinits_peak); 2002 2003 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2004 2005 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2006 2007 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2008 bool wait, bool force_static, const unsigned int *power_opts); 2009 2010 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2011 2012 bool dc_link_setup_psr(struct dc_link *dc_link, 2013 const struct dc_stream_state *stream, struct psr_config *psr_config, 2014 struct psr_context *psr_context); 2015 2016 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2017 2018 /* On eDP links this function call will stall until T12 has elapsed. 2019 * If the panel is not in power off state, this function will return 2020 * immediately. 2021 */ 2022 bool dc_link_wait_for_t12(struct dc_link *link); 2023 2024 /* Determine if dp trace has been initialized to reflect upto date result * 2025 * return - true if trace is initialized and has valid data. False dp trace 2026 * doesn't have valid result. 2027 */ 2028 bool dc_dp_trace_is_initialized(struct dc_link *link); 2029 2030 /* Query a dp trace flag to indicate if the current dp trace data has been 2031 * logged before 2032 */ 2033 bool dc_dp_trace_is_logged(struct dc_link *link, 2034 bool in_detection); 2035 2036 /* Set dp trace flag to indicate whether DM has already logged the current dp 2037 * trace data. DM can set is_logged to true upon logging and check 2038 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2039 */ 2040 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2041 bool in_detection, 2042 bool is_logged); 2043 2044 /* Obtain driver time stamp for last dp link training end. The time stamp is 2045 * formatted based on dm_get_timestamp DM function. 2046 * @in_detection - true to get link training end time stamp of last link 2047 * training in detection sequence. false to get link training end time stamp 2048 * of last link training in commit (dpms) sequence 2049 */ 2050 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2051 bool in_detection); 2052 2053 /* Get how many link training attempts dc has done with latest sequence. 2054 * @in_detection - true to get link training count of last link 2055 * training in detection sequence. false to get link training count of last link 2056 * training in commit (dpms) sequence 2057 */ 2058 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2059 bool in_detection); 2060 2061 /* Get how many link loss has happened since last link training attempts */ 2062 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2063 2064 /* 2065 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2066 */ 2067 /* 2068 * Send a request from DP-Tx requesting to allocate BW remotely after 2069 * allocating it locally. This will get processed by CM and a CB function 2070 * will be called. 2071 * 2072 * @link: pointer to the dc_link struct instance 2073 * @req_bw: The requested bw in Kbyte to allocated 2074 * 2075 * return: none 2076 */ 2077 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2078 2079 /* 2080 * Handle function for when the status of the Request above is complete. 2081 * We will find out the result of allocating on CM and update structs. 2082 * 2083 * @link: pointer to the dc_link struct instance 2084 * @bw: Allocated or Estimated BW depending on the result 2085 * @result: Response type 2086 * 2087 * return: none 2088 */ 2089 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2090 uint8_t bw, uint8_t result); 2091 2092 /* 2093 * Handle the USB4 BW Allocation related functionality here: 2094 * Plug => Try to allocate max bw from timing parameters supported by the sink 2095 * Unplug => de-allocate bw 2096 * 2097 * @link: pointer to the dc_link struct instance 2098 * @peak_bw: Peak bw used by the link/sink 2099 * 2100 * return: allocated bw else return 0 2101 */ 2102 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2103 struct dc_link *link, int peak_bw); 2104 2105 /* 2106 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2107 * available BW for each host router 2108 * 2109 * @dc: pointer to dc struct 2110 * @stream: pointer to all possible streams 2111 * @num_streams: number of valid DPIA streams 2112 * 2113 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2114 */ 2115 bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, 2116 const unsigned int count); 2117 2118 /* Sink Interfaces - A sink corresponds to a display output device */ 2119 2120 struct dc_container_id { 2121 // 128bit GUID in binary form 2122 unsigned char guid[16]; 2123 // 8 byte port ID -> ELD.PortID 2124 unsigned int portId[2]; 2125 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2126 unsigned short manufacturerName; 2127 // 2 byte product code -> ELD.ProductCode 2128 unsigned short productCode; 2129 }; 2130 2131 2132 struct dc_sink_dsc_caps { 2133 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2134 // 'false' if they are sink's DSC caps 2135 bool is_virtual_dpcd_dsc; 2136 #if defined(CONFIG_DRM_AMD_DC_FP) 2137 // 'true' if MST topology supports DSC passthrough for sink 2138 // 'false' if MST topology does not support DSC passthrough 2139 bool is_dsc_passthrough_supported; 2140 #endif 2141 struct dsc_dec_dpcd_caps dsc_dec_caps; 2142 }; 2143 2144 struct dc_sink_fec_caps { 2145 bool is_rx_fec_supported; 2146 bool is_topology_fec_supported; 2147 }; 2148 2149 struct scdc_caps { 2150 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2151 union hdmi_scdc_device_id_data device_id; 2152 }; 2153 2154 /* 2155 * The sink structure contains EDID and other display device properties 2156 */ 2157 struct dc_sink { 2158 enum signal_type sink_signal; 2159 struct dc_edid dc_edid; /* raw edid */ 2160 struct dc_edid_caps edid_caps; /* parse display caps */ 2161 struct dc_container_id *dc_container_id; 2162 uint32_t dongle_max_pix_clk; 2163 void *priv; 2164 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2165 bool converter_disable_audio; 2166 2167 struct scdc_caps scdc_caps; 2168 struct dc_sink_dsc_caps dsc_caps; 2169 struct dc_sink_fec_caps fec_caps; 2170 2171 bool is_vsc_sdp_colorimetry_supported; 2172 2173 /* private to DC core */ 2174 struct dc_link *link; 2175 struct dc_context *ctx; 2176 2177 uint32_t sink_id; 2178 2179 /* private to dc_sink.c */ 2180 // refcount must be the last member in dc_sink, since we want the 2181 // sink structure to be logically cloneable up to (but not including) 2182 // refcount 2183 struct kref refcount; 2184 }; 2185 2186 void dc_sink_retain(struct dc_sink *sink); 2187 void dc_sink_release(struct dc_sink *sink); 2188 2189 struct dc_sink_init_data { 2190 enum signal_type sink_signal; 2191 struct dc_link *link; 2192 uint32_t dongle_max_pix_clk; 2193 bool converter_disable_audio; 2194 }; 2195 2196 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2197 2198 /* Newer interfaces */ 2199 struct dc_cursor { 2200 struct dc_plane_address address; 2201 struct dc_cursor_attributes attributes; 2202 }; 2203 2204 2205 /* Interrupt interfaces */ 2206 enum dc_irq_source dc_interrupt_to_irq_source( 2207 struct dc *dc, 2208 uint32_t src_id, 2209 uint32_t ext_id); 2210 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2211 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2212 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2213 struct dc *dc, uint32_t link_index); 2214 2215 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2216 2217 /* Power Interfaces */ 2218 2219 void dc_set_power_state( 2220 struct dc *dc, 2221 enum dc_acpi_cm_power_state power_state); 2222 void dc_resume(struct dc *dc); 2223 2224 void dc_power_down_on_boot(struct dc *dc); 2225 2226 /* 2227 * HDCP Interfaces 2228 */ 2229 enum hdcp_message_status dc_process_hdcp_msg( 2230 enum signal_type signal, 2231 struct dc_link *link, 2232 struct hdcp_protection_message *message_info); 2233 bool dc_is_dmcu_initialized(struct dc *dc); 2234 2235 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2236 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2237 2238 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 2239 struct dc_cursor_attributes *cursor_attr); 2240 2241 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 2242 2243 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2244 void dc_unlock_memory_clock_frequency(struct dc *dc); 2245 2246 /* set min memory clock to the min required for current mode, max to maxDPM */ 2247 void dc_lock_memory_clock_frequency(struct dc *dc); 2248 2249 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2250 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2251 2252 /* cleanup on driver unload */ 2253 void dc_hardware_release(struct dc *dc); 2254 2255 /* disables fw based mclk switch */ 2256 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2257 2258 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2259 void dc_z10_restore(const struct dc *dc); 2260 void dc_z10_save_init(struct dc *dc); 2261 2262 bool dc_is_dmub_outbox_supported(struct dc *dc); 2263 bool dc_enable_dmub_notifications(struct dc *dc); 2264 2265 bool dc_abm_save_restore( 2266 struct dc *dc, 2267 struct dc_stream_state *stream, 2268 struct abm_save_restore *pData); 2269 2270 void dc_enable_dmub_outbox(struct dc *dc); 2271 2272 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2273 uint32_t link_index, 2274 struct aux_payload *payload); 2275 2276 /* Get dc link index from dpia port index */ 2277 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2278 uint8_t dpia_port_index); 2279 2280 bool dc_process_dmub_set_config_async(struct dc *dc, 2281 uint32_t link_index, 2282 struct set_config_cmd_payload *payload, 2283 struct dmub_notification *notify); 2284 2285 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2286 uint32_t link_index, 2287 uint8_t mst_alloc_slots, 2288 uint8_t *mst_slots_in_use); 2289 2290 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2291 uint32_t hpd_int_enable); 2292 2293 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2294 2295 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2296 2297 /* DSC Interfaces */ 2298 #include "dc_dsc.h" 2299 2300 /* Disable acc mode Interfaces */ 2301 void dc_disable_accelerated_mode(struct dc *dc); 2302 2303 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2304 struct dc_stream_state *new_stream); 2305 2306 #endif /* DC_INTERFACE_H_ */ 2307