1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.08" 43 44 #define MAX_SURFACES 3 45 #define MAX_STREAMS 6 46 #define MAX_SINKS_PER_LINK 4 47 48 /******************************************************************************* 49 * Display Core Interfaces 50 ******************************************************************************/ 51 struct dc_versions { 52 const char *dc_ver; 53 struct dmcu_version dmcu_version; 54 }; 55 56 struct dc_caps { 57 uint32_t max_streams; 58 uint32_t max_links; 59 uint32_t max_audios; 60 uint32_t max_slave_planes; 61 uint32_t max_planes; 62 uint32_t max_downscale_ratio; 63 uint32_t i2c_speed_in_khz; 64 uint32_t dmdata_alloc_size; 65 unsigned int max_cursor_size; 66 unsigned int max_video_width; 67 int linear_pitch_alignment; 68 bool dcc_const_color; 69 bool dynamic_audio; 70 bool is_apu; 71 bool dual_link_dvi; 72 bool post_blend_color_processing; 73 bool force_dp_tps4_for_cp2520; 74 bool disable_dp_clk_share; 75 bool psp_setup_panel_mode; 76 }; 77 78 struct dc_dcc_surface_param { 79 struct dc_size surface_size; 80 enum surface_pixel_format format; 81 enum swizzle_mode_values swizzle_mode; 82 enum dc_scan_direction scan; 83 }; 84 85 struct dc_dcc_setting { 86 unsigned int max_compressed_blk_size; 87 unsigned int max_uncompressed_blk_size; 88 bool independent_64b_blks; 89 }; 90 91 struct dc_surface_dcc_cap { 92 union { 93 struct { 94 struct dc_dcc_setting rgb; 95 } grph; 96 97 struct { 98 struct dc_dcc_setting luma; 99 struct dc_dcc_setting chroma; 100 } video; 101 }; 102 103 bool capable; 104 bool const_color_support; 105 }; 106 107 struct dc_static_screen_events { 108 bool force_trigger; 109 bool cursor_update; 110 bool surface_update; 111 bool overlay_update; 112 }; 113 114 115 /* Surface update type is used by dc_update_surfaces_and_stream 116 * The update type is determined at the very beginning of the function based 117 * on parameters passed in and decides how much programming (or updating) is 118 * going to be done during the call. 119 * 120 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 121 * logical calculations or hardware register programming. This update MUST be 122 * ISR safe on windows. Currently fast update will only be used to flip surface 123 * address. 124 * 125 * UPDATE_TYPE_MED is used for slower updates which require significant hw 126 * re-programming however do not affect bandwidth consumption or clock 127 * requirements. At present, this is the level at which front end updates 128 * that do not require us to run bw_calcs happen. These are in/out transfer func 129 * updates, viewport offset changes, recout size changes and pixel depth changes. 130 * This update can be done at ISR, but we want to minimize how often this happens. 131 * 132 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 133 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 134 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 135 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 136 * a full update. This cannot be done at ISR level and should be a rare event. 137 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 138 * underscan we don't expect to see this call at all. 139 */ 140 141 enum surface_update_type { 142 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 143 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 144 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 145 }; 146 147 /* Forward declaration*/ 148 struct dc; 149 struct dc_plane_state; 150 struct dc_state; 151 152 153 struct dc_cap_funcs { 154 bool (*get_dcc_compression_cap)(const struct dc *dc, 155 const struct dc_dcc_surface_param *input, 156 struct dc_surface_dcc_cap *output); 157 }; 158 159 struct link_training_settings; 160 161 162 /* Structure to hold configuration flags set by dm at dc creation. */ 163 struct dc_config { 164 bool gpu_vm_support; 165 bool disable_disp_pll_sharing; 166 bool fbc_support; 167 }; 168 169 enum visual_confirm { 170 VISUAL_CONFIRM_DISABLE = 0, 171 VISUAL_CONFIRM_SURFACE = 1, 172 VISUAL_CONFIRM_HDR = 2, 173 }; 174 175 enum dcc_option { 176 DCC_ENABLE = 0, 177 DCC_DISABLE = 1, 178 DCC_HALF_REQ_DISALBE = 2, 179 }; 180 181 enum pipe_split_policy { 182 MPC_SPLIT_DYNAMIC = 0, 183 MPC_SPLIT_AVOID = 1, 184 MPC_SPLIT_AVOID_MULT_DISP = 2, 185 }; 186 187 enum wm_report_mode { 188 WM_REPORT_DEFAULT = 0, 189 WM_REPORT_OVERRIDE = 1, 190 }; 191 192 /* 193 * For any clocks that may differ per pipe 194 * only the max is stored in this structure 195 */ 196 struct dc_clocks { 197 int dispclk_khz; 198 int max_supported_dppclk_khz; 199 int dppclk_khz; 200 int dcfclk_khz; 201 int socclk_khz; 202 int dcfclk_deep_sleep_khz; 203 int fclk_khz; 204 int phyclk_khz; 205 int dramclk_khz; 206 }; 207 208 struct dc_debug_options { 209 enum visual_confirm visual_confirm; 210 bool sanity_checks; 211 bool max_disp_clk; 212 bool surface_trace; 213 bool timing_trace; 214 bool clock_trace; 215 bool validation_trace; 216 bool bandwidth_calcs_trace; 217 int max_downscale_src_width; 218 219 /* stutter efficiency related */ 220 bool disable_stutter; 221 bool use_max_lb; 222 enum dcc_option disable_dcc; 223 enum pipe_split_policy pipe_split_policy; 224 bool force_single_disp_pipe_split; 225 bool voltage_align_fclk; 226 227 bool disable_dfs_bypass; 228 bool disable_dpp_power_gate; 229 bool disable_hubp_power_gate; 230 bool disable_pplib_wm_range; 231 enum wm_report_mode pplib_wm_report_mode; 232 unsigned int min_disp_clk_khz; 233 int sr_exit_time_dpm0_ns; 234 int sr_enter_plus_exit_time_dpm0_ns; 235 int sr_exit_time_ns; 236 int sr_enter_plus_exit_time_ns; 237 int urgent_latency_ns; 238 int percent_of_ideal_drambw; 239 int dram_clock_change_latency_ns; 240 bool optimized_watermark; 241 int always_scale; 242 bool disable_pplib_clock_request; 243 bool disable_clock_gate; 244 bool disable_dmcu; 245 bool disable_psr; 246 bool force_abm_enable; 247 bool disable_stereo_support; 248 bool vsr_support; 249 bool performance_trace; 250 bool az_endpoint_mute_only; 251 bool always_use_regamma; 252 bool p010_mpo_support; 253 bool recovery_enabled; 254 bool avoid_vbios_exec_table; 255 bool scl_reset_length10; 256 bool hdmi20_disable; 257 bool skip_detection_link_training; 258 }; 259 260 struct dc_debug_data { 261 uint32_t ltFailCount; 262 uint32_t i2cErrorCount; 263 uint32_t auxErrorCount; 264 }; 265 266 267 struct dc_state; 268 struct resource_pool; 269 struct dce_hwseq; 270 struct dc { 271 struct dc_versions versions; 272 struct dc_caps caps; 273 struct dc_cap_funcs cap_funcs; 274 struct dc_config config; 275 struct dc_debug_options debug; 276 struct dc_context *ctx; 277 278 uint8_t link_count; 279 struct dc_link *links[MAX_PIPES * 2]; 280 281 struct dc_state *current_state; 282 struct resource_pool *res_pool; 283 284 /* Display Engine Clock levels */ 285 struct dm_pp_clock_levels sclk_lvls; 286 287 /* Inputs into BW and WM calculations. */ 288 struct bw_calcs_dceip *bw_dceip; 289 struct bw_calcs_vbios *bw_vbios; 290 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 291 struct dcn_soc_bounding_box *dcn_soc; 292 struct dcn_ip_params *dcn_ip; 293 struct display_mode_lib dml; 294 #endif 295 296 /* HW functions */ 297 struct hw_sequencer_funcs hwss; 298 struct dce_hwseq *hwseq; 299 300 bool optimized_required; 301 302 /* FBC compressor */ 303 struct compressor *fbc_compressor; 304 305 struct dc_debug_data debug_data; 306 307 const char *build_id; 308 }; 309 310 enum frame_buffer_mode { 311 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 312 FRAME_BUFFER_MODE_ZFB_ONLY, 313 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 314 } ; 315 316 struct dchub_init_data { 317 int64_t zfb_phys_addr_base; 318 int64_t zfb_mc_base_addr; 319 uint64_t zfb_size_in_byte; 320 enum frame_buffer_mode fb_mode; 321 bool dchub_initialzied; 322 bool dchub_info_valid; 323 }; 324 325 struct dc_init_data { 326 struct hw_asic_id asic_id; 327 void *driver; /* ctx */ 328 struct cgs_device *cgs_device; 329 330 int num_virtual_links; 331 /* 332 * If 'vbios_override' not NULL, it will be called instead 333 * of the real VBIOS. Intended use is Diagnostics on FPGA. 334 */ 335 struct dc_bios *vbios_override; 336 enum dce_environment dce_environment; 337 338 struct dc_config flags; 339 uint32_t log_mask; 340 }; 341 342 struct dc *dc_create(const struct dc_init_data *init_params); 343 344 void dc_destroy(struct dc **dc); 345 346 /******************************************************************************* 347 * Surface Interfaces 348 ******************************************************************************/ 349 350 enum { 351 TRANSFER_FUNC_POINTS = 1025 352 }; 353 354 struct dc_hdr_static_metadata { 355 /* display chromaticities and white point in units of 0.00001 */ 356 unsigned int chromaticity_green_x; 357 unsigned int chromaticity_green_y; 358 unsigned int chromaticity_blue_x; 359 unsigned int chromaticity_blue_y; 360 unsigned int chromaticity_red_x; 361 unsigned int chromaticity_red_y; 362 unsigned int chromaticity_white_point_x; 363 unsigned int chromaticity_white_point_y; 364 365 uint32_t min_luminance; 366 uint32_t max_luminance; 367 uint32_t maximum_content_light_level; 368 uint32_t maximum_frame_average_light_level; 369 }; 370 371 enum dc_transfer_func_type { 372 TF_TYPE_PREDEFINED, 373 TF_TYPE_DISTRIBUTED_POINTS, 374 TF_TYPE_BYPASS, 375 TF_TYPE_HWPWL 376 }; 377 378 struct dc_transfer_func_distributed_points { 379 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 380 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 381 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 382 383 uint16_t end_exponent; 384 uint16_t x_point_at_y1_red; 385 uint16_t x_point_at_y1_green; 386 uint16_t x_point_at_y1_blue; 387 }; 388 389 enum dc_transfer_func_predefined { 390 TRANSFER_FUNCTION_SRGB, 391 TRANSFER_FUNCTION_BT709, 392 TRANSFER_FUNCTION_PQ, 393 TRANSFER_FUNCTION_LINEAR, 394 TRANSFER_FUNCTION_UNITY, 395 TRANSFER_FUNCTION_HLG, 396 TRANSFER_FUNCTION_HLG12, 397 TRANSFER_FUNCTION_GAMMA22 398 }; 399 400 struct dc_transfer_func { 401 struct kref refcount; 402 enum dc_transfer_func_type type; 403 enum dc_transfer_func_predefined tf; 404 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 405 uint32_t sdr_ref_white_level; 406 struct dc_context *ctx; 407 union { 408 struct pwl_params pwl; 409 struct dc_transfer_func_distributed_points tf_pts; 410 }; 411 }; 412 413 /* 414 * This structure is filled in by dc_surface_get_status and contains 415 * the last requested address and the currently active address so the called 416 * can determine if there are any outstanding flips 417 */ 418 struct dc_plane_status { 419 struct dc_plane_address requested_address; 420 struct dc_plane_address current_address; 421 bool is_flip_pending; 422 bool is_right_eye; 423 }; 424 425 union surface_update_flags { 426 427 struct { 428 /* Medium updates */ 429 uint32_t dcc_change:1; 430 uint32_t color_space_change:1; 431 uint32_t horizontal_mirror_change:1; 432 uint32_t per_pixel_alpha_change:1; 433 uint32_t global_alpha_change:1; 434 uint32_t rotation_change:1; 435 uint32_t swizzle_change:1; 436 uint32_t scaling_change:1; 437 uint32_t position_change:1; 438 uint32_t in_transfer_func_change:1; 439 uint32_t input_csc_change:1; 440 uint32_t coeff_reduction_change:1; 441 uint32_t output_tf_change:1; 442 uint32_t pixel_format_change:1; 443 444 /* Full updates */ 445 uint32_t new_plane:1; 446 uint32_t bpp_change:1; 447 uint32_t gamma_change:1; 448 uint32_t bandwidth_change:1; 449 uint32_t clock_change:1; 450 uint32_t stereo_format_change:1; 451 uint32_t full_update:1; 452 } bits; 453 454 uint32_t raw; 455 }; 456 457 struct dc_plane_state { 458 struct dc_plane_address address; 459 struct dc_plane_flip_time time; 460 struct scaling_taps scaling_quality; 461 struct rect src_rect; 462 struct rect dst_rect; 463 struct rect clip_rect; 464 465 union plane_size plane_size; 466 union dc_tiling_info tiling_info; 467 468 struct dc_plane_dcc_param dcc; 469 470 struct dc_gamma *gamma_correction; 471 struct dc_transfer_func *in_transfer_func; 472 struct dc_bias_and_scale *bias_and_scale; 473 struct dc_csc_transform input_csc_color_matrix; 474 struct fixed31_32 coeff_reduction_factor; 475 uint32_t sdr_white_level; 476 477 // TODO: No longer used, remove 478 struct dc_hdr_static_metadata hdr_static_ctx; 479 480 enum dc_color_space color_space; 481 482 enum surface_pixel_format format; 483 enum dc_rotation_angle rotation; 484 enum plane_stereo_format stereo_format; 485 486 bool is_tiling_rotated; 487 bool per_pixel_alpha; 488 bool global_alpha; 489 int global_alpha_value; 490 bool visible; 491 bool flip_immediate; 492 bool horizontal_mirror; 493 494 union surface_update_flags update_flags; 495 /* private to DC core */ 496 struct dc_plane_status status; 497 struct dc_context *ctx; 498 499 /* private to dc_surface.c */ 500 enum dc_irq_source irq_source; 501 struct kref refcount; 502 }; 503 504 struct dc_plane_info { 505 union plane_size plane_size; 506 union dc_tiling_info tiling_info; 507 struct dc_plane_dcc_param dcc; 508 enum surface_pixel_format format; 509 enum dc_rotation_angle rotation; 510 enum plane_stereo_format stereo_format; 511 enum dc_color_space color_space; 512 unsigned int sdr_white_level; 513 bool horizontal_mirror; 514 bool visible; 515 bool per_pixel_alpha; 516 bool global_alpha; 517 int global_alpha_value; 518 bool input_csc_enabled; 519 }; 520 521 struct dc_scaling_info { 522 struct rect src_rect; 523 struct rect dst_rect; 524 struct rect clip_rect; 525 struct scaling_taps scaling_quality; 526 }; 527 528 struct dc_surface_update { 529 struct dc_plane_state *surface; 530 531 /* isr safe update parameters. null means no updates */ 532 const struct dc_flip_addrs *flip_addr; 533 const struct dc_plane_info *plane_info; 534 const struct dc_scaling_info *scaling_info; 535 536 /* following updates require alloc/sleep/spin that is not isr safe, 537 * null means no updates 538 */ 539 const struct dc_gamma *gamma; 540 const struct dc_transfer_func *in_transfer_func; 541 542 const struct dc_csc_transform *input_csc_color_matrix; 543 const struct fixed31_32 *coeff_reduction_factor; 544 }; 545 546 /* 547 * Create a new surface with default parameters; 548 */ 549 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 550 const struct dc_plane_status *dc_plane_get_status( 551 const struct dc_plane_state *plane_state); 552 553 void dc_plane_state_retain(struct dc_plane_state *plane_state); 554 void dc_plane_state_release(struct dc_plane_state *plane_state); 555 556 void dc_gamma_retain(struct dc_gamma *dc_gamma); 557 void dc_gamma_release(struct dc_gamma **dc_gamma); 558 struct dc_gamma *dc_create_gamma(void); 559 560 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 561 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 562 struct dc_transfer_func *dc_create_transfer_func(void); 563 564 /* 565 * This structure holds a surface address. There could be multiple addresses 566 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 567 * as frame durations and DCC format can also be set. 568 */ 569 struct dc_flip_addrs { 570 struct dc_plane_address address; 571 unsigned int flip_timestamp_in_us; 572 bool flip_immediate; 573 /* TODO: add flip duration for FreeSync */ 574 }; 575 576 bool dc_post_update_surfaces_to_stream( 577 struct dc *dc); 578 579 #include "dc_stream.h" 580 581 /* 582 * Structure to store surface/stream associations for validation 583 */ 584 struct dc_validation_set { 585 struct dc_stream_state *stream; 586 struct dc_plane_state *plane_states[MAX_SURFACES]; 587 uint8_t plane_count; 588 }; 589 590 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 591 592 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 593 594 enum dc_status dc_validate_global_state( 595 struct dc *dc, 596 struct dc_state *new_ctx); 597 598 599 void dc_resource_state_construct( 600 const struct dc *dc, 601 struct dc_state *dst_ctx); 602 603 void dc_resource_state_copy_construct( 604 const struct dc_state *src_ctx, 605 struct dc_state *dst_ctx); 606 607 void dc_resource_state_copy_construct_current( 608 const struct dc *dc, 609 struct dc_state *dst_ctx); 610 611 void dc_resource_state_destruct(struct dc_state *context); 612 613 /* 614 * TODO update to make it about validation sets 615 * Set up streams and links associated to drive sinks 616 * The streams parameter is an absolute set of all active streams. 617 * 618 * After this call: 619 * Phy, Encoder, Timing Generator are programmed and enabled. 620 * New streams are enabled with blank stream; no memory read. 621 */ 622 bool dc_commit_state(struct dc *dc, struct dc_state *context); 623 624 625 struct dc_state *dc_create_state(void); 626 void dc_retain_state(struct dc_state *context); 627 void dc_release_state(struct dc_state *context); 628 629 /******************************************************************************* 630 * Link Interfaces 631 ******************************************************************************/ 632 633 struct dpcd_caps { 634 union dpcd_rev dpcd_rev; 635 union max_lane_count max_ln_count; 636 union max_down_spread max_down_spread; 637 638 /* dongle type (DP converter, CV smart dongle) */ 639 enum display_dongle_type dongle_type; 640 /* Dongle's downstream count. */ 641 union sink_count sink_count; 642 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 643 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 644 struct dc_dongle_caps dongle_caps; 645 646 uint32_t sink_dev_id; 647 int8_t sink_dev_id_str[6]; 648 int8_t sink_hw_revision; 649 int8_t sink_fw_revision[2]; 650 651 uint32_t branch_dev_id; 652 int8_t branch_dev_name[6]; 653 int8_t branch_hw_revision; 654 int8_t branch_fw_revision[2]; 655 656 bool allow_invalid_MSA_timing_param; 657 bool panel_mode_edp; 658 bool dpcd_display_control_capable; 659 }; 660 661 #include "dc_link.h" 662 663 /******************************************************************************* 664 * Sink Interfaces - A sink corresponds to a display output device 665 ******************************************************************************/ 666 667 struct dc_container_id { 668 // 128bit GUID in binary form 669 unsigned char guid[16]; 670 // 8 byte port ID -> ELD.PortID 671 unsigned int portId[2]; 672 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 673 unsigned short manufacturerName; 674 // 2 byte product code -> ELD.ProductCode 675 unsigned short productCode; 676 }; 677 678 679 680 /* 681 * The sink structure contains EDID and other display device properties 682 */ 683 struct dc_sink { 684 enum signal_type sink_signal; 685 struct dc_edid dc_edid; /* raw edid */ 686 struct dc_edid_caps edid_caps; /* parse display caps */ 687 struct dc_container_id *dc_container_id; 688 uint32_t dongle_max_pix_clk; 689 void *priv; 690 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 691 bool converter_disable_audio; 692 693 /* private to DC core */ 694 struct dc_link *link; 695 struct dc_context *ctx; 696 697 uint32_t sink_id; 698 699 /* private to dc_sink.c */ 700 // refcount must be the last member in dc_sink, since we want the 701 // sink structure to be logically cloneable up to (but not including) 702 // refcount 703 struct kref refcount; 704 }; 705 706 void dc_sink_retain(struct dc_sink *sink); 707 void dc_sink_release(struct dc_sink *sink); 708 709 struct dc_sink_init_data { 710 enum signal_type sink_signal; 711 struct dc_link *link; 712 uint32_t dongle_max_pix_clk; 713 bool converter_disable_audio; 714 }; 715 716 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 717 718 /* Newer interfaces */ 719 struct dc_cursor { 720 struct dc_plane_address address; 721 struct dc_cursor_attributes attributes; 722 }; 723 724 725 /******************************************************************************* 726 * Interrupt interfaces 727 ******************************************************************************/ 728 enum dc_irq_source dc_interrupt_to_irq_source( 729 struct dc *dc, 730 uint32_t src_id, 731 uint32_t ext_id); 732 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 733 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 734 enum dc_irq_source dc_get_hpd_irq_source_at_index( 735 struct dc *dc, uint32_t link_index); 736 737 /******************************************************************************* 738 * Power Interfaces 739 ******************************************************************************/ 740 741 void dc_set_power_state( 742 struct dc *dc, 743 enum dc_acpi_cm_power_state power_state); 744 void dc_resume(struct dc *dc); 745 bool dc_is_dmcu_initialized(struct dc *dc); 746 747 #endif /* DC_INTERFACE_H_ */ 748