1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "dml/display_mode_lib.h" 40 41 #define DC_VER "3.1.38" 42 43 #define MAX_SURFACES 3 44 #define MAX_STREAMS 6 45 #define MAX_SINKS_PER_LINK 4 46 47 48 /******************************************************************************* 49 * Display Core Interfaces 50 ******************************************************************************/ 51 struct dmcu_version { 52 unsigned int date; 53 unsigned int month; 54 unsigned int year; 55 unsigned int interface_version; 56 }; 57 58 struct dc_versions { 59 const char *dc_ver; 60 struct dmcu_version dmcu_version; 61 }; 62 63 struct dc_caps { 64 uint32_t max_streams; 65 uint32_t max_links; 66 uint32_t max_audios; 67 uint32_t max_slave_planes; 68 uint32_t max_planes; 69 uint32_t max_downscale_ratio; 70 uint32_t i2c_speed_in_khz; 71 unsigned int max_cursor_size; 72 unsigned int max_video_width; 73 int linear_pitch_alignment; 74 bool dcc_const_color; 75 bool dynamic_audio; 76 bool is_apu; 77 bool dual_link_dvi; 78 }; 79 80 struct dc_dcc_surface_param { 81 struct dc_size surface_size; 82 enum surface_pixel_format format; 83 enum swizzle_mode_values swizzle_mode; 84 enum dc_scan_direction scan; 85 }; 86 87 struct dc_dcc_setting { 88 unsigned int max_compressed_blk_size; 89 unsigned int max_uncompressed_blk_size; 90 bool independent_64b_blks; 91 }; 92 93 struct dc_surface_dcc_cap { 94 union { 95 struct { 96 struct dc_dcc_setting rgb; 97 } grph; 98 99 struct { 100 struct dc_dcc_setting luma; 101 struct dc_dcc_setting chroma; 102 } video; 103 }; 104 105 bool capable; 106 bool const_color_support; 107 }; 108 109 struct dc_static_screen_events { 110 bool force_trigger; 111 bool cursor_update; 112 bool surface_update; 113 bool overlay_update; 114 }; 115 116 117 /* Surface update type is used by dc_update_surfaces_and_stream 118 * The update type is determined at the very beginning of the function based 119 * on parameters passed in and decides how much programming (or updating) is 120 * going to be done during the call. 121 * 122 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 123 * logical calculations or hardware register programming. This update MUST be 124 * ISR safe on windows. Currently fast update will only be used to flip surface 125 * address. 126 * 127 * UPDATE_TYPE_MED is used for slower updates which require significant hw 128 * re-programming however do not affect bandwidth consumption or clock 129 * requirements. At present, this is the level at which front end updates 130 * that do not require us to run bw_calcs happen. These are in/out transfer func 131 * updates, viewport offset changes, recout size changes and pixel depth changes. 132 * This update can be done at ISR, but we want to minimize how often this happens. 133 * 134 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 135 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 136 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 137 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 138 * a full update. This cannot be done at ISR level and should be a rare event. 139 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 140 * underscan we don't expect to see this call at all. 141 */ 142 143 enum surface_update_type { 144 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 145 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 146 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 147 }; 148 149 /* Forward declaration*/ 150 struct dc; 151 struct dc_plane_state; 152 struct dc_state; 153 154 155 struct dc_cap_funcs { 156 bool (*get_dcc_compression_cap)(const struct dc *dc, 157 const struct dc_dcc_surface_param *input, 158 struct dc_surface_dcc_cap *output); 159 }; 160 161 struct link_training_settings; 162 163 164 /* Structure to hold configuration flags set by dm at dc creation. */ 165 struct dc_config { 166 bool gpu_vm_support; 167 bool disable_disp_pll_sharing; 168 }; 169 170 enum dcc_option { 171 DCC_ENABLE = 0, 172 DCC_DISABLE = 1, 173 DCC_HALF_REQ_DISALBE = 2, 174 }; 175 176 enum pipe_split_policy { 177 MPC_SPLIT_DYNAMIC = 0, 178 MPC_SPLIT_AVOID = 1, 179 MPC_SPLIT_AVOID_MULT_DISP = 2, 180 }; 181 182 enum wm_report_mode { 183 WM_REPORT_DEFAULT = 0, 184 WM_REPORT_OVERRIDE = 1, 185 }; 186 187 struct dc_clocks { 188 int dispclk_khz; 189 int max_supported_dppclk_khz; 190 int dppclk_khz; 191 int dcfclk_khz; 192 int socclk_khz; 193 int dcfclk_deep_sleep_khz; 194 int fclk_khz; 195 }; 196 197 struct dc_debug { 198 bool surface_visual_confirm; 199 bool sanity_checks; 200 bool max_disp_clk; 201 bool surface_trace; 202 bool timing_trace; 203 bool clock_trace; 204 bool validation_trace; 205 206 /* stutter efficiency related */ 207 bool disable_stutter; 208 bool use_max_lb; 209 enum dcc_option disable_dcc; 210 enum pipe_split_policy pipe_split_policy; 211 bool force_single_disp_pipe_split; 212 bool voltage_align_fclk; 213 214 bool disable_dfs_bypass; 215 bool disable_dpp_power_gate; 216 bool disable_hubp_power_gate; 217 bool disable_pplib_wm_range; 218 enum wm_report_mode pplib_wm_report_mode; 219 unsigned int min_disp_clk_khz; 220 int sr_exit_time_dpm0_ns; 221 int sr_enter_plus_exit_time_dpm0_ns; 222 int sr_exit_time_ns; 223 int sr_enter_plus_exit_time_ns; 224 int urgent_latency_ns; 225 int percent_of_ideal_drambw; 226 int dram_clock_change_latency_ns; 227 int always_scale; 228 bool disable_pplib_clock_request; 229 bool disable_clock_gate; 230 bool disable_dmcu; 231 bool disable_psr; 232 bool force_abm_enable; 233 bool disable_hbup_pg; 234 bool disable_dpp_pg; 235 bool disable_stereo_support; 236 bool vsr_support; 237 bool performance_trace; 238 bool az_endpoint_mute_only; 239 bool always_use_regamma; 240 bool p010_mpo_support; 241 }; 242 struct dc_state; 243 struct resource_pool; 244 struct dce_hwseq; 245 struct dc { 246 struct dc_versions versions; 247 struct dc_caps caps; 248 struct dc_cap_funcs cap_funcs; 249 struct dc_config config; 250 struct dc_debug debug; 251 252 struct dc_context *ctx; 253 254 uint8_t link_count; 255 struct dc_link *links[MAX_PIPES * 2]; 256 257 struct dc_state *current_state; 258 struct resource_pool *res_pool; 259 260 /* Display Engine Clock levels */ 261 struct dm_pp_clock_levels sclk_lvls; 262 263 /* Inputs into BW and WM calculations. */ 264 struct bw_calcs_dceip *bw_dceip; 265 struct bw_calcs_vbios *bw_vbios; 266 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 267 struct dcn_soc_bounding_box *dcn_soc; 268 struct dcn_ip_params *dcn_ip; 269 struct display_mode_lib dml; 270 #endif 271 272 /* HW functions */ 273 struct hw_sequencer_funcs hwss; 274 struct dce_hwseq *hwseq; 275 276 /* temp store of dm_pp_display_configuration 277 * to compare to see if display config changed 278 */ 279 struct dm_pp_display_configuration prev_display_config; 280 281 bool optimized_required; 282 283 bool apply_edp_fast_boot_optimization; 284 285 /* FBC compressor */ 286 #if defined(CONFIG_DRM_AMD_DC_FBC) 287 struct compressor *fbc_compressor; 288 #endif 289 }; 290 291 enum frame_buffer_mode { 292 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 293 FRAME_BUFFER_MODE_ZFB_ONLY, 294 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 295 } ; 296 297 struct dchub_init_data { 298 int64_t zfb_phys_addr_base; 299 int64_t zfb_mc_base_addr; 300 uint64_t zfb_size_in_byte; 301 enum frame_buffer_mode fb_mode; 302 bool dchub_initialzied; 303 bool dchub_info_valid; 304 }; 305 306 struct dc_init_data { 307 struct hw_asic_id asic_id; 308 void *driver; /* ctx */ 309 struct cgs_device *cgs_device; 310 311 int num_virtual_links; 312 /* 313 * If 'vbios_override' not NULL, it will be called instead 314 * of the real VBIOS. Intended use is Diagnostics on FPGA. 315 */ 316 struct dc_bios *vbios_override; 317 enum dce_environment dce_environment; 318 319 struct dc_config flags; 320 uint32_t log_mask; 321 }; 322 323 struct dc *dc_create(const struct dc_init_data *init_params); 324 325 void dc_destroy(struct dc **dc); 326 327 /******************************************************************************* 328 * Surface Interfaces 329 ******************************************************************************/ 330 331 enum { 332 TRANSFER_FUNC_POINTS = 1025 333 }; 334 335 // Moved here from color module for linux 336 enum color_transfer_func { 337 transfer_func_unknown, 338 transfer_func_srgb, 339 transfer_func_bt709, 340 transfer_func_pq2084, 341 transfer_func_pq2084_interim, 342 transfer_func_linear_0_1, 343 transfer_func_linear_0_125, 344 transfer_func_dolbyvision, 345 transfer_func_gamma_22, 346 transfer_func_gamma_26 347 }; 348 349 struct dc_hdr_static_metadata { 350 /* display chromaticities and white point in units of 0.00001 */ 351 unsigned int chromaticity_green_x; 352 unsigned int chromaticity_green_y; 353 unsigned int chromaticity_blue_x; 354 unsigned int chromaticity_blue_y; 355 unsigned int chromaticity_red_x; 356 unsigned int chromaticity_red_y; 357 unsigned int chromaticity_white_point_x; 358 unsigned int chromaticity_white_point_y; 359 360 uint32_t min_luminance; 361 uint32_t max_luminance; 362 uint32_t maximum_content_light_level; 363 uint32_t maximum_frame_average_light_level; 364 365 bool hdr_supported; 366 bool is_hdr; 367 }; 368 369 enum dc_transfer_func_type { 370 TF_TYPE_PREDEFINED, 371 TF_TYPE_DISTRIBUTED_POINTS, 372 TF_TYPE_BYPASS, 373 }; 374 375 struct dc_transfer_func_distributed_points { 376 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 377 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 378 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 379 380 uint16_t end_exponent; 381 uint16_t x_point_at_y1_red; 382 uint16_t x_point_at_y1_green; 383 uint16_t x_point_at_y1_blue; 384 }; 385 386 enum dc_transfer_func_predefined { 387 TRANSFER_FUNCTION_SRGB, 388 TRANSFER_FUNCTION_BT709, 389 TRANSFER_FUNCTION_PQ, 390 TRANSFER_FUNCTION_LINEAR, 391 TRANSFER_FUNCTION_UNITY, 392 }; 393 394 struct dc_transfer_func { 395 struct kref refcount; 396 struct dc_transfer_func_distributed_points tf_pts; 397 enum dc_transfer_func_type type; 398 enum dc_transfer_func_predefined tf; 399 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 400 uint32_t sdr_ref_white_level; 401 struct dc_context *ctx; 402 }; 403 404 /* 405 * This structure is filled in by dc_surface_get_status and contains 406 * the last requested address and the currently active address so the called 407 * can determine if there are any outstanding flips 408 */ 409 struct dc_plane_status { 410 struct dc_plane_address requested_address; 411 struct dc_plane_address current_address; 412 bool is_flip_pending; 413 bool is_right_eye; 414 }; 415 416 union surface_update_flags { 417 418 struct { 419 /* Medium updates */ 420 uint32_t dcc_change:1; 421 uint32_t color_space_change:1; 422 uint32_t input_tf_change:1; 423 uint32_t horizontal_mirror_change:1; 424 uint32_t per_pixel_alpha_change:1; 425 uint32_t rotation_change:1; 426 uint32_t swizzle_change:1; 427 uint32_t scaling_change:1; 428 uint32_t position_change:1; 429 uint32_t in_transfer_func_change:1; 430 uint32_t input_csc_change:1; 431 uint32_t output_tf_change:1; 432 uint32_t pixel_format_change:1; 433 434 /* Full updates */ 435 uint32_t new_plane:1; 436 uint32_t bpp_change:1; 437 uint32_t gamma_change:1; 438 uint32_t bandwidth_change:1; 439 uint32_t clock_change:1; 440 uint32_t stereo_format_change:1; 441 uint32_t full_update:1; 442 } bits; 443 444 uint32_t raw; 445 }; 446 447 struct dc_plane_state { 448 struct dc_plane_address address; 449 struct dc_plane_flip_time time; 450 struct scaling_taps scaling_quality; 451 struct rect src_rect; 452 struct rect dst_rect; 453 struct rect clip_rect; 454 455 union plane_size plane_size; 456 union dc_tiling_info tiling_info; 457 458 struct dc_plane_dcc_param dcc; 459 460 struct dc_gamma *gamma_correction; 461 struct dc_transfer_func *in_transfer_func; 462 struct dc_bias_and_scale *bias_and_scale; 463 struct csc_transform input_csc_color_matrix; 464 struct fixed31_32 coeff_reduction_factor; 465 uint32_t sdr_white_level; 466 467 // TODO: No longer used, remove 468 struct dc_hdr_static_metadata hdr_static_ctx; 469 470 enum dc_color_space color_space; 471 enum color_transfer_func input_tf; 472 473 enum surface_pixel_format format; 474 enum dc_rotation_angle rotation; 475 enum plane_stereo_format stereo_format; 476 477 bool is_tiling_rotated; 478 bool per_pixel_alpha; 479 bool visible; 480 bool flip_immediate; 481 bool horizontal_mirror; 482 483 union surface_update_flags update_flags; 484 /* private to DC core */ 485 struct dc_plane_status status; 486 struct dc_context *ctx; 487 488 /* private to dc_surface.c */ 489 enum dc_irq_source irq_source; 490 struct kref refcount; 491 }; 492 493 struct dc_plane_info { 494 union plane_size plane_size; 495 union dc_tiling_info tiling_info; 496 struct dc_plane_dcc_param dcc; 497 enum surface_pixel_format format; 498 enum dc_rotation_angle rotation; 499 enum plane_stereo_format stereo_format; 500 enum dc_color_space color_space; 501 enum color_transfer_func input_tf; 502 unsigned int sdr_white_level; 503 bool horizontal_mirror; 504 bool visible; 505 bool per_pixel_alpha; 506 bool input_csc_enabled; 507 }; 508 509 struct dc_scaling_info { 510 struct rect src_rect; 511 struct rect dst_rect; 512 struct rect clip_rect; 513 struct scaling_taps scaling_quality; 514 }; 515 516 struct dc_surface_update { 517 struct dc_plane_state *surface; 518 519 /* isr safe update parameters. null means no updates */ 520 struct dc_flip_addrs *flip_addr; 521 struct dc_plane_info *plane_info; 522 struct dc_scaling_info *scaling_info; 523 524 /* following updates require alloc/sleep/spin that is not isr safe, 525 * null means no updates 526 */ 527 struct dc_gamma *gamma; 528 enum color_transfer_func color_input_tf; 529 struct dc_transfer_func *in_transfer_func; 530 531 struct csc_transform *input_csc_color_matrix; 532 struct fixed31_32 *coeff_reduction_factor; 533 }; 534 535 /* 536 * Create a new surface with default parameters; 537 */ 538 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 539 const struct dc_plane_status *dc_plane_get_status( 540 const struct dc_plane_state *plane_state); 541 542 void dc_plane_state_retain(struct dc_plane_state *plane_state); 543 void dc_plane_state_release(struct dc_plane_state *plane_state); 544 545 void dc_gamma_retain(struct dc_gamma *dc_gamma); 546 void dc_gamma_release(struct dc_gamma **dc_gamma); 547 struct dc_gamma *dc_create_gamma(void); 548 549 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 550 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 551 struct dc_transfer_func *dc_create_transfer_func(void); 552 553 /* 554 * This structure holds a surface address. There could be multiple addresses 555 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 556 * as frame durations and DCC format can also be set. 557 */ 558 struct dc_flip_addrs { 559 struct dc_plane_address address; 560 unsigned int flip_timestamp_in_us; 561 bool flip_immediate; 562 /* TODO: add flip duration for FreeSync */ 563 }; 564 565 bool dc_post_update_surfaces_to_stream( 566 struct dc *dc); 567 568 #include "dc_stream.h" 569 570 /* 571 * Structure to store surface/stream associations for validation 572 */ 573 struct dc_validation_set { 574 struct dc_stream_state *stream; 575 struct dc_plane_state *plane_states[MAX_SURFACES]; 576 uint8_t plane_count; 577 }; 578 579 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 580 581 enum dc_status dc_validate_global_state( 582 struct dc *dc, 583 struct dc_state *new_ctx); 584 585 586 void dc_resource_state_construct( 587 const struct dc *dc, 588 struct dc_state *dst_ctx); 589 590 void dc_resource_state_copy_construct( 591 const struct dc_state *src_ctx, 592 struct dc_state *dst_ctx); 593 594 void dc_resource_state_copy_construct_current( 595 const struct dc *dc, 596 struct dc_state *dst_ctx); 597 598 void dc_resource_state_destruct(struct dc_state *context); 599 600 /* 601 * TODO update to make it about validation sets 602 * Set up streams and links associated to drive sinks 603 * The streams parameter is an absolute set of all active streams. 604 * 605 * After this call: 606 * Phy, Encoder, Timing Generator are programmed and enabled. 607 * New streams are enabled with blank stream; no memory read. 608 */ 609 bool dc_commit_state(struct dc *dc, struct dc_state *context); 610 611 612 struct dc_state *dc_create_state(void); 613 void dc_retain_state(struct dc_state *context); 614 void dc_release_state(struct dc_state *context); 615 616 /******************************************************************************* 617 * Link Interfaces 618 ******************************************************************************/ 619 620 struct dpcd_caps { 621 union dpcd_rev dpcd_rev; 622 union max_lane_count max_ln_count; 623 union max_down_spread max_down_spread; 624 625 /* dongle type (DP converter, CV smart dongle) */ 626 enum display_dongle_type dongle_type; 627 /* Dongle's downstream count. */ 628 union sink_count sink_count; 629 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 630 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 631 struct dc_dongle_caps dongle_caps; 632 633 uint32_t sink_dev_id; 634 uint32_t branch_dev_id; 635 int8_t branch_dev_name[6]; 636 int8_t branch_hw_revision; 637 638 bool allow_invalid_MSA_timing_param; 639 bool panel_mode_edp; 640 bool dpcd_display_control_capable; 641 }; 642 643 #include "dc_link.h" 644 645 /******************************************************************************* 646 * Sink Interfaces - A sink corresponds to a display output device 647 ******************************************************************************/ 648 649 struct dc_container_id { 650 // 128bit GUID in binary form 651 unsigned char guid[16]; 652 // 8 byte port ID -> ELD.PortID 653 unsigned int portId[2]; 654 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 655 unsigned short manufacturerName; 656 // 2 byte product code -> ELD.ProductCode 657 unsigned short productCode; 658 }; 659 660 661 662 /* 663 * The sink structure contains EDID and other display device properties 664 */ 665 struct dc_sink { 666 enum signal_type sink_signal; 667 struct dc_edid dc_edid; /* raw edid */ 668 struct dc_edid_caps edid_caps; /* parse display caps */ 669 struct dc_container_id *dc_container_id; 670 uint32_t dongle_max_pix_clk; 671 void *priv; 672 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 673 bool converter_disable_audio; 674 675 /* private to DC core */ 676 struct dc_link *link; 677 struct dc_context *ctx; 678 679 /* private to dc_sink.c */ 680 struct kref refcount; 681 682 }; 683 684 void dc_sink_retain(struct dc_sink *sink); 685 void dc_sink_release(struct dc_sink *sink); 686 687 struct dc_sink_init_data { 688 enum signal_type sink_signal; 689 struct dc_link *link; 690 uint32_t dongle_max_pix_clk; 691 bool converter_disable_audio; 692 }; 693 694 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 695 696 /* Newer interfaces */ 697 struct dc_cursor { 698 struct dc_plane_address address; 699 struct dc_cursor_attributes attributes; 700 }; 701 702 /******************************************************************************* 703 * Interrupt interfaces 704 ******************************************************************************/ 705 enum dc_irq_source dc_interrupt_to_irq_source( 706 struct dc *dc, 707 uint32_t src_id, 708 uint32_t ext_id); 709 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 710 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 711 enum dc_irq_source dc_get_hpd_irq_source_at_index( 712 struct dc *dc, uint32_t link_index); 713 714 /******************************************************************************* 715 * Power Interfaces 716 ******************************************************************************/ 717 718 void dc_set_power_state( 719 struct dc *dc, 720 enum dc_acpi_cm_power_state power_state); 721 void dc_resume(struct dc *dc); 722 723 #endif /* DC_INTERFACE_H_ */ 724