1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "dml/display_mode_lib.h" 40 41 #define DC_VER "3.2.04" 42 43 #define MAX_SURFACES 3 44 #define MAX_STREAMS 6 45 #define MAX_SINKS_PER_LINK 4 46 47 /******************************************************************************* 48 * Display Core Interfaces 49 ******************************************************************************/ 50 struct dmcu_version { 51 unsigned int date; 52 unsigned int month; 53 unsigned int year; 54 unsigned int interface_version; 55 }; 56 57 struct dc_versions { 58 const char *dc_ver; 59 struct dmcu_version dmcu_version; 60 }; 61 62 struct dc_caps { 63 uint32_t max_streams; 64 uint32_t max_links; 65 uint32_t max_audios; 66 uint32_t max_slave_planes; 67 uint32_t max_planes; 68 uint32_t max_downscale_ratio; 69 uint32_t i2c_speed_in_khz; 70 uint32_t dmdata_alloc_size; 71 unsigned int max_cursor_size; 72 unsigned int max_video_width; 73 int linear_pitch_alignment; 74 bool dcc_const_color; 75 bool dynamic_audio; 76 bool is_apu; 77 bool dual_link_dvi; 78 bool post_blend_color_processing; 79 bool force_dp_tps4_for_cp2520; 80 bool disable_dp_clk_share; 81 bool psp_setup_panel_mode; 82 }; 83 84 struct dc_dcc_surface_param { 85 struct dc_size surface_size; 86 enum surface_pixel_format format; 87 enum swizzle_mode_values swizzle_mode; 88 enum dc_scan_direction scan; 89 }; 90 91 struct dc_dcc_setting { 92 unsigned int max_compressed_blk_size; 93 unsigned int max_uncompressed_blk_size; 94 bool independent_64b_blks; 95 }; 96 97 struct dc_surface_dcc_cap { 98 union { 99 struct { 100 struct dc_dcc_setting rgb; 101 } grph; 102 103 struct { 104 struct dc_dcc_setting luma; 105 struct dc_dcc_setting chroma; 106 } video; 107 }; 108 109 bool capable; 110 bool const_color_support; 111 }; 112 113 struct dc_static_screen_events { 114 bool force_trigger; 115 bool cursor_update; 116 bool surface_update; 117 bool overlay_update; 118 }; 119 120 121 /* Surface update type is used by dc_update_surfaces_and_stream 122 * The update type is determined at the very beginning of the function based 123 * on parameters passed in and decides how much programming (or updating) is 124 * going to be done during the call. 125 * 126 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 127 * logical calculations or hardware register programming. This update MUST be 128 * ISR safe on windows. Currently fast update will only be used to flip surface 129 * address. 130 * 131 * UPDATE_TYPE_MED is used for slower updates which require significant hw 132 * re-programming however do not affect bandwidth consumption or clock 133 * requirements. At present, this is the level at which front end updates 134 * that do not require us to run bw_calcs happen. These are in/out transfer func 135 * updates, viewport offset changes, recout size changes and pixel depth changes. 136 * This update can be done at ISR, but we want to minimize how often this happens. 137 * 138 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 139 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 140 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 141 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 142 * a full update. This cannot be done at ISR level and should be a rare event. 143 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 144 * underscan we don't expect to see this call at all. 145 */ 146 147 enum surface_update_type { 148 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 149 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 150 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 151 }; 152 153 /* Forward declaration*/ 154 struct dc; 155 struct dc_plane_state; 156 struct dc_state; 157 158 159 struct dc_cap_funcs { 160 bool (*get_dcc_compression_cap)(const struct dc *dc, 161 const struct dc_dcc_surface_param *input, 162 struct dc_surface_dcc_cap *output); 163 }; 164 165 struct link_training_settings; 166 167 168 /* Structure to hold configuration flags set by dm at dc creation. */ 169 struct dc_config { 170 bool gpu_vm_support; 171 bool disable_disp_pll_sharing; 172 bool fbc_support; 173 }; 174 175 enum visual_confirm { 176 VISUAL_CONFIRM_DISABLE = 0, 177 VISUAL_CONFIRM_SURFACE = 1, 178 VISUAL_CONFIRM_HDR = 2, 179 }; 180 181 enum dcc_option { 182 DCC_ENABLE = 0, 183 DCC_DISABLE = 1, 184 DCC_HALF_REQ_DISALBE = 2, 185 }; 186 187 enum pipe_split_policy { 188 MPC_SPLIT_DYNAMIC = 0, 189 MPC_SPLIT_AVOID = 1, 190 MPC_SPLIT_AVOID_MULT_DISP = 2, 191 }; 192 193 enum wm_report_mode { 194 WM_REPORT_DEFAULT = 0, 195 WM_REPORT_OVERRIDE = 1, 196 }; 197 198 /* 199 * For any clocks that may differ per pipe 200 * only the max is stored in this structure 201 */ 202 struct dc_clocks { 203 int dispclk_khz; 204 int max_supported_dppclk_khz; 205 int dppclk_khz; 206 int dcfclk_khz; 207 int socclk_khz; 208 int dcfclk_deep_sleep_khz; 209 int fclk_khz; 210 int phyclk_khz; 211 int dramclk_khz; 212 }; 213 214 struct dc_debug_options { 215 enum visual_confirm visual_confirm; 216 bool sanity_checks; 217 bool max_disp_clk; 218 bool surface_trace; 219 bool timing_trace; 220 bool clock_trace; 221 bool validation_trace; 222 bool bandwidth_calcs_trace; 223 int max_downscale_src_width; 224 225 /* stutter efficiency related */ 226 bool disable_stutter; 227 bool use_max_lb; 228 enum dcc_option disable_dcc; 229 enum pipe_split_policy pipe_split_policy; 230 bool force_single_disp_pipe_split; 231 bool voltage_align_fclk; 232 233 bool disable_dfs_bypass; 234 bool disable_dpp_power_gate; 235 bool disable_hubp_power_gate; 236 bool disable_pplib_wm_range; 237 enum wm_report_mode pplib_wm_report_mode; 238 unsigned int min_disp_clk_khz; 239 int sr_exit_time_dpm0_ns; 240 int sr_enter_plus_exit_time_dpm0_ns; 241 int sr_exit_time_ns; 242 int sr_enter_plus_exit_time_ns; 243 int urgent_latency_ns; 244 int percent_of_ideal_drambw; 245 int dram_clock_change_latency_ns; 246 bool optimized_watermark; 247 int always_scale; 248 bool disable_pplib_clock_request; 249 bool disable_clock_gate; 250 bool disable_dmcu; 251 bool disable_psr; 252 bool force_abm_enable; 253 bool disable_stereo_support; 254 bool vsr_support; 255 bool performance_trace; 256 bool az_endpoint_mute_only; 257 bool always_use_regamma; 258 bool p010_mpo_support; 259 bool recovery_enabled; 260 bool avoid_vbios_exec_table; 261 bool scl_reset_length10; 262 bool hdmi20_disable; 263 bool skip_detection_link_training; 264 }; 265 266 struct dc_debug_data { 267 uint32_t ltFailCount; 268 uint32_t i2cErrorCount; 269 uint32_t auxErrorCount; 270 }; 271 272 273 struct dc_state; 274 struct resource_pool; 275 struct dce_hwseq; 276 struct dc { 277 struct dc_versions versions; 278 struct dc_caps caps; 279 struct dc_cap_funcs cap_funcs; 280 struct dc_config config; 281 struct dc_debug_options debug; 282 struct dc_context *ctx; 283 284 uint8_t link_count; 285 struct dc_link *links[MAX_PIPES * 2]; 286 287 struct dc_state *current_state; 288 struct resource_pool *res_pool; 289 290 /* Display Engine Clock levels */ 291 struct dm_pp_clock_levels sclk_lvls; 292 293 /* Inputs into BW and WM calculations. */ 294 struct bw_calcs_dceip *bw_dceip; 295 struct bw_calcs_vbios *bw_vbios; 296 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 297 struct dcn_soc_bounding_box *dcn_soc; 298 struct dcn_ip_params *dcn_ip; 299 struct display_mode_lib dml; 300 #endif 301 302 /* HW functions */ 303 struct hw_sequencer_funcs hwss; 304 struct dce_hwseq *hwseq; 305 306 bool optimized_required; 307 308 /* FBC compressor */ 309 struct compressor *fbc_compressor; 310 311 struct dc_debug_data debug_data; 312 313 const char *build_id; 314 }; 315 316 enum frame_buffer_mode { 317 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 318 FRAME_BUFFER_MODE_ZFB_ONLY, 319 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 320 } ; 321 322 struct dchub_init_data { 323 int64_t zfb_phys_addr_base; 324 int64_t zfb_mc_base_addr; 325 uint64_t zfb_size_in_byte; 326 enum frame_buffer_mode fb_mode; 327 bool dchub_initialzied; 328 bool dchub_info_valid; 329 }; 330 331 struct dc_init_data { 332 struct hw_asic_id asic_id; 333 void *driver; /* ctx */ 334 struct cgs_device *cgs_device; 335 336 int num_virtual_links; 337 /* 338 * If 'vbios_override' not NULL, it will be called instead 339 * of the real VBIOS. Intended use is Diagnostics on FPGA. 340 */ 341 struct dc_bios *vbios_override; 342 enum dce_environment dce_environment; 343 344 struct dc_config flags; 345 uint32_t log_mask; 346 }; 347 348 struct dc *dc_create(const struct dc_init_data *init_params); 349 350 void dc_destroy(struct dc **dc); 351 352 /******************************************************************************* 353 * Surface Interfaces 354 ******************************************************************************/ 355 356 enum { 357 TRANSFER_FUNC_POINTS = 1025 358 }; 359 360 struct dc_hdr_static_metadata { 361 /* display chromaticities and white point in units of 0.00001 */ 362 unsigned int chromaticity_green_x; 363 unsigned int chromaticity_green_y; 364 unsigned int chromaticity_blue_x; 365 unsigned int chromaticity_blue_y; 366 unsigned int chromaticity_red_x; 367 unsigned int chromaticity_red_y; 368 unsigned int chromaticity_white_point_x; 369 unsigned int chromaticity_white_point_y; 370 371 uint32_t min_luminance; 372 uint32_t max_luminance; 373 uint32_t maximum_content_light_level; 374 uint32_t maximum_frame_average_light_level; 375 }; 376 377 enum dc_transfer_func_type { 378 TF_TYPE_PREDEFINED, 379 TF_TYPE_DISTRIBUTED_POINTS, 380 TF_TYPE_BYPASS, 381 TF_TYPE_HWPWL 382 }; 383 384 struct dc_transfer_func_distributed_points { 385 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 386 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 387 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 388 389 uint16_t end_exponent; 390 uint16_t x_point_at_y1_red; 391 uint16_t x_point_at_y1_green; 392 uint16_t x_point_at_y1_blue; 393 }; 394 395 enum dc_transfer_func_predefined { 396 TRANSFER_FUNCTION_SRGB, 397 TRANSFER_FUNCTION_BT709, 398 TRANSFER_FUNCTION_PQ, 399 TRANSFER_FUNCTION_LINEAR, 400 TRANSFER_FUNCTION_UNITY, 401 TRANSFER_FUNCTION_HLG, 402 TRANSFER_FUNCTION_HLG12, 403 TRANSFER_FUNCTION_GAMMA22 404 }; 405 406 struct dc_transfer_func { 407 struct kref refcount; 408 enum dc_transfer_func_type type; 409 enum dc_transfer_func_predefined tf; 410 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 411 uint32_t sdr_ref_white_level; 412 struct dc_context *ctx; 413 union { 414 struct pwl_params pwl; 415 struct dc_transfer_func_distributed_points tf_pts; 416 }; 417 }; 418 419 /* 420 * This structure is filled in by dc_surface_get_status and contains 421 * the last requested address and the currently active address so the called 422 * can determine if there are any outstanding flips 423 */ 424 struct dc_plane_status { 425 struct dc_plane_address requested_address; 426 struct dc_plane_address current_address; 427 bool is_flip_pending; 428 bool is_right_eye; 429 }; 430 431 union surface_update_flags { 432 433 struct { 434 /* Medium updates */ 435 uint32_t dcc_change:1; 436 uint32_t color_space_change:1; 437 uint32_t horizontal_mirror_change:1; 438 uint32_t per_pixel_alpha_change:1; 439 uint32_t global_alpha_change:1; 440 uint32_t rotation_change:1; 441 uint32_t swizzle_change:1; 442 uint32_t scaling_change:1; 443 uint32_t position_change:1; 444 uint32_t in_transfer_func_change:1; 445 uint32_t input_csc_change:1; 446 uint32_t coeff_reduction_change:1; 447 uint32_t output_tf_change:1; 448 uint32_t pixel_format_change:1; 449 450 /* Full updates */ 451 uint32_t new_plane:1; 452 uint32_t bpp_change:1; 453 uint32_t gamma_change:1; 454 uint32_t bandwidth_change:1; 455 uint32_t clock_change:1; 456 uint32_t stereo_format_change:1; 457 uint32_t full_update:1; 458 } bits; 459 460 uint32_t raw; 461 }; 462 463 struct dc_plane_state { 464 struct dc_plane_address address; 465 struct dc_plane_flip_time time; 466 struct scaling_taps scaling_quality; 467 struct rect src_rect; 468 struct rect dst_rect; 469 struct rect clip_rect; 470 471 union plane_size plane_size; 472 union dc_tiling_info tiling_info; 473 474 struct dc_plane_dcc_param dcc; 475 476 struct dc_gamma *gamma_correction; 477 struct dc_transfer_func *in_transfer_func; 478 struct dc_bias_and_scale *bias_and_scale; 479 struct dc_csc_transform input_csc_color_matrix; 480 struct fixed31_32 coeff_reduction_factor; 481 uint32_t sdr_white_level; 482 483 // TODO: No longer used, remove 484 struct dc_hdr_static_metadata hdr_static_ctx; 485 486 enum dc_color_space color_space; 487 488 enum surface_pixel_format format; 489 enum dc_rotation_angle rotation; 490 enum plane_stereo_format stereo_format; 491 492 bool is_tiling_rotated; 493 bool per_pixel_alpha; 494 bool global_alpha; 495 int global_alpha_value; 496 bool visible; 497 bool flip_immediate; 498 bool horizontal_mirror; 499 500 union surface_update_flags update_flags; 501 /* private to DC core */ 502 struct dc_plane_status status; 503 struct dc_context *ctx; 504 505 /* private to dc_surface.c */ 506 enum dc_irq_source irq_source; 507 struct kref refcount; 508 }; 509 510 struct dc_plane_info { 511 union plane_size plane_size; 512 union dc_tiling_info tiling_info; 513 struct dc_plane_dcc_param dcc; 514 enum surface_pixel_format format; 515 enum dc_rotation_angle rotation; 516 enum plane_stereo_format stereo_format; 517 enum dc_color_space color_space; 518 unsigned int sdr_white_level; 519 bool horizontal_mirror; 520 bool visible; 521 bool per_pixel_alpha; 522 bool global_alpha; 523 int global_alpha_value; 524 bool input_csc_enabled; 525 }; 526 527 struct dc_scaling_info { 528 struct rect src_rect; 529 struct rect dst_rect; 530 struct rect clip_rect; 531 struct scaling_taps scaling_quality; 532 }; 533 534 struct dc_surface_update { 535 struct dc_plane_state *surface; 536 537 /* isr safe update parameters. null means no updates */ 538 const struct dc_flip_addrs *flip_addr; 539 const struct dc_plane_info *plane_info; 540 const struct dc_scaling_info *scaling_info; 541 542 /* following updates require alloc/sleep/spin that is not isr safe, 543 * null means no updates 544 */ 545 const struct dc_gamma *gamma; 546 const struct dc_transfer_func *in_transfer_func; 547 548 const struct dc_csc_transform *input_csc_color_matrix; 549 const struct fixed31_32 *coeff_reduction_factor; 550 }; 551 552 /* 553 * Create a new surface with default parameters; 554 */ 555 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 556 const struct dc_plane_status *dc_plane_get_status( 557 const struct dc_plane_state *plane_state); 558 559 void dc_plane_state_retain(struct dc_plane_state *plane_state); 560 void dc_plane_state_release(struct dc_plane_state *plane_state); 561 562 void dc_gamma_retain(struct dc_gamma *dc_gamma); 563 void dc_gamma_release(struct dc_gamma **dc_gamma); 564 struct dc_gamma *dc_create_gamma(void); 565 566 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 567 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 568 struct dc_transfer_func *dc_create_transfer_func(void); 569 570 /* 571 * This structure holds a surface address. There could be multiple addresses 572 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 573 * as frame durations and DCC format can also be set. 574 */ 575 struct dc_flip_addrs { 576 struct dc_plane_address address; 577 unsigned int flip_timestamp_in_us; 578 bool flip_immediate; 579 /* TODO: add flip duration for FreeSync */ 580 }; 581 582 bool dc_post_update_surfaces_to_stream( 583 struct dc *dc); 584 585 #include "dc_stream.h" 586 587 /* 588 * Structure to store surface/stream associations for validation 589 */ 590 struct dc_validation_set { 591 struct dc_stream_state *stream; 592 struct dc_plane_state *plane_states[MAX_SURFACES]; 593 uint8_t plane_count; 594 }; 595 596 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 597 598 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 599 600 enum dc_status dc_validate_global_state( 601 struct dc *dc, 602 struct dc_state *new_ctx); 603 604 605 void dc_resource_state_construct( 606 const struct dc *dc, 607 struct dc_state *dst_ctx); 608 609 void dc_resource_state_copy_construct( 610 const struct dc_state *src_ctx, 611 struct dc_state *dst_ctx); 612 613 void dc_resource_state_copy_construct_current( 614 const struct dc *dc, 615 struct dc_state *dst_ctx); 616 617 void dc_resource_state_destruct(struct dc_state *context); 618 619 /* 620 * TODO update to make it about validation sets 621 * Set up streams and links associated to drive sinks 622 * The streams parameter is an absolute set of all active streams. 623 * 624 * After this call: 625 * Phy, Encoder, Timing Generator are programmed and enabled. 626 * New streams are enabled with blank stream; no memory read. 627 */ 628 bool dc_commit_state(struct dc *dc, struct dc_state *context); 629 630 631 struct dc_state *dc_create_state(void); 632 void dc_retain_state(struct dc_state *context); 633 void dc_release_state(struct dc_state *context); 634 635 /******************************************************************************* 636 * Link Interfaces 637 ******************************************************************************/ 638 639 struct dpcd_caps { 640 union dpcd_rev dpcd_rev; 641 union max_lane_count max_ln_count; 642 union max_down_spread max_down_spread; 643 644 /* dongle type (DP converter, CV smart dongle) */ 645 enum display_dongle_type dongle_type; 646 /* Dongle's downstream count. */ 647 union sink_count sink_count; 648 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 649 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 650 struct dc_dongle_caps dongle_caps; 651 652 uint32_t sink_dev_id; 653 int8_t sink_dev_id_str[6]; 654 int8_t sink_hw_revision; 655 int8_t sink_fw_revision[2]; 656 657 uint32_t branch_dev_id; 658 int8_t branch_dev_name[6]; 659 int8_t branch_hw_revision; 660 int8_t branch_fw_revision[2]; 661 662 bool allow_invalid_MSA_timing_param; 663 bool panel_mode_edp; 664 bool dpcd_display_control_capable; 665 }; 666 667 #include "dc_link.h" 668 669 /******************************************************************************* 670 * Sink Interfaces - A sink corresponds to a display output device 671 ******************************************************************************/ 672 673 struct dc_container_id { 674 // 128bit GUID in binary form 675 unsigned char guid[16]; 676 // 8 byte port ID -> ELD.PortID 677 unsigned int portId[2]; 678 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 679 unsigned short manufacturerName; 680 // 2 byte product code -> ELD.ProductCode 681 unsigned short productCode; 682 }; 683 684 685 686 /* 687 * The sink structure contains EDID and other display device properties 688 */ 689 struct dc_sink { 690 enum signal_type sink_signal; 691 struct dc_edid dc_edid; /* raw edid */ 692 struct dc_edid_caps edid_caps; /* parse display caps */ 693 struct dc_container_id *dc_container_id; 694 uint32_t dongle_max_pix_clk; 695 void *priv; 696 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 697 bool converter_disable_audio; 698 699 /* private to DC core */ 700 struct dc_link *link; 701 struct dc_context *ctx; 702 703 uint32_t sink_id; 704 705 /* private to dc_sink.c */ 706 // refcount must be the last member in dc_sink, since we want the 707 // sink structure to be logically cloneable up to (but not including) 708 // refcount 709 struct kref refcount; 710 }; 711 712 void dc_sink_retain(struct dc_sink *sink); 713 void dc_sink_release(struct dc_sink *sink); 714 715 struct dc_sink_init_data { 716 enum signal_type sink_signal; 717 struct dc_link *link; 718 uint32_t dongle_max_pix_clk; 719 bool converter_disable_audio; 720 }; 721 722 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 723 724 /* Newer interfaces */ 725 struct dc_cursor { 726 struct dc_plane_address address; 727 struct dc_cursor_attributes attributes; 728 }; 729 730 731 /******************************************************************************* 732 * Interrupt interfaces 733 ******************************************************************************/ 734 enum dc_irq_source dc_interrupt_to_irq_source( 735 struct dc *dc, 736 uint32_t src_id, 737 uint32_t ext_id); 738 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 739 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 740 enum dc_irq_source dc_get_hpd_irq_source_at_index( 741 struct dc *dc, uint32_t link_index); 742 743 /******************************************************************************* 744 * Power Interfaces 745 ******************************************************************************/ 746 747 void dc_set_power_state( 748 struct dc *dc, 749 enum dc_acpi_cm_power_state power_state); 750 void dc_resume(struct dc *dc); 751 752 #endif /* DC_INTERFACE_H_ */ 753