1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.204" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 // Sizes defined as multiples of 64KB 79 enum det_size { 80 DET_SIZE_DEFAULT = 0, 81 DET_SIZE_192KB = 3, 82 DET_SIZE_256KB = 4, 83 DET_SIZE_320KB = 5, 84 DET_SIZE_384KB = 6 85 }; 86 87 88 struct dc_plane_cap { 89 enum dc_plane_type type; 90 uint32_t blends_with_above : 1; 91 uint32_t blends_with_below : 1; 92 uint32_t per_pixel_alpha : 1; 93 struct { 94 uint32_t argb8888 : 1; 95 uint32_t nv12 : 1; 96 uint32_t fp16 : 1; 97 uint32_t p010 : 1; 98 uint32_t ayuv : 1; 99 } pixel_format_support; 100 // max upscaling factor x1000 101 // upscaling factors are always >= 1 102 // for example, 1080p -> 8K is 4.0, or 4000 raw value 103 struct { 104 uint32_t argb8888; 105 uint32_t nv12; 106 uint32_t fp16; 107 } max_upscale_factor; 108 // max downscale factor x1000 109 // downscale factors are always <= 1 110 // for example, 8K -> 1080p is 0.25, or 250 raw value 111 struct { 112 uint32_t argb8888; 113 uint32_t nv12; 114 uint32_t fp16; 115 } max_downscale_factor; 116 // minimal width/height 117 uint32_t min_width; 118 uint32_t min_height; 119 }; 120 121 /** 122 * DOC: color-management-caps 123 * 124 * **Color management caps (DPP and MPC)** 125 * 126 * Modules/color calculates various color operations which are translated to 127 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 128 * DCN1, every new generation comes with fairly major differences in color 129 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 130 * decide mapping to HW block based on logical capabilities. 131 */ 132 133 /** 134 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 135 * @srgb: RGB color space transfer func 136 * @bt2020: BT.2020 transfer func 137 * @gamma2_2: standard gamma 138 * @pq: perceptual quantizer transfer function 139 * @hlg: hybrid log–gamma transfer function 140 */ 141 struct rom_curve_caps { 142 uint16_t srgb : 1; 143 uint16_t bt2020 : 1; 144 uint16_t gamma2_2 : 1; 145 uint16_t pq : 1; 146 uint16_t hlg : 1; 147 }; 148 149 /** 150 * struct dpp_color_caps - color pipeline capabilities for display pipe and 151 * plane blocks 152 * 153 * @dcn_arch: all DCE generations treated the same 154 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 155 * just plain 256-entry lookup 156 * @icsc: input color space conversion 157 * @dgam_ram: programmable degamma LUT 158 * @post_csc: post color space conversion, before gamut remap 159 * @gamma_corr: degamma correction 160 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 161 * with MPC by setting mpc:shared_3d_lut flag 162 * @ogam_ram: programmable out/blend gamma LUT 163 * @ocsc: output color space conversion 164 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 165 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 166 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 167 * 168 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 169 */ 170 struct dpp_color_caps { 171 uint16_t dcn_arch : 1; 172 uint16_t input_lut_shared : 1; 173 uint16_t icsc : 1; 174 uint16_t dgam_ram : 1; 175 uint16_t post_csc : 1; 176 uint16_t gamma_corr : 1; 177 uint16_t hw_3d_lut : 1; 178 uint16_t ogam_ram : 1; 179 uint16_t ocsc : 1; 180 uint16_t dgam_rom_for_yuv : 1; 181 struct rom_curve_caps dgam_rom_caps; 182 struct rom_curve_caps ogam_rom_caps; 183 }; 184 185 /** 186 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 187 * plane combined blocks 188 * 189 * @gamut_remap: color transformation matrix 190 * @ogam_ram: programmable out gamma LUT 191 * @ocsc: output color space conversion matrix 192 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 193 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 194 * instance 195 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 196 */ 197 struct mpc_color_caps { 198 uint16_t gamut_remap : 1; 199 uint16_t ogam_ram : 1; 200 uint16_t ocsc : 1; 201 uint16_t num_3dluts : 3; 202 uint16_t shared_3d_lut:1; 203 struct rom_curve_caps ogam_rom_caps; 204 }; 205 206 /** 207 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 208 * @dpp: color pipes caps for DPP 209 * @mpc: color pipes caps for MPC 210 */ 211 struct dc_color_caps { 212 struct dpp_color_caps dpp; 213 struct mpc_color_caps mpc; 214 }; 215 216 struct dc_dmub_caps { 217 bool psr; 218 bool mclk_sw; 219 }; 220 221 struct dc_caps { 222 uint32_t max_streams; 223 uint32_t max_links; 224 uint32_t max_audios; 225 uint32_t max_slave_planes; 226 uint32_t max_slave_yuv_planes; 227 uint32_t max_slave_rgb_planes; 228 uint32_t max_planes; 229 uint32_t max_downscale_ratio; 230 uint32_t i2c_speed_in_khz; 231 uint32_t i2c_speed_in_khz_hdcp; 232 uint32_t dmdata_alloc_size; 233 unsigned int max_cursor_size; 234 unsigned int max_video_width; 235 unsigned int min_horizontal_blanking_period; 236 int linear_pitch_alignment; 237 bool dcc_const_color; 238 bool dynamic_audio; 239 bool is_apu; 240 bool dual_link_dvi; 241 bool post_blend_color_processing; 242 bool force_dp_tps4_for_cp2520; 243 bool disable_dp_clk_share; 244 bool psp_setup_panel_mode; 245 bool extended_aux_timeout_support; 246 bool dmcub_support; 247 bool zstate_support; 248 uint32_t num_of_internal_disp; 249 enum dp_protocol_version max_dp_protocol_version; 250 unsigned int mall_size_per_mem_channel; 251 unsigned int mall_size_total; 252 unsigned int cursor_cache_size; 253 struct dc_plane_cap planes[MAX_PLANES]; 254 struct dc_color_caps color; 255 struct dc_dmub_caps dmub_caps; 256 bool dp_hpo; 257 bool dp_hdmi21_pcon_support; 258 bool edp_dsc_support; 259 bool vbios_lttpr_aware; 260 bool vbios_lttpr_enable; 261 uint32_t max_otg_num; 262 uint32_t max_cab_allocation_bytes; 263 uint32_t cache_line_size; 264 uint32_t cache_num_ways; 265 uint16_t subvp_fw_processing_delay_us; 266 uint16_t subvp_prefetch_end_to_mall_start_us; 267 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 268 uint16_t subvp_pstate_allow_width_us; 269 uint16_t subvp_vertical_int_margin_us; 270 bool seamless_odm; 271 }; 272 273 struct dc_bug_wa { 274 bool no_connect_phy_config; 275 bool dedcn20_305_wa; 276 bool skip_clock_update; 277 bool lt_early_cr_pattern; 278 }; 279 280 struct dc_dcc_surface_param { 281 struct dc_size surface_size; 282 enum surface_pixel_format format; 283 enum swizzle_mode_values swizzle_mode; 284 enum dc_scan_direction scan; 285 }; 286 287 struct dc_dcc_setting { 288 unsigned int max_compressed_blk_size; 289 unsigned int max_uncompressed_blk_size; 290 bool independent_64b_blks; 291 //These bitfields to be used starting with DCN 292 struct { 293 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 294 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 295 uint32_t dcc_256_128_128 : 1; //available starting with DCN 296 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 297 } dcc_controls; 298 }; 299 300 struct dc_surface_dcc_cap { 301 union { 302 struct { 303 struct dc_dcc_setting rgb; 304 } grph; 305 306 struct { 307 struct dc_dcc_setting luma; 308 struct dc_dcc_setting chroma; 309 } video; 310 }; 311 312 bool capable; 313 bool const_color_support; 314 }; 315 316 struct dc_static_screen_params { 317 struct { 318 bool force_trigger; 319 bool cursor_update; 320 bool surface_update; 321 bool overlay_update; 322 } triggers; 323 unsigned int num_frames; 324 }; 325 326 327 /* Surface update type is used by dc_update_surfaces_and_stream 328 * The update type is determined at the very beginning of the function based 329 * on parameters passed in and decides how much programming (or updating) is 330 * going to be done during the call. 331 * 332 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 333 * logical calculations or hardware register programming. This update MUST be 334 * ISR safe on windows. Currently fast update will only be used to flip surface 335 * address. 336 * 337 * UPDATE_TYPE_MED is used for slower updates which require significant hw 338 * re-programming however do not affect bandwidth consumption or clock 339 * requirements. At present, this is the level at which front end updates 340 * that do not require us to run bw_calcs happen. These are in/out transfer func 341 * updates, viewport offset changes, recout size changes and pixel depth changes. 342 * This update can be done at ISR, but we want to minimize how often this happens. 343 * 344 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 345 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 346 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 347 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 348 * a full update. This cannot be done at ISR level and should be a rare event. 349 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 350 * underscan we don't expect to see this call at all. 351 */ 352 353 enum surface_update_type { 354 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 355 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 356 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 357 }; 358 359 /* Forward declaration*/ 360 struct dc; 361 struct dc_plane_state; 362 struct dc_state; 363 364 365 struct dc_cap_funcs { 366 bool (*get_dcc_compression_cap)(const struct dc *dc, 367 const struct dc_dcc_surface_param *input, 368 struct dc_surface_dcc_cap *output); 369 }; 370 371 struct link_training_settings; 372 373 union allow_lttpr_non_transparent_mode { 374 struct { 375 bool DP1_4A : 1; 376 bool DP2_0 : 1; 377 } bits; 378 unsigned char raw; 379 }; 380 381 /* Structure to hold configuration flags set by dm at dc creation. */ 382 struct dc_config { 383 bool gpu_vm_support; 384 bool disable_disp_pll_sharing; 385 bool fbc_support; 386 bool disable_fractional_pwm; 387 bool allow_seamless_boot_optimization; 388 bool seamless_boot_edp_requested; 389 bool edp_not_connected; 390 bool edp_no_power_sequencing; 391 bool force_enum_edp; 392 bool forced_clocks; 393 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 394 bool multi_mon_pp_mclk_switch; 395 bool disable_dmcu; 396 bool enable_4to1MPC; 397 bool enable_windowed_mpo_odm; 398 uint32_t allow_edp_hotplug_detection; 399 bool clamp_min_dcfclk; 400 uint64_t vblank_alignment_dto_params; 401 uint8_t vblank_alignment_max_frame_time_diff; 402 bool is_asymmetric_memory; 403 bool is_single_rank_dimm; 404 bool is_vmin_only_asic; 405 bool use_pipe_ctx_sync_logic; 406 bool ignore_dpref_ss; 407 bool enable_mipi_converter_optimization; 408 bool use_default_clock_table; 409 }; 410 411 enum visual_confirm { 412 VISUAL_CONFIRM_DISABLE = 0, 413 VISUAL_CONFIRM_SURFACE = 1, 414 VISUAL_CONFIRM_HDR = 2, 415 VISUAL_CONFIRM_MPCTREE = 4, 416 VISUAL_CONFIRM_PSR = 5, 417 VISUAL_CONFIRM_SWAPCHAIN = 6, 418 VISUAL_CONFIRM_FAMS = 7, 419 VISUAL_CONFIRM_SWIZZLE = 9, 420 VISUAL_CONFIRM_SUBVP = 14, 421 }; 422 423 enum dc_psr_power_opts { 424 psr_power_opt_invalid = 0x0, 425 psr_power_opt_smu_opt_static_screen = 0x1, 426 psr_power_opt_z10_static_screen = 0x10, 427 psr_power_opt_ds_disable_allow = 0x100, 428 }; 429 430 enum dml_hostvm_override_opts { 431 DML_HOSTVM_NO_OVERRIDE = 0x0, 432 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 433 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 434 }; 435 436 enum dcc_option { 437 DCC_ENABLE = 0, 438 DCC_DISABLE = 1, 439 DCC_HALF_REQ_DISALBE = 2, 440 }; 441 442 /** 443 * enum pipe_split_policy - Pipe split strategy supported by DCN 444 * 445 * This enum is used to define the pipe split policy supported by DCN. By 446 * default, DC favors MPC_SPLIT_DYNAMIC. 447 */ 448 enum pipe_split_policy { 449 /** 450 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 451 * pipe in order to bring the best trade-off between performance and 452 * power consumption. This is the recommended option. 453 */ 454 MPC_SPLIT_DYNAMIC = 0, 455 456 /** 457 * @MPC_SPLIT_DYNAMIC: Avoid pipe split, which means that DC will not 458 * try any sort of split optimization. 459 */ 460 MPC_SPLIT_AVOID = 1, 461 462 /** 463 * @MPC_SPLIT_DYNAMIC: With this option, DC will only try to optimize 464 * the pipe utilization when using a single display; if the user 465 * connects to a second display, DC will avoid pipe split. 466 */ 467 MPC_SPLIT_AVOID_MULT_DISP = 2, 468 }; 469 470 enum wm_report_mode { 471 WM_REPORT_DEFAULT = 0, 472 WM_REPORT_OVERRIDE = 1, 473 }; 474 enum dtm_pstate{ 475 dtm_level_p0 = 0,/*highest voltage*/ 476 dtm_level_p1, 477 dtm_level_p2, 478 dtm_level_p3, 479 dtm_level_p4,/*when active_display_count = 0*/ 480 }; 481 482 enum dcn_pwr_state { 483 DCN_PWR_STATE_UNKNOWN = -1, 484 DCN_PWR_STATE_MISSION_MODE = 0, 485 DCN_PWR_STATE_LOW_POWER = 3, 486 }; 487 488 enum dcn_zstate_support_state { 489 DCN_ZSTATE_SUPPORT_UNKNOWN, 490 DCN_ZSTATE_SUPPORT_ALLOW, 491 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 492 DCN_ZSTATE_SUPPORT_DISALLOW, 493 }; 494 /* 495 * For any clocks that may differ per pipe 496 * only the max is stored in this structure 497 */ 498 struct dc_clocks { 499 int dispclk_khz; 500 int actual_dispclk_khz; 501 int dppclk_khz; 502 int actual_dppclk_khz; 503 int disp_dpp_voltage_level_khz; 504 int dcfclk_khz; 505 int socclk_khz; 506 int dcfclk_deep_sleep_khz; 507 int fclk_khz; 508 int phyclk_khz; 509 int dramclk_khz; 510 bool p_state_change_support; 511 enum dcn_zstate_support_state zstate_support; 512 bool dtbclk_en; 513 int ref_dtbclk_khz; 514 bool fclk_p_state_change_support; 515 enum dcn_pwr_state pwr_state; 516 /* 517 * Elements below are not compared for the purposes of 518 * optimization required 519 */ 520 bool prev_p_state_change_support; 521 bool fclk_prev_p_state_change_support; 522 int num_ways; 523 bool fw_based_mclk_switching; 524 bool fw_based_mclk_switching_shut_down; 525 int prev_num_ways; 526 enum dtm_pstate dtm_level; 527 int max_supported_dppclk_khz; 528 int max_supported_dispclk_khz; 529 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 530 int bw_dispclk_khz; 531 }; 532 533 struct dc_bw_validation_profile { 534 bool enable; 535 536 unsigned long long total_ticks; 537 unsigned long long voltage_level_ticks; 538 unsigned long long watermark_ticks; 539 unsigned long long rq_dlg_ticks; 540 541 unsigned long long total_count; 542 unsigned long long skip_fast_count; 543 unsigned long long skip_pass_count; 544 unsigned long long skip_fail_count; 545 }; 546 547 #define BW_VAL_TRACE_SETUP() \ 548 unsigned long long end_tick = 0; \ 549 unsigned long long voltage_level_tick = 0; \ 550 unsigned long long watermark_tick = 0; \ 551 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 552 dm_get_timestamp(dc->ctx) : 0 553 554 #define BW_VAL_TRACE_COUNT() \ 555 if (dc->debug.bw_val_profile.enable) \ 556 dc->debug.bw_val_profile.total_count++ 557 558 #define BW_VAL_TRACE_SKIP(status) \ 559 if (dc->debug.bw_val_profile.enable) { \ 560 if (!voltage_level_tick) \ 561 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 562 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 563 } 564 565 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 566 if (dc->debug.bw_val_profile.enable) \ 567 voltage_level_tick = dm_get_timestamp(dc->ctx) 568 569 #define BW_VAL_TRACE_END_WATERMARKS() \ 570 if (dc->debug.bw_val_profile.enable) \ 571 watermark_tick = dm_get_timestamp(dc->ctx) 572 573 #define BW_VAL_TRACE_FINISH() \ 574 if (dc->debug.bw_val_profile.enable) { \ 575 end_tick = dm_get_timestamp(dc->ctx); \ 576 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 577 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 578 if (watermark_tick) { \ 579 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 580 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 581 } \ 582 } 583 584 union mem_low_power_enable_options { 585 struct { 586 bool vga: 1; 587 bool i2c: 1; 588 bool dmcu: 1; 589 bool dscl: 1; 590 bool cm: 1; 591 bool mpc: 1; 592 bool optc: 1; 593 bool vpg: 1; 594 bool afmt: 1; 595 } bits; 596 uint32_t u32All; 597 }; 598 599 union root_clock_optimization_options { 600 struct { 601 bool dpp: 1; 602 bool dsc: 1; 603 bool hdmistream: 1; 604 bool hdmichar: 1; 605 bool dpstream: 1; 606 bool symclk32_se: 1; 607 bool symclk32_le: 1; 608 bool symclk_fe: 1; 609 bool physymclk: 1; 610 bool dpiasymclk: 1; 611 uint32_t reserved: 22; 612 } bits; 613 uint32_t u32All; 614 }; 615 616 union dpia_debug_options { 617 struct { 618 uint32_t disable_dpia:1; /* bit 0 */ 619 uint32_t force_non_lttpr:1; /* bit 1 */ 620 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 621 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 622 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 623 uint32_t reserved:27; 624 } bits; 625 uint32_t raw; 626 }; 627 628 /* AUX wake work around options 629 * 0: enable/disable work around 630 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 631 * 15-2: reserved 632 * 31-16: timeout in ms 633 */ 634 union aux_wake_wa_options { 635 struct { 636 uint32_t enable_wa : 1; 637 uint32_t use_default_timeout : 1; 638 uint32_t rsvd: 14; 639 uint32_t timeout_ms : 16; 640 } bits; 641 uint32_t raw; 642 }; 643 644 struct dc_debug_data { 645 uint32_t ltFailCount; 646 uint32_t i2cErrorCount; 647 uint32_t auxErrorCount; 648 }; 649 650 struct dc_phy_addr_space_config { 651 struct { 652 uint64_t start_addr; 653 uint64_t end_addr; 654 uint64_t fb_top; 655 uint64_t fb_offset; 656 uint64_t fb_base; 657 uint64_t agp_top; 658 uint64_t agp_bot; 659 uint64_t agp_base; 660 } system_aperture; 661 662 struct { 663 uint64_t page_table_start_addr; 664 uint64_t page_table_end_addr; 665 uint64_t page_table_base_addr; 666 bool base_addr_is_mc_addr; 667 } gart_config; 668 669 bool valid; 670 bool is_hvm_enabled; 671 uint64_t page_table_default_page_addr; 672 }; 673 674 struct dc_virtual_addr_space_config { 675 uint64_t page_table_base_addr; 676 uint64_t page_table_start_addr; 677 uint64_t page_table_end_addr; 678 uint32_t page_table_block_size_in_bytes; 679 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 680 }; 681 682 struct dc_bounding_box_overrides { 683 int sr_exit_time_ns; 684 int sr_enter_plus_exit_time_ns; 685 int urgent_latency_ns; 686 int percent_of_ideal_drambw; 687 int dram_clock_change_latency_ns; 688 int dummy_clock_change_latency_ns; 689 int fclk_clock_change_latency_ns; 690 /* This forces a hard min on the DCFCLK we use 691 * for DML. Unlike the debug option for forcing 692 * DCFCLK, this override affects watermark calculations 693 */ 694 int min_dcfclk_mhz; 695 }; 696 697 struct dc_state; 698 struct resource_pool; 699 struct dce_hwseq; 700 701 /** 702 * struct dc_debug_options - DC debug struct 703 * 704 * This struct provides a simple mechanism for developers to change some 705 * configurations, enable/disable features, and activate extra debug options. 706 * This can be very handy to narrow down whether some specific feature is 707 * causing an issue or not. 708 */ 709 struct dc_debug_options { 710 bool native422_support; 711 bool disable_dsc; 712 enum visual_confirm visual_confirm; 713 int visual_confirm_rect_height; 714 715 bool sanity_checks; 716 bool max_disp_clk; 717 bool surface_trace; 718 bool timing_trace; 719 bool clock_trace; 720 bool validation_trace; 721 bool bandwidth_calcs_trace; 722 int max_downscale_src_width; 723 724 /* stutter efficiency related */ 725 bool disable_stutter; 726 bool use_max_lb; 727 enum dcc_option disable_dcc; 728 729 /** 730 * @pipe_split_policy: Define which pipe split policy is used by the 731 * display core. 732 */ 733 enum pipe_split_policy pipe_split_policy; 734 bool force_single_disp_pipe_split; 735 bool voltage_align_fclk; 736 bool disable_min_fclk; 737 738 bool disable_dfs_bypass; 739 bool disable_dpp_power_gate; 740 bool disable_hubp_power_gate; 741 bool disable_dsc_power_gate; 742 int dsc_min_slice_height_override; 743 int dsc_bpp_increment_div; 744 bool disable_pplib_wm_range; 745 enum wm_report_mode pplib_wm_report_mode; 746 unsigned int min_disp_clk_khz; 747 unsigned int min_dpp_clk_khz; 748 unsigned int min_dram_clk_khz; 749 int sr_exit_time_dpm0_ns; 750 int sr_enter_plus_exit_time_dpm0_ns; 751 int sr_exit_time_ns; 752 int sr_enter_plus_exit_time_ns; 753 int urgent_latency_ns; 754 uint32_t underflow_assert_delay_us; 755 int percent_of_ideal_drambw; 756 int dram_clock_change_latency_ns; 757 bool optimized_watermark; 758 int always_scale; 759 bool disable_pplib_clock_request; 760 bool disable_clock_gate; 761 bool disable_mem_low_power; 762 bool pstate_enabled; 763 bool disable_dmcu; 764 bool disable_psr; 765 bool force_abm_enable; 766 bool disable_stereo_support; 767 bool vsr_support; 768 bool performance_trace; 769 bool az_endpoint_mute_only; 770 bool always_use_regamma; 771 bool recovery_enabled; 772 bool avoid_vbios_exec_table; 773 bool scl_reset_length10; 774 bool hdmi20_disable; 775 bool skip_detection_link_training; 776 uint32_t edid_read_retry_times; 777 unsigned int force_odm_combine; //bit vector based on otg inst 778 unsigned int seamless_boot_odm_combine; 779 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 780 bool disable_z9_mpc; 781 unsigned int force_fclk_khz; 782 bool enable_tri_buf; 783 bool dmub_offload_enabled; 784 bool dmcub_emulation; 785 bool disable_idle_power_optimizations; 786 unsigned int mall_size_override; 787 unsigned int mall_additional_timer_percent; 788 bool mall_error_as_fatal; 789 bool dmub_command_table; /* for testing only */ 790 struct dc_bw_validation_profile bw_val_profile; 791 bool disable_fec; 792 bool disable_48mhz_pwrdwn; 793 /* This forces a hard min on the DCFCLK requested to SMU/PP 794 * watermarks are not affected. 795 */ 796 unsigned int force_min_dcfclk_mhz; 797 int dwb_fi_phase; 798 bool disable_timing_sync; 799 bool cm_in_bypass; 800 int force_clock_mode;/*every mode change.*/ 801 802 bool disable_dram_clock_change_vactive_support; 803 bool validate_dml_output; 804 bool enable_dmcub_surface_flip; 805 bool usbc_combo_phy_reset_wa; 806 bool enable_dram_clock_change_one_display_vactive; 807 /* TODO - remove once tested */ 808 bool legacy_dp2_lt; 809 bool set_mst_en_for_sst; 810 bool disable_uhbr; 811 bool force_dp2_lt_fallback_method; 812 bool ignore_cable_id; 813 union mem_low_power_enable_options enable_mem_low_power; 814 union root_clock_optimization_options root_clock_optimization; 815 bool hpo_optimization; 816 bool force_vblank_alignment; 817 818 /* Enable dmub aux for legacy ddc */ 819 bool enable_dmub_aux_for_legacy_ddc; 820 bool disable_fams; 821 bool optimize_edp_link_rate; /* eDP ILR */ 822 /* FEC/PSR1 sequence enable delay in 100us */ 823 uint8_t fec_enable_delay_in100us; 824 bool enable_driver_sequence_debug; 825 enum det_size crb_alloc_policy; 826 int crb_alloc_policy_min_disp_count; 827 bool disable_z10; 828 bool enable_z9_disable_interface; 829 union dpia_debug_options dpia_debug; 830 bool disable_fixed_vs_aux_timeout_wa; 831 bool force_disable_subvp; 832 bool force_subvp_mclk_switch; 833 bool allow_sw_cursor_fallback; 834 unsigned int force_subvp_num_ways; 835 bool alloc_extra_way_for_cursor; 836 bool force_usr_allow; 837 /* uses value at boot and disables switch */ 838 bool disable_dtb_ref_clk_switch; 839 uint32_t fixed_vs_aux_delay_config_wa; 840 bool extended_blank_optimization; 841 union aux_wake_wa_options aux_wake_wa; 842 uint32_t mst_start_top_delay; 843 uint8_t psr_power_use_phy_fsm; 844 enum dml_hostvm_override_opts dml_hostvm_override; 845 bool dml_disallow_alternate_prefetch_modes; 846 bool use_legacy_soc_bb_mechanism; 847 bool exit_idle_opt_for_cursor_updates; 848 bool enable_single_display_2to1_odm_policy; 849 bool enable_dp_dig_pixel_rate_div_policy; 850 enum lttpr_mode lttpr_mode_override; 851 }; 852 853 struct gpu_info_soc_bounding_box_v1_0; 854 struct dc { 855 struct dc_debug_options debug; 856 struct dc_versions versions; 857 struct dc_caps caps; 858 struct dc_cap_funcs cap_funcs; 859 struct dc_config config; 860 struct dc_bounding_box_overrides bb_overrides; 861 struct dc_bug_wa work_arounds; 862 struct dc_context *ctx; 863 struct dc_phy_addr_space_config vm_pa_config; 864 865 uint8_t link_count; 866 struct dc_link *links[MAX_PIPES * 2]; 867 868 struct dc_state *current_state; 869 struct resource_pool *res_pool; 870 871 struct clk_mgr *clk_mgr; 872 873 /* Display Engine Clock levels */ 874 struct dm_pp_clock_levels sclk_lvls; 875 876 /* Inputs into BW and WM calculations. */ 877 struct bw_calcs_dceip *bw_dceip; 878 struct bw_calcs_vbios *bw_vbios; 879 struct dcn_soc_bounding_box *dcn_soc; 880 struct dcn_ip_params *dcn_ip; 881 struct display_mode_lib dml; 882 883 /* HW functions */ 884 struct hw_sequencer_funcs hwss; 885 struct dce_hwseq *hwseq; 886 887 /* Require to optimize clocks and bandwidth for added/removed planes */ 888 bool optimized_required; 889 bool wm_optimized_required; 890 bool idle_optimizations_allowed; 891 bool enable_c20_dtm_b0; 892 893 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 894 895 /* FBC compressor */ 896 struct compressor *fbc_compressor; 897 898 struct dc_debug_data debug_data; 899 struct dpcd_vendor_signature vendor_signature; 900 901 const char *build_id; 902 struct vm_helper *vm_helper; 903 904 uint32_t *dcn_reg_offsets; 905 uint32_t *nbio_reg_offsets; 906 907 /* Scratch memory */ 908 struct { 909 struct { 910 /* 911 * For matching clock_limits table in driver with table 912 * from PMFW. 913 */ 914 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 915 } update_bw_bounding_box; 916 } scratch; 917 }; 918 919 enum frame_buffer_mode { 920 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 921 FRAME_BUFFER_MODE_ZFB_ONLY, 922 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 923 } ; 924 925 struct dchub_init_data { 926 int64_t zfb_phys_addr_base; 927 int64_t zfb_mc_base_addr; 928 uint64_t zfb_size_in_byte; 929 enum frame_buffer_mode fb_mode; 930 bool dchub_initialzied; 931 bool dchub_info_valid; 932 }; 933 934 struct dc_init_data { 935 struct hw_asic_id asic_id; 936 void *driver; /* ctx */ 937 struct cgs_device *cgs_device; 938 struct dc_bounding_box_overrides bb_overrides; 939 940 int num_virtual_links; 941 /* 942 * If 'vbios_override' not NULL, it will be called instead 943 * of the real VBIOS. Intended use is Diagnostics on FPGA. 944 */ 945 struct dc_bios *vbios_override; 946 enum dce_environment dce_environment; 947 948 struct dmub_offload_funcs *dmub_if; 949 struct dc_reg_helper_state *dmub_offload; 950 951 struct dc_config flags; 952 uint64_t log_mask; 953 954 struct dpcd_vendor_signature vendor_signature; 955 bool force_smu_not_present; 956 /* 957 * IP offset for run time initializaion of register addresses 958 * 959 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 960 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 961 * before them. 962 */ 963 uint32_t *dcn_reg_offsets; 964 uint32_t *nbio_reg_offsets; 965 }; 966 967 struct dc_callback_init { 968 #ifdef CONFIG_DRM_AMD_DC_HDCP 969 struct cp_psp cp_psp; 970 #else 971 uint8_t reserved; 972 #endif 973 }; 974 975 struct dc *dc_create(const struct dc_init_data *init_params); 976 void dc_hardware_init(struct dc *dc); 977 978 int dc_get_vmid_use_vector(struct dc *dc); 979 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 980 /* Returns the number of vmids supported */ 981 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 982 void dc_init_callbacks(struct dc *dc, 983 const struct dc_callback_init *init_params); 984 void dc_deinit_callbacks(struct dc *dc); 985 void dc_destroy(struct dc **dc); 986 987 /******************************************************************************* 988 * Surface Interfaces 989 ******************************************************************************/ 990 991 enum { 992 TRANSFER_FUNC_POINTS = 1025 993 }; 994 995 struct dc_hdr_static_metadata { 996 /* display chromaticities and white point in units of 0.00001 */ 997 unsigned int chromaticity_green_x; 998 unsigned int chromaticity_green_y; 999 unsigned int chromaticity_blue_x; 1000 unsigned int chromaticity_blue_y; 1001 unsigned int chromaticity_red_x; 1002 unsigned int chromaticity_red_y; 1003 unsigned int chromaticity_white_point_x; 1004 unsigned int chromaticity_white_point_y; 1005 1006 uint32_t min_luminance; 1007 uint32_t max_luminance; 1008 uint32_t maximum_content_light_level; 1009 uint32_t maximum_frame_average_light_level; 1010 }; 1011 1012 enum dc_transfer_func_type { 1013 TF_TYPE_PREDEFINED, 1014 TF_TYPE_DISTRIBUTED_POINTS, 1015 TF_TYPE_BYPASS, 1016 TF_TYPE_HWPWL 1017 }; 1018 1019 struct dc_transfer_func_distributed_points { 1020 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1021 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1022 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1023 1024 uint16_t end_exponent; 1025 uint16_t x_point_at_y1_red; 1026 uint16_t x_point_at_y1_green; 1027 uint16_t x_point_at_y1_blue; 1028 }; 1029 1030 enum dc_transfer_func_predefined { 1031 TRANSFER_FUNCTION_SRGB, 1032 TRANSFER_FUNCTION_BT709, 1033 TRANSFER_FUNCTION_PQ, 1034 TRANSFER_FUNCTION_LINEAR, 1035 TRANSFER_FUNCTION_UNITY, 1036 TRANSFER_FUNCTION_HLG, 1037 TRANSFER_FUNCTION_HLG12, 1038 TRANSFER_FUNCTION_GAMMA22, 1039 TRANSFER_FUNCTION_GAMMA24, 1040 TRANSFER_FUNCTION_GAMMA26 1041 }; 1042 1043 1044 struct dc_transfer_func { 1045 struct kref refcount; 1046 enum dc_transfer_func_type type; 1047 enum dc_transfer_func_predefined tf; 1048 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1049 uint32_t sdr_ref_white_level; 1050 union { 1051 struct pwl_params pwl; 1052 struct dc_transfer_func_distributed_points tf_pts; 1053 }; 1054 }; 1055 1056 1057 union dc_3dlut_state { 1058 struct { 1059 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1060 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1061 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1062 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1063 uint32_t mpc_rmu1_mux:4; 1064 uint32_t mpc_rmu2_mux:4; 1065 uint32_t reserved:15; 1066 } bits; 1067 uint32_t raw; 1068 }; 1069 1070 1071 struct dc_3dlut { 1072 struct kref refcount; 1073 struct tetrahedral_params lut_3d; 1074 struct fixed31_32 hdr_multiplier; 1075 union dc_3dlut_state state; 1076 }; 1077 /* 1078 * This structure is filled in by dc_surface_get_status and contains 1079 * the last requested address and the currently active address so the called 1080 * can determine if there are any outstanding flips 1081 */ 1082 struct dc_plane_status { 1083 struct dc_plane_address requested_address; 1084 struct dc_plane_address current_address; 1085 bool is_flip_pending; 1086 bool is_right_eye; 1087 }; 1088 1089 union surface_update_flags { 1090 1091 struct { 1092 uint32_t addr_update:1; 1093 /* Medium updates */ 1094 uint32_t dcc_change:1; 1095 uint32_t color_space_change:1; 1096 uint32_t horizontal_mirror_change:1; 1097 uint32_t per_pixel_alpha_change:1; 1098 uint32_t global_alpha_change:1; 1099 uint32_t hdr_mult:1; 1100 uint32_t rotation_change:1; 1101 uint32_t swizzle_change:1; 1102 uint32_t scaling_change:1; 1103 uint32_t position_change:1; 1104 uint32_t in_transfer_func_change:1; 1105 uint32_t input_csc_change:1; 1106 uint32_t coeff_reduction_change:1; 1107 uint32_t output_tf_change:1; 1108 uint32_t pixel_format_change:1; 1109 uint32_t plane_size_change:1; 1110 uint32_t gamut_remap_change:1; 1111 1112 /* Full updates */ 1113 uint32_t new_plane:1; 1114 uint32_t bpp_change:1; 1115 uint32_t gamma_change:1; 1116 uint32_t bandwidth_change:1; 1117 uint32_t clock_change:1; 1118 uint32_t stereo_format_change:1; 1119 uint32_t lut_3d:1; 1120 uint32_t full_update:1; 1121 } bits; 1122 1123 uint32_t raw; 1124 }; 1125 1126 struct dc_plane_state { 1127 struct dc_plane_address address; 1128 struct dc_plane_flip_time time; 1129 bool triplebuffer_flips; 1130 struct scaling_taps scaling_quality; 1131 struct rect src_rect; 1132 struct rect dst_rect; 1133 struct rect clip_rect; 1134 1135 struct plane_size plane_size; 1136 union dc_tiling_info tiling_info; 1137 1138 struct dc_plane_dcc_param dcc; 1139 1140 struct dc_gamma *gamma_correction; 1141 struct dc_transfer_func *in_transfer_func; 1142 struct dc_bias_and_scale *bias_and_scale; 1143 struct dc_csc_transform input_csc_color_matrix; 1144 struct fixed31_32 coeff_reduction_factor; 1145 struct fixed31_32 hdr_mult; 1146 struct colorspace_transform gamut_remap_matrix; 1147 1148 // TODO: No longer used, remove 1149 struct dc_hdr_static_metadata hdr_static_ctx; 1150 1151 enum dc_color_space color_space; 1152 1153 struct dc_3dlut *lut3d_func; 1154 struct dc_transfer_func *in_shaper_func; 1155 struct dc_transfer_func *blend_tf; 1156 1157 struct dc_transfer_func *gamcor_tf; 1158 enum surface_pixel_format format; 1159 enum dc_rotation_angle rotation; 1160 enum plane_stereo_format stereo_format; 1161 1162 bool is_tiling_rotated; 1163 bool per_pixel_alpha; 1164 bool pre_multiplied_alpha; 1165 bool global_alpha; 1166 int global_alpha_value; 1167 bool visible; 1168 bool flip_immediate; 1169 bool horizontal_mirror; 1170 int layer_index; 1171 1172 union surface_update_flags update_flags; 1173 bool flip_int_enabled; 1174 bool skip_manual_trigger; 1175 1176 /* private to DC core */ 1177 struct dc_plane_status status; 1178 struct dc_context *ctx; 1179 1180 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1181 bool force_full_update; 1182 1183 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1184 1185 /* private to dc_surface.c */ 1186 enum dc_irq_source irq_source; 1187 struct kref refcount; 1188 struct tg_color visual_confirm_color; 1189 }; 1190 1191 struct dc_plane_info { 1192 struct plane_size plane_size; 1193 union dc_tiling_info tiling_info; 1194 struct dc_plane_dcc_param dcc; 1195 enum surface_pixel_format format; 1196 enum dc_rotation_angle rotation; 1197 enum plane_stereo_format stereo_format; 1198 enum dc_color_space color_space; 1199 bool horizontal_mirror; 1200 bool visible; 1201 bool per_pixel_alpha; 1202 bool pre_multiplied_alpha; 1203 bool global_alpha; 1204 int global_alpha_value; 1205 bool input_csc_enabled; 1206 int layer_index; 1207 }; 1208 1209 struct dc_scaling_info { 1210 struct rect src_rect; 1211 struct rect dst_rect; 1212 struct rect clip_rect; 1213 struct scaling_taps scaling_quality; 1214 }; 1215 1216 struct dc_surface_update { 1217 struct dc_plane_state *surface; 1218 1219 /* isr safe update parameters. null means no updates */ 1220 const struct dc_flip_addrs *flip_addr; 1221 const struct dc_plane_info *plane_info; 1222 const struct dc_scaling_info *scaling_info; 1223 struct fixed31_32 hdr_mult; 1224 /* following updates require alloc/sleep/spin that is not isr safe, 1225 * null means no updates 1226 */ 1227 const struct dc_gamma *gamma; 1228 const struct dc_transfer_func *in_transfer_func; 1229 1230 const struct dc_csc_transform *input_csc_color_matrix; 1231 const struct fixed31_32 *coeff_reduction_factor; 1232 const struct dc_transfer_func *func_shaper; 1233 const struct dc_3dlut *lut3d_func; 1234 const struct dc_transfer_func *blend_tf; 1235 const struct colorspace_transform *gamut_remap_matrix; 1236 }; 1237 1238 /* 1239 * Create a new surface with default parameters; 1240 */ 1241 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1242 const struct dc_plane_status *dc_plane_get_status( 1243 const struct dc_plane_state *plane_state); 1244 1245 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1246 void dc_plane_state_release(struct dc_plane_state *plane_state); 1247 1248 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1249 void dc_gamma_release(struct dc_gamma **dc_gamma); 1250 struct dc_gamma *dc_create_gamma(void); 1251 1252 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1253 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1254 struct dc_transfer_func *dc_create_transfer_func(void); 1255 1256 struct dc_3dlut *dc_create_3dlut_func(void); 1257 void dc_3dlut_func_release(struct dc_3dlut *lut); 1258 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1259 1260 void dc_post_update_surfaces_to_stream( 1261 struct dc *dc); 1262 1263 #include "dc_stream.h" 1264 1265 /* 1266 * Structure to store surface/stream associations for validation 1267 */ 1268 struct dc_validation_set { 1269 struct dc_stream_state *stream; 1270 struct dc_plane_state *plane_states[MAX_SURFACES]; 1271 uint8_t plane_count; 1272 }; 1273 1274 bool dc_validate_boot_timing(const struct dc *dc, 1275 const struct dc_sink *sink, 1276 struct dc_crtc_timing *crtc_timing); 1277 1278 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1279 1280 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1281 1282 bool dc_set_generic_gpio_for_stereo(bool enable, 1283 struct gpio_service *gpio_service); 1284 1285 /* 1286 * fast_validate: we return after determining if we can support the new state, 1287 * but before we populate the programming info 1288 */ 1289 enum dc_status dc_validate_global_state( 1290 struct dc *dc, 1291 struct dc_state *new_ctx, 1292 bool fast_validate); 1293 1294 1295 void dc_resource_state_construct( 1296 const struct dc *dc, 1297 struct dc_state *dst_ctx); 1298 1299 bool dc_acquire_release_mpc_3dlut( 1300 struct dc *dc, bool acquire, 1301 struct dc_stream_state *stream, 1302 struct dc_3dlut **lut, 1303 struct dc_transfer_func **shaper); 1304 1305 void dc_resource_state_copy_construct( 1306 const struct dc_state *src_ctx, 1307 struct dc_state *dst_ctx); 1308 1309 void dc_resource_state_copy_construct_current( 1310 const struct dc *dc, 1311 struct dc_state *dst_ctx); 1312 1313 void dc_resource_state_destruct(struct dc_state *context); 1314 1315 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1316 1317 /* 1318 * TODO update to make it about validation sets 1319 * Set up streams and links associated to drive sinks 1320 * The streams parameter is an absolute set of all active streams. 1321 * 1322 * After this call: 1323 * Phy, Encoder, Timing Generator are programmed and enabled. 1324 * New streams are enabled with blank stream; no memory read. 1325 */ 1326 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1327 1328 struct dc_state *dc_create_state(struct dc *dc); 1329 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1330 void dc_retain_state(struct dc_state *context); 1331 void dc_release_state(struct dc_state *context); 1332 1333 /******************************************************************************* 1334 * Link Interfaces 1335 ******************************************************************************/ 1336 1337 struct dpcd_caps { 1338 union dpcd_rev dpcd_rev; 1339 union max_lane_count max_ln_count; 1340 union max_down_spread max_down_spread; 1341 union dprx_feature dprx_feature; 1342 1343 /* valid only for eDP v1.4 or higher*/ 1344 uint8_t edp_supported_link_rates_count; 1345 enum dc_link_rate edp_supported_link_rates[8]; 1346 1347 /* dongle type (DP converter, CV smart dongle) */ 1348 enum display_dongle_type dongle_type; 1349 bool is_dongle_type_one; 1350 /* branch device or sink device */ 1351 bool is_branch_dev; 1352 /* Dongle's downstream count. */ 1353 union sink_count sink_count; 1354 bool is_mst_capable; 1355 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1356 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1357 struct dc_dongle_caps dongle_caps; 1358 1359 uint32_t sink_dev_id; 1360 int8_t sink_dev_id_str[6]; 1361 int8_t sink_hw_revision; 1362 int8_t sink_fw_revision[2]; 1363 1364 uint32_t branch_dev_id; 1365 int8_t branch_dev_name[6]; 1366 int8_t branch_hw_revision; 1367 int8_t branch_fw_revision[2]; 1368 1369 bool allow_invalid_MSA_timing_param; 1370 bool panel_mode_edp; 1371 bool dpcd_display_control_capable; 1372 bool ext_receiver_cap_field_present; 1373 bool set_power_state_capable_edp; 1374 bool dynamic_backlight_capable_edp; 1375 union dpcd_fec_capability fec_cap; 1376 struct dpcd_dsc_capabilities dsc_caps; 1377 struct dc_lttpr_caps lttpr_caps; 1378 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1379 1380 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1381 union dp_main_line_channel_coding_cap channel_coding_cap; 1382 union dp_sink_video_fallback_formats fallback_formats; 1383 union dp_fec_capability1 fec_cap1; 1384 union dp_cable_id cable_id; 1385 uint8_t edp_rev; 1386 union edp_alpm_caps alpm_caps; 1387 struct edp_psr_info psr_info; 1388 }; 1389 1390 union dpcd_sink_ext_caps { 1391 struct { 1392 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1393 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1394 */ 1395 uint8_t sdr_aux_backlight_control : 1; 1396 uint8_t hdr_aux_backlight_control : 1; 1397 uint8_t reserved_1 : 2; 1398 uint8_t oled : 1; 1399 uint8_t reserved : 3; 1400 } bits; 1401 uint8_t raw; 1402 }; 1403 1404 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1405 union hdcp_rx_caps { 1406 struct { 1407 uint8_t version; 1408 uint8_t reserved; 1409 struct { 1410 uint8_t repeater : 1; 1411 uint8_t hdcp_capable : 1; 1412 uint8_t reserved : 6; 1413 } byte0; 1414 } fields; 1415 uint8_t raw[3]; 1416 }; 1417 1418 union hdcp_bcaps { 1419 struct { 1420 uint8_t HDCP_CAPABLE:1; 1421 uint8_t REPEATER:1; 1422 uint8_t RESERVED:6; 1423 } bits; 1424 uint8_t raw; 1425 }; 1426 1427 struct hdcp_caps { 1428 union hdcp_rx_caps rx_caps; 1429 union hdcp_bcaps bcaps; 1430 }; 1431 #endif 1432 1433 #include "dc_link.h" 1434 1435 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1436 1437 /******************************************************************************* 1438 * Sink Interfaces - A sink corresponds to a display output device 1439 ******************************************************************************/ 1440 1441 struct dc_container_id { 1442 // 128bit GUID in binary form 1443 unsigned char guid[16]; 1444 // 8 byte port ID -> ELD.PortID 1445 unsigned int portId[2]; 1446 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1447 unsigned short manufacturerName; 1448 // 2 byte product code -> ELD.ProductCode 1449 unsigned short productCode; 1450 }; 1451 1452 1453 struct dc_sink_dsc_caps { 1454 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1455 // 'false' if they are sink's DSC caps 1456 bool is_virtual_dpcd_dsc; 1457 #if defined(CONFIG_DRM_AMD_DC_DCN) 1458 // 'true' if MST topology supports DSC passthrough for sink 1459 // 'false' if MST topology does not support DSC passthrough 1460 bool is_dsc_passthrough_supported; 1461 #endif 1462 struct dsc_dec_dpcd_caps dsc_dec_caps; 1463 }; 1464 1465 struct dc_sink_fec_caps { 1466 bool is_rx_fec_supported; 1467 bool is_topology_fec_supported; 1468 }; 1469 1470 /* 1471 * The sink structure contains EDID and other display device properties 1472 */ 1473 struct dc_sink { 1474 enum signal_type sink_signal; 1475 struct dc_edid dc_edid; /* raw edid */ 1476 struct dc_edid_caps edid_caps; /* parse display caps */ 1477 struct dc_container_id *dc_container_id; 1478 uint32_t dongle_max_pix_clk; 1479 void *priv; 1480 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1481 bool converter_disable_audio; 1482 1483 struct dc_sink_dsc_caps dsc_caps; 1484 struct dc_sink_fec_caps fec_caps; 1485 1486 bool is_vsc_sdp_colorimetry_supported; 1487 1488 /* private to DC core */ 1489 struct dc_link *link; 1490 struct dc_context *ctx; 1491 1492 uint32_t sink_id; 1493 1494 /* private to dc_sink.c */ 1495 // refcount must be the last member in dc_sink, since we want the 1496 // sink structure to be logically cloneable up to (but not including) 1497 // refcount 1498 struct kref refcount; 1499 }; 1500 1501 void dc_sink_retain(struct dc_sink *sink); 1502 void dc_sink_release(struct dc_sink *sink); 1503 1504 struct dc_sink_init_data { 1505 enum signal_type sink_signal; 1506 struct dc_link *link; 1507 uint32_t dongle_max_pix_clk; 1508 bool converter_disable_audio; 1509 }; 1510 1511 bool dc_extended_blank_supported(struct dc *dc); 1512 1513 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1514 1515 /* Newer interfaces */ 1516 struct dc_cursor { 1517 struct dc_plane_address address; 1518 struct dc_cursor_attributes attributes; 1519 }; 1520 1521 1522 /******************************************************************************* 1523 * Interrupt interfaces 1524 ******************************************************************************/ 1525 enum dc_irq_source dc_interrupt_to_irq_source( 1526 struct dc *dc, 1527 uint32_t src_id, 1528 uint32_t ext_id); 1529 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1530 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1531 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1532 struct dc *dc, uint32_t link_index); 1533 1534 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1535 1536 /******************************************************************************* 1537 * Power Interfaces 1538 ******************************************************************************/ 1539 1540 void dc_set_power_state( 1541 struct dc *dc, 1542 enum dc_acpi_cm_power_state power_state); 1543 void dc_resume(struct dc *dc); 1544 1545 void dc_power_down_on_boot(struct dc *dc); 1546 1547 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1548 /* 1549 * HDCP Interfaces 1550 */ 1551 enum hdcp_message_status dc_process_hdcp_msg( 1552 enum signal_type signal, 1553 struct dc_link *link, 1554 struct hdcp_protection_message *message_info); 1555 #endif 1556 bool dc_is_dmcu_initialized(struct dc *dc); 1557 1558 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1559 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1560 1561 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1562 struct dc_cursor_attributes *cursor_attr); 1563 1564 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1565 1566 /* set min and max memory clock to lowest and highest DPM level, respectively */ 1567 void dc_unlock_memory_clock_frequency(struct dc *dc); 1568 1569 /* set min memory clock to the min required for current mode, max to maxDPM */ 1570 void dc_lock_memory_clock_frequency(struct dc *dc); 1571 1572 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1573 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1574 1575 /* cleanup on driver unload */ 1576 void dc_hardware_release(struct dc *dc); 1577 1578 /* disables fw based mclk switch */ 1579 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 1580 1581 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1582 void dc_z10_restore(const struct dc *dc); 1583 void dc_z10_save_init(struct dc *dc); 1584 1585 bool dc_is_dmub_outbox_supported(struct dc *dc); 1586 bool dc_enable_dmub_notifications(struct dc *dc); 1587 1588 void dc_enable_dmub_outbox(struct dc *dc); 1589 1590 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1591 uint32_t link_index, 1592 struct aux_payload *payload); 1593 1594 /* Get dc link index from dpia port index */ 1595 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1596 uint8_t dpia_port_index); 1597 1598 bool dc_process_dmub_set_config_async(struct dc *dc, 1599 uint32_t link_index, 1600 struct set_config_cmd_payload *payload, 1601 struct dmub_notification *notify); 1602 1603 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1604 uint32_t link_index, 1605 uint8_t mst_alloc_slots, 1606 uint8_t *mst_slots_in_use); 1607 1608 /******************************************************************************* 1609 * DSC Interfaces 1610 ******************************************************************************/ 1611 #include "dc_dsc.h" 1612 1613 /******************************************************************************* 1614 * Disable acc mode Interfaces 1615 ******************************************************************************/ 1616 void dc_disable_accelerated_mode(struct dc *dc); 1617 1618 #endif /* DC_INTERFACE_H_ */ 1619