1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "dml/display_mode_lib.h" 40 41 #define DC_VER "3.1.44" 42 43 #define MAX_SURFACES 3 44 #define MAX_STREAMS 6 45 #define MAX_SINKS_PER_LINK 4 46 47 48 /******************************************************************************* 49 * Display Core Interfaces 50 ******************************************************************************/ 51 struct dmcu_version { 52 unsigned int date; 53 unsigned int month; 54 unsigned int year; 55 unsigned int interface_version; 56 }; 57 58 struct dc_versions { 59 const char *dc_ver; 60 struct dmcu_version dmcu_version; 61 }; 62 63 struct dc_caps { 64 uint32_t max_streams; 65 uint32_t max_links; 66 uint32_t max_audios; 67 uint32_t max_slave_planes; 68 uint32_t max_planes; 69 uint32_t max_downscale_ratio; 70 uint32_t i2c_speed_in_khz; 71 unsigned int max_cursor_size; 72 unsigned int max_video_width; 73 int linear_pitch_alignment; 74 bool dcc_const_color; 75 bool dynamic_audio; 76 bool is_apu; 77 bool dual_link_dvi; 78 bool post_blend_color_processing; 79 }; 80 81 struct dc_dcc_surface_param { 82 struct dc_size surface_size; 83 enum surface_pixel_format format; 84 enum swizzle_mode_values swizzle_mode; 85 enum dc_scan_direction scan; 86 }; 87 88 struct dc_dcc_setting { 89 unsigned int max_compressed_blk_size; 90 unsigned int max_uncompressed_blk_size; 91 bool independent_64b_blks; 92 }; 93 94 struct dc_surface_dcc_cap { 95 union { 96 struct { 97 struct dc_dcc_setting rgb; 98 } grph; 99 100 struct { 101 struct dc_dcc_setting luma; 102 struct dc_dcc_setting chroma; 103 } video; 104 }; 105 106 bool capable; 107 bool const_color_support; 108 }; 109 110 struct dc_static_screen_events { 111 bool force_trigger; 112 bool cursor_update; 113 bool surface_update; 114 bool overlay_update; 115 }; 116 117 118 /* Surface update type is used by dc_update_surfaces_and_stream 119 * The update type is determined at the very beginning of the function based 120 * on parameters passed in and decides how much programming (or updating) is 121 * going to be done during the call. 122 * 123 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 124 * logical calculations or hardware register programming. This update MUST be 125 * ISR safe on windows. Currently fast update will only be used to flip surface 126 * address. 127 * 128 * UPDATE_TYPE_MED is used for slower updates which require significant hw 129 * re-programming however do not affect bandwidth consumption or clock 130 * requirements. At present, this is the level at which front end updates 131 * that do not require us to run bw_calcs happen. These are in/out transfer func 132 * updates, viewport offset changes, recout size changes and pixel depth changes. 133 * This update can be done at ISR, but we want to minimize how often this happens. 134 * 135 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 136 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 137 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 138 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 139 * a full update. This cannot be done at ISR level and should be a rare event. 140 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 141 * underscan we don't expect to see this call at all. 142 */ 143 144 enum surface_update_type { 145 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 146 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 147 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 148 }; 149 150 /* Forward declaration*/ 151 struct dc; 152 struct dc_plane_state; 153 struct dc_state; 154 155 156 struct dc_cap_funcs { 157 bool (*get_dcc_compression_cap)(const struct dc *dc, 158 const struct dc_dcc_surface_param *input, 159 struct dc_surface_dcc_cap *output); 160 }; 161 162 struct link_training_settings; 163 164 165 /* Structure to hold configuration flags set by dm at dc creation. */ 166 struct dc_config { 167 bool gpu_vm_support; 168 bool disable_disp_pll_sharing; 169 }; 170 171 enum dcc_option { 172 DCC_ENABLE = 0, 173 DCC_DISABLE = 1, 174 DCC_HALF_REQ_DISALBE = 2, 175 }; 176 177 enum pipe_split_policy { 178 MPC_SPLIT_DYNAMIC = 0, 179 MPC_SPLIT_AVOID = 1, 180 MPC_SPLIT_AVOID_MULT_DISP = 2, 181 }; 182 183 enum wm_report_mode { 184 WM_REPORT_DEFAULT = 0, 185 WM_REPORT_OVERRIDE = 1, 186 }; 187 188 struct dc_clocks { 189 int dispclk_khz; 190 int max_supported_dppclk_khz; 191 int dppclk_khz; 192 int dcfclk_khz; 193 int socclk_khz; 194 int dcfclk_deep_sleep_khz; 195 int fclk_khz; 196 }; 197 198 struct dc_debug { 199 bool surface_visual_confirm; 200 bool sanity_checks; 201 bool max_disp_clk; 202 bool surface_trace; 203 bool timing_trace; 204 bool clock_trace; 205 bool validation_trace; 206 bool bandwidth_calcs_trace; 207 int max_downscale_src_width; 208 209 /* stutter efficiency related */ 210 bool disable_stutter; 211 bool use_max_lb; 212 enum dcc_option disable_dcc; 213 enum pipe_split_policy pipe_split_policy; 214 bool force_single_disp_pipe_split; 215 bool voltage_align_fclk; 216 217 bool disable_dfs_bypass; 218 bool disable_dpp_power_gate; 219 bool disable_hubp_power_gate; 220 bool disable_pplib_wm_range; 221 enum wm_report_mode pplib_wm_report_mode; 222 unsigned int min_disp_clk_khz; 223 int sr_exit_time_dpm0_ns; 224 int sr_enter_plus_exit_time_dpm0_ns; 225 int sr_exit_time_ns; 226 int sr_enter_plus_exit_time_ns; 227 int urgent_latency_ns; 228 int percent_of_ideal_drambw; 229 int dram_clock_change_latency_ns; 230 int always_scale; 231 bool disable_pplib_clock_request; 232 bool disable_clock_gate; 233 bool disable_dmcu; 234 bool disable_psr; 235 bool force_abm_enable; 236 bool disable_hbup_pg; 237 bool disable_dpp_pg; 238 bool disable_stereo_support; 239 bool vsr_support; 240 bool performance_trace; 241 bool az_endpoint_mute_only; 242 bool always_use_regamma; 243 bool p010_mpo_support; 244 bool recovery_enabled; 245 246 }; 247 struct dc_state; 248 struct resource_pool; 249 struct dce_hwseq; 250 struct dc { 251 struct dc_versions versions; 252 struct dc_caps caps; 253 struct dc_cap_funcs cap_funcs; 254 struct dc_config config; 255 struct dc_debug debug; 256 257 struct dc_context *ctx; 258 259 uint8_t link_count; 260 struct dc_link *links[MAX_PIPES * 2]; 261 262 struct dc_state *current_state; 263 struct resource_pool *res_pool; 264 265 /* Display Engine Clock levels */ 266 struct dm_pp_clock_levels sclk_lvls; 267 268 /* Inputs into BW and WM calculations. */ 269 struct bw_calcs_dceip *bw_dceip; 270 struct bw_calcs_vbios *bw_vbios; 271 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 272 struct dcn_soc_bounding_box *dcn_soc; 273 struct dcn_ip_params *dcn_ip; 274 struct display_mode_lib dml; 275 #endif 276 277 /* HW functions */ 278 struct hw_sequencer_funcs hwss; 279 struct dce_hwseq *hwseq; 280 281 /* temp store of dm_pp_display_configuration 282 * to compare to see if display config changed 283 */ 284 struct dm_pp_display_configuration prev_display_config; 285 286 bool optimized_required; 287 288 bool apply_edp_fast_boot_optimization; 289 290 /* FBC compressor */ 291 #if defined(CONFIG_DRM_AMD_DC_FBC) 292 struct compressor *fbc_compressor; 293 #endif 294 }; 295 296 enum frame_buffer_mode { 297 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 298 FRAME_BUFFER_MODE_ZFB_ONLY, 299 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 300 } ; 301 302 struct dchub_init_data { 303 int64_t zfb_phys_addr_base; 304 int64_t zfb_mc_base_addr; 305 uint64_t zfb_size_in_byte; 306 enum frame_buffer_mode fb_mode; 307 bool dchub_initialzied; 308 bool dchub_info_valid; 309 }; 310 311 struct dc_init_data { 312 struct hw_asic_id asic_id; 313 void *driver; /* ctx */ 314 struct cgs_device *cgs_device; 315 316 int num_virtual_links; 317 /* 318 * If 'vbios_override' not NULL, it will be called instead 319 * of the real VBIOS. Intended use is Diagnostics on FPGA. 320 */ 321 struct dc_bios *vbios_override; 322 enum dce_environment dce_environment; 323 324 struct dc_config flags; 325 uint32_t log_mask; 326 }; 327 328 struct dc *dc_create(const struct dc_init_data *init_params); 329 330 void dc_destroy(struct dc **dc); 331 332 /******************************************************************************* 333 * Surface Interfaces 334 ******************************************************************************/ 335 336 enum { 337 TRANSFER_FUNC_POINTS = 1025 338 }; 339 340 struct dc_hdr_static_metadata { 341 /* display chromaticities and white point in units of 0.00001 */ 342 unsigned int chromaticity_green_x; 343 unsigned int chromaticity_green_y; 344 unsigned int chromaticity_blue_x; 345 unsigned int chromaticity_blue_y; 346 unsigned int chromaticity_red_x; 347 unsigned int chromaticity_red_y; 348 unsigned int chromaticity_white_point_x; 349 unsigned int chromaticity_white_point_y; 350 351 uint32_t min_luminance; 352 uint32_t max_luminance; 353 uint32_t maximum_content_light_level; 354 uint32_t maximum_frame_average_light_level; 355 }; 356 357 enum dc_transfer_func_type { 358 TF_TYPE_PREDEFINED, 359 TF_TYPE_DISTRIBUTED_POINTS, 360 TF_TYPE_BYPASS, 361 }; 362 363 struct dc_transfer_func_distributed_points { 364 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 365 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 366 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 367 368 uint16_t end_exponent; 369 uint16_t x_point_at_y1_red; 370 uint16_t x_point_at_y1_green; 371 uint16_t x_point_at_y1_blue; 372 }; 373 374 enum dc_transfer_func_predefined { 375 TRANSFER_FUNCTION_SRGB, 376 TRANSFER_FUNCTION_BT709, 377 TRANSFER_FUNCTION_PQ, 378 TRANSFER_FUNCTION_LINEAR, 379 TRANSFER_FUNCTION_UNITY, 380 }; 381 382 struct dc_transfer_func { 383 struct kref refcount; 384 struct dc_transfer_func_distributed_points tf_pts; 385 enum dc_transfer_func_type type; 386 enum dc_transfer_func_predefined tf; 387 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 388 uint32_t sdr_ref_white_level; 389 struct dc_context *ctx; 390 }; 391 392 /* 393 * This structure is filled in by dc_surface_get_status and contains 394 * the last requested address and the currently active address so the called 395 * can determine if there are any outstanding flips 396 */ 397 struct dc_plane_status { 398 struct dc_plane_address requested_address; 399 struct dc_plane_address current_address; 400 bool is_flip_pending; 401 bool is_right_eye; 402 }; 403 404 union surface_update_flags { 405 406 struct { 407 /* Medium updates */ 408 uint32_t dcc_change:1; 409 uint32_t color_space_change:1; 410 uint32_t horizontal_mirror_change:1; 411 uint32_t per_pixel_alpha_change:1; 412 uint32_t rotation_change:1; 413 uint32_t swizzle_change:1; 414 uint32_t scaling_change:1; 415 uint32_t position_change:1; 416 uint32_t in_transfer_func_change:1; 417 uint32_t input_csc_change:1; 418 uint32_t coeff_reduction_change:1; 419 uint32_t output_tf_change:1; 420 uint32_t pixel_format_change:1; 421 422 /* Full updates */ 423 uint32_t new_plane:1; 424 uint32_t bpp_change:1; 425 uint32_t gamma_change:1; 426 uint32_t bandwidth_change:1; 427 uint32_t clock_change:1; 428 uint32_t stereo_format_change:1; 429 uint32_t full_update:1; 430 } bits; 431 432 uint32_t raw; 433 }; 434 435 struct dc_plane_state { 436 struct dc_plane_address address; 437 struct dc_plane_flip_time time; 438 struct scaling_taps scaling_quality; 439 struct rect src_rect; 440 struct rect dst_rect; 441 struct rect clip_rect; 442 443 union plane_size plane_size; 444 union dc_tiling_info tiling_info; 445 446 struct dc_plane_dcc_param dcc; 447 448 struct dc_gamma *gamma_correction; 449 struct dc_transfer_func *in_transfer_func; 450 struct dc_bias_and_scale *bias_and_scale; 451 struct dc_csc_transform input_csc_color_matrix; 452 struct fixed31_32 coeff_reduction_factor; 453 uint32_t sdr_white_level; 454 455 // TODO: No longer used, remove 456 struct dc_hdr_static_metadata hdr_static_ctx; 457 458 enum dc_color_space color_space; 459 460 enum surface_pixel_format format; 461 enum dc_rotation_angle rotation; 462 enum plane_stereo_format stereo_format; 463 464 bool is_tiling_rotated; 465 bool per_pixel_alpha; 466 bool visible; 467 bool flip_immediate; 468 bool horizontal_mirror; 469 470 union surface_update_flags update_flags; 471 /* private to DC core */ 472 struct dc_plane_status status; 473 struct dc_context *ctx; 474 475 /* private to dc_surface.c */ 476 enum dc_irq_source irq_source; 477 struct kref refcount; 478 }; 479 480 struct dc_plane_info { 481 union plane_size plane_size; 482 union dc_tiling_info tiling_info; 483 struct dc_plane_dcc_param dcc; 484 enum surface_pixel_format format; 485 enum dc_rotation_angle rotation; 486 enum plane_stereo_format stereo_format; 487 enum dc_color_space color_space; 488 unsigned int sdr_white_level; 489 bool horizontal_mirror; 490 bool visible; 491 bool per_pixel_alpha; 492 bool input_csc_enabled; 493 }; 494 495 struct dc_scaling_info { 496 struct rect src_rect; 497 struct rect dst_rect; 498 struct rect clip_rect; 499 struct scaling_taps scaling_quality; 500 }; 501 502 struct dc_surface_update { 503 struct dc_plane_state *surface; 504 505 /* isr safe update parameters. null means no updates */ 506 const struct dc_flip_addrs *flip_addr; 507 const struct dc_plane_info *plane_info; 508 const struct dc_scaling_info *scaling_info; 509 510 /* following updates require alloc/sleep/spin that is not isr safe, 511 * null means no updates 512 */ 513 const struct dc_gamma *gamma; 514 const struct dc_transfer_func *in_transfer_func; 515 516 const struct dc_csc_transform *input_csc_color_matrix; 517 const struct fixed31_32 *coeff_reduction_factor; 518 }; 519 520 /* 521 * Create a new surface with default parameters; 522 */ 523 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 524 const struct dc_plane_status *dc_plane_get_status( 525 const struct dc_plane_state *plane_state); 526 527 void dc_plane_state_retain(struct dc_plane_state *plane_state); 528 void dc_plane_state_release(struct dc_plane_state *plane_state); 529 530 void dc_gamma_retain(struct dc_gamma *dc_gamma); 531 void dc_gamma_release(struct dc_gamma **dc_gamma); 532 struct dc_gamma *dc_create_gamma(void); 533 534 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 535 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 536 struct dc_transfer_func *dc_create_transfer_func(void); 537 538 /* 539 * This structure holds a surface address. There could be multiple addresses 540 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 541 * as frame durations and DCC format can also be set. 542 */ 543 struct dc_flip_addrs { 544 struct dc_plane_address address; 545 unsigned int flip_timestamp_in_us; 546 bool flip_immediate; 547 /* TODO: add flip duration for FreeSync */ 548 }; 549 550 bool dc_post_update_surfaces_to_stream( 551 struct dc *dc); 552 553 #include "dc_stream.h" 554 555 /* 556 * Structure to store surface/stream associations for validation 557 */ 558 struct dc_validation_set { 559 struct dc_stream_state *stream; 560 struct dc_plane_state *plane_states[MAX_SURFACES]; 561 uint8_t plane_count; 562 }; 563 564 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 565 566 enum dc_status dc_validate_global_state( 567 struct dc *dc, 568 struct dc_state *new_ctx); 569 570 571 void dc_resource_state_construct( 572 const struct dc *dc, 573 struct dc_state *dst_ctx); 574 575 void dc_resource_state_copy_construct( 576 const struct dc_state *src_ctx, 577 struct dc_state *dst_ctx); 578 579 void dc_resource_state_copy_construct_current( 580 const struct dc *dc, 581 struct dc_state *dst_ctx); 582 583 void dc_resource_state_destruct(struct dc_state *context); 584 585 /* 586 * TODO update to make it about validation sets 587 * Set up streams and links associated to drive sinks 588 * The streams parameter is an absolute set of all active streams. 589 * 590 * After this call: 591 * Phy, Encoder, Timing Generator are programmed and enabled. 592 * New streams are enabled with blank stream; no memory read. 593 */ 594 bool dc_commit_state(struct dc *dc, struct dc_state *context); 595 596 597 struct dc_state *dc_create_state(void); 598 void dc_retain_state(struct dc_state *context); 599 void dc_release_state(struct dc_state *context); 600 601 /******************************************************************************* 602 * Link Interfaces 603 ******************************************************************************/ 604 605 struct dpcd_caps { 606 union dpcd_rev dpcd_rev; 607 union max_lane_count max_ln_count; 608 union max_down_spread max_down_spread; 609 610 /* dongle type (DP converter, CV smart dongle) */ 611 enum display_dongle_type dongle_type; 612 /* Dongle's downstream count. */ 613 union sink_count sink_count; 614 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 615 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 616 struct dc_dongle_caps dongle_caps; 617 618 uint32_t sink_dev_id; 619 uint32_t branch_dev_id; 620 int8_t branch_dev_name[6]; 621 int8_t branch_hw_revision; 622 623 bool allow_invalid_MSA_timing_param; 624 bool panel_mode_edp; 625 bool dpcd_display_control_capable; 626 }; 627 628 #include "dc_link.h" 629 630 /******************************************************************************* 631 * Sink Interfaces - A sink corresponds to a display output device 632 ******************************************************************************/ 633 634 struct dc_container_id { 635 // 128bit GUID in binary form 636 unsigned char guid[16]; 637 // 8 byte port ID -> ELD.PortID 638 unsigned int portId[2]; 639 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 640 unsigned short manufacturerName; 641 // 2 byte product code -> ELD.ProductCode 642 unsigned short productCode; 643 }; 644 645 646 647 /* 648 * The sink structure contains EDID and other display device properties 649 */ 650 struct dc_sink { 651 enum signal_type sink_signal; 652 struct dc_edid dc_edid; /* raw edid */ 653 struct dc_edid_caps edid_caps; /* parse display caps */ 654 struct dc_container_id *dc_container_id; 655 uint32_t dongle_max_pix_clk; 656 void *priv; 657 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 658 bool converter_disable_audio; 659 660 /* private to DC core */ 661 struct dc_link *link; 662 struct dc_context *ctx; 663 664 /* private to dc_sink.c */ 665 struct kref refcount; 666 667 }; 668 669 void dc_sink_retain(struct dc_sink *sink); 670 void dc_sink_release(struct dc_sink *sink); 671 672 struct dc_sink_init_data { 673 enum signal_type sink_signal; 674 struct dc_link *link; 675 uint32_t dongle_max_pix_clk; 676 bool converter_disable_audio; 677 }; 678 679 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 680 681 /* Newer interfaces */ 682 struct dc_cursor { 683 struct dc_plane_address address; 684 struct dc_cursor_attributes attributes; 685 }; 686 687 688 /******************************************************************************* 689 * Interrupt interfaces 690 ******************************************************************************/ 691 enum dc_irq_source dc_interrupt_to_irq_source( 692 struct dc *dc, 693 uint32_t src_id, 694 uint32_t ext_id); 695 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 696 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 697 enum dc_irq_source dc_get_hpd_irq_source_at_index( 698 struct dc *dc, uint32_t link_index); 699 700 /******************************************************************************* 701 * Power Interfaces 702 ******************************************************************************/ 703 704 void dc_set_power_state( 705 struct dc *dc, 706 enum dc_acpi_cm_power_state power_state); 707 void dc_resume(struct dc *dc); 708 709 #endif /* DC_INTERFACE_H_ */ 710